The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.
TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an
adjustment is necessary for this mainboard.
Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Enaebl the RTC driver to be used on mc_apl4.
Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: Id36e39c4568f5dd241cd864d2e75365abd0f2a91
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29882
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I4ab40e34253c20adaacfdf42050314e06547eefb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard also has a SD slot.
Change-Id: I969e8ecb27aee4c8be212e67dfe6bd807ecd3b2f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard has four connected PCIe devices. The required root ports
are switched on and configured.
Change-Id: I82b13e1d245a172762ebd689ae136a762027033f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29810
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
An additional read of PTN configuration data at the end of the
ptn3460_init function is not necessary.
Change-Id: I5f7f647242e94b1af13757d00e80ed9813d435d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The power budget for this mainboard is very limited while the
performance demand is low. Set the CPU clock to the lowest value to
enable maximum efficiency and thus lowest power dissipation.
Change-Id: I23c7c5393deb676b94f2b0ac25e21a7a44cd8cb3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl5 mainboard will follow in separate commits.
Change-Id: Icdbb116a822ffa7a3bfb7026a5d1164db56a0c46
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently, there is nothing for this mainboard to do in ramstage.
Change-Id: Id74a5f3f0a0583dc6bc81044913b8bb83d3b0b93
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is equipped with LPDDR4 modules. The corresponding memory
swizzle data must be set for this purpose.
Change-Id: I4017de0713f0df5e614086912fc39d8eb6562702
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Uwe Pöche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard also has a SD slot.
Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard also has an external RTC chip, but not on this bus. The
topic is currently in clarification and will be published with a later
patch. In a first step we enable all I2C busses.
Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable all PCIe root ports for this mainboard.
Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there are legacy PCI device, which are connected to
different PCIe root ports via PCIe-2-PCI bridges. This patch disables
the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges.
Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 and then the reset button
is pressed the PCH will drive SLP_S3 active (low).
Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is an on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
For this mainboard the correction of transmit voltage swing from SATA
interface is not necessary.
Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29513
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl4 mainboard will follow in separate commits.
Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Disable I2C7 because there is no device connected.
Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable all PCIe root ports for this mainboard.
Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl3 mainboard will follow in separate commits.
Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The assignment of header->checksum was in some cases done twice, or
unnecessarily split into two lines.
Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to enable the OS SPI driver to use the software interface of
this controller the OPCODE menu has to be set up properly before
locking the controller. This is done on baseboard level so that all
variants will get this done as well.
Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
In order to minimize Electromagnetic Interference (EMI) on the LVDS
interface driven by PTN3460, clock spreading must be activated for
mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal
frequency.
Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28761
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard is based on mc_apl1. In a first step, it contains a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl2 mainboard will follow in separate commits.
Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In preparation for a future MC Apollo Lake board which will be equipped
with LPDDR4 modules, it is necessary to make the swizzle data
configurable. Starting from the mc_apl1 baseboard, which is equipped
with DDR3L memory and therefore does not need swizzle data, the
structures are initialized with zero.
Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3.
Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
The firmware of devices connected to LPC should deassert the LPC CLKRUN#
signal when there is no bus activity on LPC.
Necessary changes:
- Enable LPC CLKRUN#
- Enable LPC PCE (Power Control Enable)
- Enable LPC CCE (Clock Control Enable)
- Remove I/O decoding range on LPC for COM 3
- Disable I/O UART driver
Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch disables the unused PCI clock outputs on the XIO2001 PCI
Express to PCI Bridge.
Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To increase the lifetime of the circuit, it is necessary to reduce the
eMMC speed to DDR50 mode.
Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
For the 1st redesign of mc_apl1 mainboard some adjustments are
necessary:
- The FPGA is now connected directly via a PCIe Root Port
- Internal Apollo Lake UARTs are now used
- Adjusting GPIO settings
Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
A FPGA is not necessarily available in further mc_apl1 variants. So we
move the loading of the driver and the notify function to the mc_apl1
variant.
Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary
for further variants.
Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Platforms with LATE_CBMEM_INIT were agreed to be
removed with 4.7 release late 2017.
Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since the SIOW method doesn't use any arguments, don't pass it any,
and initialize it as not using any.
Change-Id: I3fa2ab8afb7d09c176a94bbd1db27587c36030cd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use of device_t has been abandoned in ramstage.
Change-Id: If67ea25a9e1363dde8aefe62b92ee7a61f0458b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Change OEM ID values to 6 characters to fix error compiling with IASL
version 20180427.
Also update table creator to 8 characters from 7.
Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The following things are specific characteristic of mc_apl1 board
variant:
- initialization for the eDP to LVDS converter
- enable decoding address range for COM 3
- legacy IRQ routing for PCI devices
- wait function for old legacy devices
- set coreboot ready LED
Change-Id: I5c853e6caae6cc880ead436f232cabddeee6d09a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25822
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens will provide further boards based on Apollo Lake. These differ
only slightly. To avoid copying the complete directory of the reference
board we simply create variants that only contain the differences, like
google/reef does.
To further the ability of multiple variant boards to share code provide
a place to land the split-up changes. This patch provides the tooling
by using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing.
The directory layout with a single variant mc_apl1 (which is also the
baseboard) looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/mc_apl1 - code
variants/mc_apl1/include/variant - headers
New boards would then be added under their board name within the
'variants' directory.
No split has been done with providing different logic yet. This is
purely an organizational change.
Change-Id: Ia3c1f45daee3b9690a448b82edbeec552ee05973
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Due to an accuracy issue on IMON in the IDT PMIC, the reported system
power consumption was higher than the actual consumption. To prevent
this problem, a logic must be implemented in mainboard_init(). This logic
consists of slope and offset as constants for Vcc and Vnn, which need
to be programmed by coreboot. This fix compensates for the accuracy
issue.
Change-Id: I77faf95951d03ac6ce97a6721dba6e8466122a25
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
By storing the FSP-M DRAM configuration parameter in the hwinfo block,
one becomes more flexible in case of a change of the DRAM type.
The configuration data from hwinfo block is a one-to-one representation
of the FSPM_UPD data starting with parameter 'Package' (offset 0x4d) and
ending before parameter 'Ch0_Bit_swizzling' (offset 0x88).
Change-Id: I58c1df0954a436710ecb59487ece07a0832b0de6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coverity scan has found an error where a NULL pointer is dereferenced.
The bug would happen if the devicetree does not contain a valid entry
for PCA9538. In this case the code
* if (dev->path.i2c.device == PCA9538_SLAVE_ADR)
would dereference to a NULL pointer.
This patch fixes this issue. Thanks coverity!
Found-by: Coverity (CID 1386126: Null pointer dereferences (REVERSE_INULL))
Change-Id: I75e271d86c16fa3938420c43575ebba910f6a2fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Show mainboard version in the console log so that one can easily see it.
Change-Id: I33bae8b340fce13c0cbe525521828929038b069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The I/O expander on the mc_bdx1 is used to get the hardware version of
the mainboard. This patch enables the chip driver for the I/O expander.
Change-Id: I98c667fe4dccf0698ab4cb5ede6082f020c70ec6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For internal measurements this mainboard needs a marking inside the NC
FPGA when coreboot is ready and payload has been loaded.
Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The default setting for I2Cx is 400kHz. On this mainboard there is a
device on I2C0 which requires a lower clock rate to work correctly. For
this reason we set the frequency to 100kHz.
Change-Id: I637a58a0c89ead55ca1176d6aecdfaba5897d64f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard has its own coreboot ready LED. The LED is switched on
via GPIO CNV_RGI_DT.
Change-Id: I179d013746c1334337dc9e6b7f09ac54eff0cd77
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On this mainboard there are PCI devices, which are connected to the PCIe
root port via a PCIe-2-PCI bridge. One of the devices only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 4 (Device 14.0).
The following routing is required:
INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA#
Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add GPIO initialization for mc_bdx1 mainboard. Call init_gpios() as
early as possible as FSP will set up things (like hiding PCI devices)
rather early. If connections on the mainboard are dependent on GPIO
settings then FSP can screw things up (e.g. disabling not yet connected
PCI root ports).
Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Like happend in commit efd0eb35af
(siemens/mc_apl1: Add delay to wait for legacy devices) add the
feature to mc_bdx1 as it uses the same legacy devices.
Change-Id: I355a53ce7aea70098d7bc08f24dc6a4e43d1d618
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
IRQ 9 is used for different purpose on this mainboard so move SCI away
to IRQ 10.
Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.
Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
APL internal UARTs are not used on this mainboard.
Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
