This adds initial support for the Pine64 ROCKPro64 board.
The ROCKPro64 (http://pine64.org/rockpro64) is a SBC using the
RK3399 SoC with up to 4GB LPDDR4.
So far only the bootblock part works, the romstage starts to execute,
though.
For ramstage to work we'll need to port some of the changes required
for LPDDR4 vs LPDDR3. This will be addressed in follow up changes.
UART2 on the PI-2 connector can be used as a coreboot console.
GND is pin 6
TXD is pin 8
RXD is pin 10
Flashing:
I used an OpenWRT nightly for the ROCKPro64 and its builtin tool.
$ mtd write coreboot.rom /dev/mtd0
Recovering from a bad flash:
To recover from a bad flash bridging pins 23 and 25 on the PI-2
connector will make the board boot from SD card.
Signed-off-by: Moritz Fischer <moritzf@google.com>
Change-Id: I47d0031fff8ee10b11ad74935eaeb05f1f7eb4b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50625
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This comment is useless, and was dropped from the tree in the past.
Change-Id: Ie46bf13ec27ff9cd9423795fc170cc7526e18122
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49124
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs.
Bilby mainboard code is taken from mandolin variant Cereme.
These new files are a renamed copy and subsequent patches will be
applied to create a working bilby implementation.
Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The I2C EEPROM on SMBUS needs to be updated with the current board
layout, so that the BMC knows the actual configuration.
Collect all needed information and update the EEPROM if something
changed. Every byte written add a delay of 5 msec.
Change-Id: Ic8485e6c700eede75b1e829238ee70da65118ace
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some (notably older Intel) boards use a tabular description of irq
routing that we want to keep pristine no matter what clang-format
considers correct (as that's ugly).
Change-Id: I259255a9f60208c659b658ecb81535e84a2aaa8c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Enable Refresh2X to mitigate RAM corruption during long
(> 1hr) periods of S3/suspend, which leads to failure to
successfully resume from S3. Unknown if an issue with all
DRAM types, but tested w/Kingston KVR24S17D8 16GiB DDR4 SODIMMs.
Test: Build/boot Librem Mini v1/v2, put device in suspend,
wait > 1hr, ensure resume from S3 successful 100% of the time.
Change-Id: Ie8e3ebbb1ebdcd98813b5f36f580a235712d2f97
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Check and print errors returned from reading from I2C
* Rework offset calculation by using more macros
* Get rid of stage-specific preprocessor code
* Define the EEPROM layout as struct
* Make use of the defined EEPROM layout to calculate offsets
* Read the UPD to disable VT-d from EEPROM
Change-Id: Iad77811318c7dfd3a3a4f8d523cfa0f457f168b6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48808
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It’s good practice to put the unit into the name.
Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move `CROS_GPIO_DEVICE_NAME` to a new `chromeos.h` header, because
Lynxpoint uses a different value. Also drop unnecessary includes.
Tested with BUILD_TIMELESS=1, Google Tidus remains identical.
Change-Id: I38baed2c114fb93cfb82535a6ec00fb67e596d64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `GPIO_OUT_HIGH` macro is not present on Lynxpoint headers.
Change-Id: I12dd065bee49097c602febf18c6c9940ecec5106
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50078
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare to unify Lynxpoint LP and Broadwell GPIO code.
Tested with BUILD_TIMELESS=1, Google Auron Paine remains identical.
Change-Id: I00b9184fe6f002c3e089c9fbc815862d60e7694f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50068
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Second pass GPIO configuration to enable the non-native function
GPIOs based on the guybrush Proto 0 reference schematic 0210.
BUG=b:177909472
TEST=builds
Change-Id: I0fdc4d7369353f88cf05e2e1ec08898d4605e602
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
We deal with mb/lippert/frontrunner-af later since it currently
does not include <cimx/sb800/acpi/fch.asl>.
Change-Id: I30b611fc1fb01777223d7222adc96308a247a35c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50591
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will be common for all boards, so move it to the chipset device
tree.
TEST=CPU cluster and LAPIC still show up in console logs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia49e7b4cfc09c60b6152b8ccc47f37b6adc1e319
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50613
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We now pass the ACPI SCI IRQ to the OS, so make sure the board routes it
correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1b4d5e0bfb1d9df9ac8a8c41cdf466a67f2673d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Needed to enable ACPI support for cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia5869905ed053cdca5f61697cffc7f9b59370859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Some Trogdor variants will include a fingerprint sensor, so this patch
adds support for its power sequencing. There is a requirement that the
fingerprint power needs to be *off* for at least 200ms, and when it is
turned back on it needs to stabilize for at least 3.5ms before taking
the FPMCU out of reset. We meet these timing requirements by splitting
the sequence across bootblock, romstage and ramstage. On current Trogdor
boards we measured <end of bootblock> to <end of romstage> at ~430ms and
<end of romstage> to <start of ramstage> at 12ms, so we easily meet the
required numbers this way.
BRANCH=trogdor
BUG=b:170284663
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iccd77e6e1c378110fca2b2b7ff1f534fce54f8ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I left most everything as NC since we don't expose the values to the
OS yet.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c3195ef27091f1bc61892c475ffe09137b63083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50511
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code to read the SPD file and index it is not variant-specific.
Change-Id: Ifaedc39b683901b60abbb1d984f1d38c1ed364e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50542
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use global variables to provide mainboard USB settings, and have the
northbridge code copy it into the `pei_data` struct. For now.
To minimize diffstat noise, this patch does not reindent the now-global
mainboard USB configuration arrays. This is cleaned up in a follow-up.
Change-Id: I273c7a6cd46734ae25b95fc11b5e188d63cac32e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50538
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a µATX mainboard with a LGA1150 socket and two DDR3 DIMM slots.
Working:
- Both DIMM slots
- Serial port to emit spam
- Some USB ports
- Integrated graphics (libgfxinit)
- DVI
- Realtek GbE
- All PCIe ports
- At least one SATA port
- RAM initialization with MRC binary
- Flashing with flashrom
- S3 suspend/resume
- VBT
- SeaBIOS 1.14 to boot Arch Linux (kernel linux-5.10.15.arch1-1)
Broken:
- Audio. It doesn't work on stock firmware either.
I suspect the codec hardware on my board is dead.
Untested:
- PS/2 mouse
- EHCI debug
- Front USB headers
- Non-Linux OSes
- TPM header
- VGA
Change-Id: I9e47747a99c65e488487fbbcac1de15b9bf5c235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41260
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.4 kernel logs the message below:
at24 i2c-PRP0001:02: Bad "address-width" property: 13
The valid size of the AT24 NVM is 16 bits so modify the value from
0x0D to 0x10.
BUG=b:177655681
BRANCH=none
TEST=Boot volteer and check the kernel log and see "Bad address-width"
error message is not shown.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ice6c3eac1e023b981217e1d7dc06587fc46b1a02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bingbu Cao <bingbu.cao@linux.intel.com>
Was copy-pasted from another board and is completely useless.
Change-Id: Iedb03284b4509597cff5d39dda4f98669f2e814b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Desktop boards do not have any backlight control.
Change-Id: Ie9f5f4d7e6ae09b3d664d53e4c03157fd4ed088e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The southbridge ASL already includes this file.
Change-Id: I492d4c860a50ac98acbcb3a51fa4d47c94baade3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Platform code will overwrite these values anyway, so do not program them
in mainboards.
Change-Id: I7571d336a1402c6cfae5835a95dc706a28106271
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49751
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ifdc3f061d919c8db9001c7a4cc26eb21117958d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ice096777077bd2e9cfbaf744371fc372c0c05606
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Was copy-pasted from bd82x6x and no mainboard actually needs it.
The few globals moved outside the GNVS will be removed, relocated or
replaced with acpigen later.
Change-Id: I590a355f1bd1e54365b2e329cfdc62384446a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49280
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Was copy-pasted from i82801ix and no mainboard actually needs it.
Change-Id: I400424540b52dc5d43aba15720b18ad57ea2ebda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49279
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The value should be set by OSPM using some combination of
_OSI() queris in the \_SB._INI() method.
To maintain previous behaviour with this commit, boards where
GNVS osys initialisation was removed now do the same in ASL.
Change-Id: Id4957b12a72fbf7fa988e7ff039e47abcc072e1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49353
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This reverts commit 2151f7561d.
Reason for revert: It depends on the shadowmountain ramstage patch.
Error on the builder:
IASL /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
#include <baseboard/ec.h>
^~~~~~~~~~~~~~~~
compilation terminated.
Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.
BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.
BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.
BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Enable acoustic noise mitgation for volteer platforms.
BUG=b:179328166
BRANCH=none
TEST= Measure the change in noise level by changing the values
in devicetree.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I279a85c7741094bb7ddf0c1fde74b31189b12171
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Configure Port C VREF according to the settings in the EEPROM.
Change-Id: I5b4f0d91fc30c6b585434b9450544281f4411ff4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50396
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement `mainboard_azalia_program_runtime_verbs` to configure the
Realtek ALC888 codec according to the settings in the EEPROM. The
encoding of the `internal_audio_connection` field is:
0: Disabled
1: Front HP out
2: Internal speaker
Change-Id: I5e0013217838888977aaa9259e0cfb78c82f719f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The reset GPIOs are already configured in bootblock.
Drop the unused ramstage code.
Change-Id: Ic99fcae2a3f00be7eebd7be618df838522dac69f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With a new HW revision of this board, the connection of the external RTC
RX6110SA was changed from I2C bus 0 to I2C bus 3.
Change-Id: I10dd44949973ea490b3c7e4ad83d56ce2e566adf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Hide the detail of allocation from cbmem from the FSP.
Loading of a BMP logo file from CBFS is not tied to FSP
version and we do not need two copies of the code, move
it under lib/.
Change-Id: I909f2771af534993cf8ba99ff0acd0bbd2c78f04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
update telemetry to improve the performance.
BUG=b:168585079
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD stardust test => pass
Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
- Add support for ME Soft Temporary Disable Mode. In this mode, ME
doesn't load its kernel and freezes at Bring UP (BUP) phase. This mode
is saved in ME NVRAM (and thus will remain for next reboots and
poweroffs).
- Add support of new CMOS option for Sandy Bridge and Ivy Bridge
ThinkPads.
HOW TO USE
To disable ME:
1. nvramtool -w me_state=Disabled
2. reboot
To enable it back:
1. nvramtool -w me_state=Normal
2. reboot
To check current status:
intelmetool -m
Tested on ThinkPad X230 and ThinkPad X220.
BACKGROUND
There's no Intel documentation that would explain how this should be
implemented, in public. Working binary sequence for MKHI command to put
ME in Soft Temporary Disable Mode, as well as a way to bring ME out of
it (by writing to H_GS register), was found and published by researchers
from PT Security:
1. To disable ME, BIOS issues the disable command (before End of Post)
and reboots. ME is supposed to be disabled on the next boot after
DID (DRAM Init Done).
My numerous tests show that issuing the command and rebooting is not
enough. If we reboot too early, ME will not be disabled. Apparently,
it is doing something in background after receiving the command. It
works with a delay of 500-1000 ms.
I also tried to dump all known (documented) registers, such as GMES
and HFS, before and during the next 2 seconds after execution of the
disable command to find a possible indication that something's
changed in ME and we're ready to reboot. Found nothing
unfortunately.
2. To enable ME back, host writes value 0x20000000 to H_GS.
PT slides don't contain any more information on it, but my tests
show, that after writing this value, GMES[31:28] is changing from
0x01 (BUP phase) to 0x03 (Policy Module) to 0x06 (Host
Communication). Then, after some more time, fw_init_complete bit of
HFS becomes 1.
This means that ME starts loading its kernel immediately, without
reboot.
On the other hand, Lenovo BIOS clearly perform a reboot after
enabling it (one reboot after saving the settings, then ThinkPad
logo appears, and then one more reboot). I'm assuming we have to
reset too.
Change-Id: Ic01526c9731cbef4e8552bbc352133a2415787c2
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
BUG=b:176213181
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If0959df5d0f069048777df81b0d4092ea90314eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Mark TSEG as reserved, which is done on other platforms as well.
For some reason CorebootPayloadPkg crashes when using the region where
TSEG typically resides, which is basically RAM.
UefiPayloadPkg doesn't show this issue.
Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch includes the bootblock and verstage changes for
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:179100924
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI support for battery, AC and lid.
I don't have MacBook Air 4,2 to test, but:
- I tested it on 5,2;
- I found decompiled DSDT for 4,2 and compared registers and bits,
they are the same as on 5,2.
So it should work.
Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kracko variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:178092096
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_KRACKO
Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable this driver along with power saving.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1. Add pl4 value
2. Change policies passive with sensor 0 and 1
3. Change granularity value with pl1 and pl2
BUG=b:178768749
TEST=make buildall
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:
- DeepSx
- USB power in S5
- Power state after G3
Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Hermes has an EEPROM with firmware configuration data. Add definitions
to read and verify the `board settings` from the EEPROM. Subsequent
commits will hook up these EEPROM settings.
Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The latest initial code is from BOE, the vendor.
BUG=b:179206650
BRANCH=kukui
TEST=Run long time aging test and the BOE LCD shows normally.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix booting with SMP enabled, when specifying more CPUs than supported
by the code.
Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.
Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.
Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
USB2 ports assigned to type-C connector need to be configured properly
by the USB2_PORT_TYPE_C. and also modify the description of USB port.
BUG=b:177480902
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the typeC port function is normal by manual.
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI entries for AT24 NVM device.
BUG=b:169551066
TEST=Build and run for basic camera functions.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Define the 25th bit of the fw_config for the regular touchpad
and numpad touchpad selection.
BUG=b:174027837
BRANCH=firmware-volteer-13672.B
TEST=build pass
Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.
BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the system can power off normally in recovery page
Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
