Kukui is using MIPI display panel and needs some identifier to tell
payloads which LCD module is installed, and to select right kernel
device tree. Following Scarlet, the decision is to embed LCD module ID
as part of SKU ID.
The LCM ID is using a different voltage mapping table from the rest.
Considering the complexity in computation of SKU ID, it is better to
move the cache logic from get_index to caller.
Also revise the mapping table since ADC on 8183 only supports 12
levels.
BUG=b:129299873
TEST=make -j; boots on Kukui Rev2 unit.
Change-Id: Ib0c00bc8ce3c71c445c5c4561403ce8ef4dd5844
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32263
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The external RTC was removed on the mainboard as it is not needed.
Remove the usage of the driver for RX6110SA as well.
Change-Id: Ia476e58c0b0f343d4e9e4fa6039bf82b194a87d3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the power rail discharge times measured on hatch,
update the assertions widths that have to be programmed in SoC.
BUG=b:129328209
TEST=warm/cold reboot and S3 are working fine on hatch.
Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Laser would prefer to use different SAR values. Since Laser
sku id is 5.
BUG=b:130381493
BRANCH=octopus
TEST=build
Change-Id: I5cce38a191edfb235e274db3c788c58b65e0ebe1
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32296
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use common code to detect ACPI S3.
Untested.
Change-Id: I2264c087b317f70506817b5458295a17e83b1efc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Restore Goodix devicetree config because of the
missing Goodix config when moving from baseboard
devicetree to board level overridetree. And move
PENH from I2C#2 to I2C#1.
BUG=b:124460799
BRANCH=None
TEST=local build and tested with Goodix touch screen
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is
the interrupt line for sx9310. This is required because IRQ# used by
GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing.
Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6
is currently unused in the devicetree.
BUG=b:129794308
TEST=Verified that there are no interrupt storms on GPP_A0.
Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change configures reset config for all pads routed to IOAPIC as
PLTRST. This is required to ensure that the internal logic of the GPIO
gets reset any time the platform enters S3 or powers off and avoids
any interrupt storms on boot-up.
BUG=b:129933011
TEST=Verified that there are no interrupt storms on boot-up from S5.
Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the new configuration 'Krane' that will need at least its own EC.
There's currently no difference in coreboot side.
BUG=b:130011505
TEST=make menuconfig; make -j # select board=Krane
BRANCH=None
Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Three GPIOs are not being used and this change will save 2-3mW
power during S0iX and this power saving is only for Arcada
BUG=b:129990365
TEST= Measure total platform power during S0iX from Arcada
Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing
actually active-low
BUG=b:130196983
BRANCH=none
TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff".
Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The "write protect" GPIO's cached value is never actually
read after entering depthcharge. Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.
The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch. Correct some of
the values sent to boards which presumably never read the
previously incorrect value. Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.
BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.
BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.
Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
ODM reported issues that some systems can't be shutdown to S5 very
occasionally.
ODM found issue is gone if they remove the WLAN card.
So, this change to disable WLAN before system enters S5.
This change is validated by ODM and it does help issue.
BUG=b:129377927
Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.
BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
run 'powerinfo' in EC console and see power state in S3.
3. Wait until AP resume.
4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.
BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'
Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree,
on both USB2 port 5 and 10.
BUG=b:123293169
BRANCH=none
TEST=compiles, verified kernel is able to find the reset-gpio
Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dev pointers were being dereferenced before the null
check. Move the checks so they are done earlier.
Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a support melfas touch panel with i2c address:0x34.
BUG=b:122019253
TEST=tested with new melfas touch panel and worked
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16
slot. All parameters for FSP are set during initialization in
romstage. Now there is no need to additionally configure the FSP
before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices:
- LP11000e Fibre Channel HBA (Gen2 x8);
- PEX8734 PCIe Fabric/Switch (Gen3 x16);
- NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2
(4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used
as primary device for display output. Dynamic switching is not yet
supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If an external graphics card is inserted in the PEG, it will be used
as the primary display device (as in the AMI BIOS)
Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The InternalGfx option in devicetree.cb is not used to enable iGPU.
The patch removes this option from chip.h and mb/*/devicetree.cb
files for all boards with skl/kbl processor.
Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change moves the I2C/SPI devices and configs which do not apply
to all variants to override tree. Currently, there are just two
variants. However, as we prepare to add more variants, these devices
need to be moved out of the base devicetree.
BUG=b:129728235
TEST=Verified that I2C/SPI devices are present in static.c for hatch
and hatch_whl.
Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device
is already powered off. However on hatch the SATA power is still enabled. And,
since DEVSLP is low, this causes the SATA device to not enter low power state.
The fix here is to set the pad config to be reset on PLTRST assertion which
will cause the pin to be high impedance state and will be pulled up by the
SATA device.
BUG=b:126611255
BRANCH=None
TEST=Make sure that S3 and S0ix is working fine on hatch.
And also make sure that DEVSLP is pulled high in S3.
Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.
Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope
Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPP_B4 to low in S5 to meet touch panel power sequence
BUG=b:124197348
BRANCH=master
TEST=Verify GPP_B4 is low.
Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding Kohaku as a variant of hatch.
BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_KOHAKU is built as well.
Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This option is duplicated in depthcharge:
https://crrev.com/c/1545144
BUG=b:124141368, b:124192753, chromium:943150
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1545144
BRANCH=none
Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Follow thermal table for second tunning.
BUG=b:129509918
TEST=Built and tested on sarien system
Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The sku ids are updated for Pantheon.
Sync'ing the sku_ids list in the master sku sheet for Pantheon.
BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
For HW require to change GPIO_E1.
Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1).
BUG=b:123730924
TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.
BUG=b:128686027
Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The dead_code() macro can be used to ensure that a certain code path is
compile-time eliminated (e.g. if you want to make sure it's never
executed for certain Kconfig combinations). Unfortunately, the current
implementation via __attribute__((error)) hits only at the GCC level.
This can catch code that can be compile-time eliminated based on state
within the same file, but it cannot be used in cases where a certain
library function is built but then garbage collected at link time.
This patch improves the macro by relying solely on the linker finding an
undefined reference. Unfortunately this makes the error message a little
less expressive (can no longer pass a custom string), but it is still
readable and one can add code comments next to the assertion to
elaborate further if necessary
Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ronak Kanabar