Commit Graph

8926 Commits

Author SHA1 Message Date
Martin Roth eb84337344 src/mainboard/kahlee: Remove delan variant
BUG=b:121354442
TEST=None

Change-Id: I348c7106772eecd513baf9abe60ef19008d0ba4d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31424
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18 20:22:33 +00:00
Casper Chang d432e367c1 mb/google/sarien/variants/arcada: Update thermal configuration for DPTF
Update dptf for arcada EVT.

BUG=b:123924662
TEST=Built and tested on arcada system

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5
Reviewed-on: https://review.coreboot.org/c/31331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18 20:19:38 +00:00
peichao.wang 67100b4147 mb/google/laser: Disable touch screen device that according to SKU ID
We need disable touch screen device on laser SKU ID 6.

BUG=none
TEST=according to sku_id (Laser(convertible): 5, Laser14(clamshell):
6, Laser14(clamshell + touch):7) distinguish whether disable touch
screen device.

Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6953c35a5e8c93d88fe63362156faa351e8ee71f
Reviewed-on: https://review.coreboot.org/c/31428
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18 03:05:14 +00:00
Sumeet Pawnikar fe1b40b1dd mb/google/hatch: Enable DPTF functionality
Enable DPTF functionality on hatch platform.

Change-Id: If9ef74364616f95b27b73c39fea42d2623d78ae2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15 16:27:29 +00:00
Paul Menzel 8ca2af1c0d src: Use macro `ACPI_FADT_LEGACY_FREE`
Replace all instances, where 0 is used by the macro/define
`ACPI_FADT_LEGACY_FREE`.

Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/31289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-02-15 16:24:02 +00:00
Karthikeyan Ramasubramanian 783be13495 mb/google/octopus: Fix USB ACPI configuration for CNVi BT module
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix
the device configuration in the devicetree.

BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.

Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-15 16:23:14 +00:00
Chris Zhou 04de23214e mb/google/sarien: Set ELAN as the default for touch panel
According to request of comment 35, setting ELAN as the default.

BUG=b:122019253
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.

Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945
Reviewed-on: https://review.coreboot.org/c/31430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-15 03:37:20 +00:00
Chris Zhou 391709154c mb/google/sarien/variants/sarien: Enable Elan touchscreen
Eanble Elan touch for sarien EVT build

BUG=b:119763054
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.

Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a
Reviewed-on: https://review.coreboot.org/c/31413
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-15 02:03:35 +00:00
Furquan Shaikh 32bc1dc531 mb/google/hatch: Bump up the BIOS region to 28MiB
This change bumps up the BIOS region to 28MiB to use the hole
between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only
the top 16MiB actually gets memory mapped. Thus, the change ensures
that only RW_LEGACY lies in the 12MiB that is not memory mapped.

BUG=b:123443737
TEST=Verified that hatch still boots up. Ensured that fmap dump looks
correct.

Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-02-13 18:46:39 +00:00
Furquan Shaikh 883d821503 mb/google/poppy/var/rammus: Enable mode change wake source for S3/S0ix
This change enables mode change as a wake source for S3 and S0ix.

Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-13 16:47:20 +00:00
Duncan Laurie f1690f0ec1 mb/google/sarien: Support multiple touchscreen at same address
The Sarien board may have different touchscreen devices that use the
same I2C slave address but have different requirements such as needing
a special driver or ACPI configuration.

In order to support this the devicetree may be configured with multiple
devices at the same address and at boot time the unused devices will be
disabled.

Because there is no GPIO for selecting the device that is present it can
instead be selected with Kconfig, or by setting a VPD key to the HID of
the touchscreen device that is present.  The default for Sarien devices
is to not enable a touchscreen for the OS.

The touchscreen selection is currently limited to the Sarien variant but
this also adds the touchscreen HID for Arcada to Kconfig so it would not
complain about the key not being set.

BUG=b:122019253
TEST=This was tested on a Sarien board by adding a second entry to the
devicetree at the same address.  Without this change the SSDT is not
loaded by the kernel because of the address conflict.  After this change
no touchscreen is enabled by default, but one can be selected with
Kconfig or by setting the 'touchscreen_hid' VPD key.

Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-13 13:04:22 +00:00
John Su c8464748cd mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1.

BUG=b:123461432
TEST=Built and tested on sarien system

Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13 13:03:58 +00:00
John Su 025c575750 mb/google/sarien/variants/sarien: Add GPIO H15 for DVT1
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1.

BUG=b:123342945
TEST=Built and tested on sarien system

Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13 13:03:53 +00:00
Keith Short e0f3400547 coreboot: check Cr50 PM mode on normal boot
Under some scenarios the key ladder on the Cr50 can get disabled.  If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.

BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>

Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13 13:03:33 +00:00
Aamir Bohra 91be00ef1b mb/google/hatch: Configure GPIO pad for non-inversion
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16)
pad in non-inversion mode i.e Rx PAD state is not inverted as
it is sent from GPIO to IOAPIC.

BUG=b:123315212
TEST=Tested for below:
     -> Verify touchpad is working fine.
     -> TPM init is successful and boot with fixed boot media.

Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13 13:03:00 +00:00
Arthur Heymans 7e8bad4daa soc/intel/cannonlake: Don't use CAR_GLOBAL
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.

Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-13 13:01:04 +00:00
Uwe Poeche fdd0519761 siemens/mc_apl4: Enable HW SPI TPM on mainboard mc_apl4
This patch enables TPM2 on LPC and adds the needed devicetree entry for
TPM for mc_apl4.

Test=mc_apl4 flashed, booted into Linux and checked via dmesg if TPM is
present

Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-13 08:34:49 +00:00
Mario Scheithauer 51579edc60 siemens/mc_apl2: Remove double entry from devicetree
Remove a double entry for LPC device from devicetree.

Change-Id: Ib5b4f760251236d6a8b4aba719666daa97e7813d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-13 08:34:17 +00:00
Philipp Hug b09e5001f3 riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
  This should probably be changed later.

TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:

util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf

Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
2019-02-13 04:49:14 +00:00
Arthur Heymans 33ab29fd7c nb/intel/nehalem: Remove CAR_GLOBAL use
We have NO_CAR_GLOBAL_MIGRATION now.

Change-Id: I077f235029e3fe3b1368f028981985895d8b766b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30505
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12 22:16:42 +00:00
Kyösti Mälkki 4dba4975b4 binaryPI: Drop nested northbridge in devicetree
SPD data needs to remain within same chip -block
with device 0:18.2.

Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-02-12 13:33:27 +00:00
Seunghwan Kim 5edbea02d4 mb/google/octopus/casta: Tune usb2eye setting
It needs to tune usb2eye setting for these ports:
 USB2[4] - type-c port
 USB2[6] - camera

BUG=b:122878632
BRANCH=octopus
TEST=built and passed usb2eye SI test

Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-12 11:56:10 +00:00
Kyösti Mälkki 79cc577ba2 google/kahlee: Remove unneeded HAVE_ACPI_RESUME guard
We leave it to linker garbage collection to drop
unreferenced code and symbols from final object files.
Function declarations and definitions are to be guarded
with preprocessor directives only as a last resort.

Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-02-12 05:00:55 +00:00
Arthur Heymans 06e33226b3 mb/intel/galileo: Drop the FSP1.1 option
This board is EOL and has FSP2.0 support, so drop the older
version.

Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-11 12:28:52 +00:00
Edward Hill f14445c145 mb/google/kahlee: Use GPIO_10 for EC_SYNC_IRQ
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.

On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.

BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)

Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-02-11 12:23:05 +00:00
Peter Lemenkov 8b9768effe amd: Remove unused defines
grep -ER \(FAM10_SCAN_PCI_BUS\|FAM10_ALLOCATE_IO_RANGE\) shows nothing.

Change-Id: Id0d321c80a9a393fcc0d9c2a5a675dba48516160
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31288
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11 11:57:21 +00:00
Michał Żygowski 7bfdf5be63 src/mainboard/pcengines/apu2/OemCustomize.c: Enable CPB feature
Enable Core Performance Boost feature in automatic mode.
Also enable C6 state which is a dependency for proper CPB operation.

CPB allows to raise single core frequency from 1000MHz to 1400MHz
during high load if other cores idle. The processor has additional
boosted P-states when CPB is enabled, but these are hidden from OS.

TEST: Higher single-core CPU performance is indicated by increased
memory bandwidth as reported by memtest86+.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2
Reviewed-on: https://review.coreboot.org/c/31229
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-11 11:40:10 +00:00
Kyösti Mälkki c043408ec5 nb/via/vx900: Replace pci_mod_configX()
If clr_mask == 0, use pci_or_configX().
If clr_mask != 0, invert mask and use pci_update_configX().

Change-Id: I4ae64e9b635b3759e4cffc4bbdf029411a4e0f42
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31272
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-10 19:44:10 +00:00
Shelley Chen 98ce3f8dad mb/google/hatch: Replace part-specific SPD files with generic ones
Traditionally, we have always allocated 1 DRAM ID per part number.
However, on nami, we have run out of DRAM IDs because we have
supported so many different parts.  We are now adopting the use of
generic SPD files that are feature-based rather than specific to each
part, allowing us to support multiple parts with a single SPD.

The common SPDs were created by taking current SPDs in Nami (which is
using the same DDR4 parts as Hatch) and zeroing out all the
manufacturer information and part names.  Additionally, we zeroed out
bytes 128 (raw card extension, module nominal height), 129 (module
maximum thickness), and 130 (reference raw card used) after verifying
that they are not used in FSP.  We verified with these fields zeroed
out, all nami devices could boot up without errors.  We also verified
on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic
SPDs boot properly.

BUG=b:122959294
BRANCH=None
TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4
     devices that we currently have.

Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08 19:01:32 +00:00
Patrick Rudolph a1024ac933 mb/ocp/wedge100s: Fix devicetree
Match devicetree what's present and in use.

Tested on wedge100s:
All PCI devices show up.

Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-08 11:00:45 +00:00
Elyes HAOUAS 8c905a82f5 mb/{asrock,intel,kontron}: Include missing <arch/io.h>
Also includes lines sorted

Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-08 11:00:01 +00:00
Karthikeyan Ramasubramanian d5c458f98a drivers/gpio_keys: Remove redundant is_wakeup_source flag
"is_wakeup_source" flag is used to indicate if the concerned device can
trigger a wakeup. This flag is redundant with the "wake" GPE event
definition. So remove the redundant flag and use the "wake" GPE event to
mark the wakeup source.

BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source
in SSDT if wake GPE is configured. Ensure that the system can suspend
and the device acts as a wakeup source

Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-08 10:59:33 +00:00
Peter Lemenkov 498f1cc1f3 mb/*/*/romstage: curly braces after the function definition
See Documentation/coding_style.md, specifically "Placing Braces and
Spaces" section.

Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-02-08 10:58:37 +00:00
Elyes HAOUAS 0c152cf1bb src: Remove unused include device/pnp_def.h
Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-02-07 08:53:07 +00:00
Furquan Shaikh a08765d287 mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.

BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.

Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-07 08:52:07 +00:00
Subrata Banik 6527b1acc7 soc/intel/cannonlake: Add Whiskeylake SoC kconfig
This patch performs below tasks

1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.

2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.

3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.

* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC

4. Add correct FSP blobs path for WHL SoC based designs.

Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-07 04:50:37 +00:00
Furquan Shaikh eaf83489f6 mb/google/hatch: Configure I2C buses
This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.

BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.

Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06 17:38:00 +00:00
Mathew King 946fa5f941 mb/google/reef: Expand the coreboot RO section
Current coreboot size is not adequate for adding new features.

Note for cros: This change is for merge to ToT only and should not be
cherry-picked into reef's firmware branch.

BUG=chromium:903833
TEST=emerge-reef coreboot

Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-06 17:10:11 +00:00
Arthur Heymans 3b0eb602b9 nb/intel/gm45: Use a common romstage
This moves a lot of the common romstage boilerplate code to a common
location, while adding a few mainboard specific hooks.

Another difference is that the settings for enable_igd and enable_peg
are now based on the static devicetree settings.

Change-Id: I30ef7f6962aabde78b5c40e0b53bb85e01c254c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-06 11:09:23 +00:00
Arthur Heymans 1bde3124b4 mb/lenovo/x200/gpio.c: Unclutter the code
Some settings don't make sense like specifying input/output on native
ports or high/low on input ports.

Change-Id: Ib37837b9cdb8bb05e2523e0c43cc71fe4fbf243b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31187
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06 11:08:52 +00:00
Arthur Heymans e51c951799 mb/roda/rk9: Use common code to set up southbridge GPIO's
Change-Id: I2057bf66435fd9113cdb1eef4c273f66b07a5a79
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06 11:07:49 +00:00
Arthur Heymans 32a414f64a mb/lenovo/{x200,t400}: Set SMBUS mux using common SB functions
Change-Id: I1e9a165b722006557557058a14e9f5dac78d4538
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-06 11:07:04 +00:00
Arthur Heymans 7f80c0cf07 mb/lenovo/t400: Remove RCBA replay
his either sets unwanted or unnecessary settings.

Also this RCBA replay did not even originate from the T400 as this
code was copied from the Thinkpad x200 code on which this replay was
already removed in 7bcd062 'mb/lenovo/x200: Remove RCBA replay'

Change-Id: Iac6846d43395e342897e03c1ad31387638bcac64
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-02-06 11:06:26 +00:00
Subrata Banik 838e8375a3 mb/intel/coffeelake_rvp: Select CHROMEOS for CFL-U and WHL-U RVP
This patch ensures to select chromeos kconfig only for required
CFL-U and WHL-U RVPs supported by Intel client team.

TEST=Ensure CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY is only selected
for CFL-U and WHL-U boards.

Change-Id: Ib61409402a948f8d5f91130e200c45320ea13d3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31214
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 22:35:20 +00:00
Duncan Laurie 4e3141f19a mb/google/sarien: Set system type for the board variants
Select the appropriate system type for the different variants of
the Sarien board.

This will allow the Arcada variant to use the tablet mode feature
of the Intel Virtual Button driver.

Change-Id: I8a829aab012256ec196c8ec0fa298fd2bc77f2e1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05 16:04:03 +00:00
Ivy Jian 4bbe8df1dc mb/google/hatch: Add keyboard backlight support
This change adds keyboard backlight feature for Hatch platform.

BUG=b:122799544
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.

Change-Id: I29273122f061e0e442f6629351ef3670535c0507
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31175
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 13:38:03 +00:00
Caveh Jalali 5aba3a2c06 mb/google/poppy/variants/atlas: config GPP_D1 as no-connect
This reconfigures the GPP_D1 GPIO pin as a no-connect.  It really
doesn't go anywhere today or on previous revs of the board.

BUG=b:110614620
BRANCH=none
TEST=atlas still boots

Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05 13:25:56 +00:00
Caveh Jalali 8b400b8c64 Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"
This reverts commit 7696290004.

We're seeing trackpad problems on some units with the I2C bus running
at 1MHz but not at 400KHz.  So, revert back to 400KHz until we
understand how to make 1MHz operation more robust.

BUG=b:123650686

Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05 13:25:43 +00:00
Hung-Te Lin 06fff376a6 mb/google/kukui: Add default HWID for Chrome OS
The default value for Chrome OS HWID should be different.
Calculated as HWID v1.

BUG=b:123336677
BRANCH=kukui
TEST=build and boots properly.

Change-Id: I39c640562c1c3b117292b8abacd36a4a9c2fa6c6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-05 13:25:30 +00:00
Thomas Heijligen 8d010db58e mb/emulation/qemu-i440fx: use e820 in romstage
Use memory map from fw_cfg e820 map to find cbmem_top in romstage to
avoid conflicts with CMOS option table. Keep qemu_gwt_memory_size() as
fallback.

Change-Id: I6465085020125fc790257f09eb157030c6ceabcb
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05 11:03:08 +00:00
Thomas Heijligen 0065b6974f mb/emulation/qemu-i440fx: make fw_cfg_present usable in PRERAM
Change-Id: I98f1c97e3ca33a12620cdd073c76fd4e271f1fcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05 11:01:22 +00:00
Thomas Heijligen da9aa6ddd7 mb/emulation/qemu-i440fx: add e820 interface
Qemu provides e820 table at fw_cfg interface. Add functions to access it.

Change-Id: I547bc7fef09999baa28149a6325cbca91e31e99b
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05 10:56:22 +00:00
Thomas Heijligen 721c8b457b mb/emulation/qemu-i440fx: remove mm file listing
Remove memory mapped copy of the file list to use it also in romstage.
fw_cfg_find_file searches directly for the file on data port.

Change-Id: Ie97ed3f0c98a5bb18a35ab0eaf8c4777a53e5779
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-02-05 10:53:19 +00:00
Werner Zeh d7e5f4b7c5 mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5
These boards need a working VTD therefore enable this feature.

Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2019-02-05 06:34:53 +00:00
Karthikeyan Ramasubramanian 8a64b6fbdb mb/google/octopus: Add USB ACPI configuration for CNVi BT module
This change enables exporting the reset GPIO for CNVi Bluetooth module to
the kernel for use in an rf-kill operation.

BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.

Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05 06:31:50 +00:00
Aamir Bohra fc63b8bbc0 mb/google/hatch: Add USB port capability ACPI support for USB2 port10
This implementation adds support to create ACPI package for USB port
capability (_UPC) and physical location of device (_PLD) for USB2 port 10.

BUG🅱️123375275
TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10
     in SSDT and BT is functional in discrete and integrated mode.

Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31197
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 05:35:38 +00:00
Subrata Banik cff6a1df3b soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig
This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.

Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-04 05:38:01 +00:00
Patrick Rudolph c47d43a8af mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGION
It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE.

Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-02 14:51:20 +00:00
Subrata Banik 73916defba mb/intel/coffeelake_rvp: Enable GBE region for RVP8 and RVP11
This patch ensures to enable IFD GBE region only for required
CFL RVP8 and 11 supported by Intel IOTG team.

TEST=Ensure CONFIG_MAINBOARD_USES_IFD_GBE_REGION is not selected
for CFL-U and WHL-U boards

Change-Id: If3fcd23c32f9afd2004fb176c0324f089f2ee412
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-02 06:08:24 +00:00
Shelley Chen 757571eec1 mb/google/hatch: Enable S0ix
BUG=b:123540469
BRANCH=None
TEST=None

Change-Id: I713e6ad70efdd152895afa45aee44a5b53a8136b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31157
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-01 18:34:57 +00:00
Lijian Zhao 003fdcbda2 mb/google/sarien: Turn on ASPM L1.2 for Card Reader
Enable ASPM L1.2 support for embedded realtek card reader, after change
the power consumption for SD controller from 5mW to less than 2mW.

BUG=N/A
TEST=Build and boot up on Arcada platform, check the PCI configuration
on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader
is also 0x0f.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0
Reviewed-on: https://review.coreboot.org/c/31145
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31 08:43:01 +00:00
Karthikeyan Ramasubramanian cd69259e0c mb/google/octopus: Add Bluetooth USB ACPI configuration
Enable USB ACPI driver for octopus boards and add bluetooth USB ACPI
configuration in devicetree. This change enables exporting the bluetooth
reset GPIO to the kernel for use in an rf-kill operation.

BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS

Change-Id: Ie40f1ad70f21a6fd398ce23d060e0c588ba6ce41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-31 08:41:35 +00:00
Thomas Heijligen a05f8a96b4 mb/emulation/qemu-i440fx: prepare fw_cfg for romstage usage
Add separate functions for selecting the port and reading the port.
Romstage can now read incremental from the data port.

Change-Id: I0ffde3bc2a4415a8af99af2275d16f6609099e37
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-31 08:39:18 +00:00
Thomas Heijligen bcd84fe149 mb/emulation/qemu-i440fx: change file handling
Reduce the number of fw_find_file calls by returning the file structure
at fw_cfg_check_file. The file structure can then be used to allocate memory
and access the file content directly without recurrence searching.
Remove now unnecessary function fw_cfg_load_file.

Fixed breaking function calls and add include guard at fw_cfg_if.h.

Change-Id: I48cc943aaa999e4323e9d7e5dd666c5316533dcc
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-31 08:38:59 +00:00
Tristan Shieh d053f393c4 google/kukui: Set GPIO_RESET to output mode
In payloads, we didn't set GPIO modes. We have to set up GPIO mode in
coreboot for payloads.

BUG=b:80501386
BRANCH=none
TEST=HW reboot works in depthcharge

Change-Id: Ibd2c6c071871edc59497fbb245cdbec6a814f621
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31148
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31 08:38:31 +00:00
Subrata Banik 1f83e9d592 lib/hardwaremain: Fix more ACPI/IOAPIC typos
CB:31139 fixs few ACPI type error. Here is few more typo mistake.

Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31152
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-31 04:34:53 +00:00
Ronak Kanabar 19f5201463 mainboard/intel/cannonlake_rvp: Enable SaGv config
This patch enables SaGv on Intel CNL-Y and CNL-U RVP board

Change-Id: I8a4b8a2a365caed304935bf0d66db9a92d10c23f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31132
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30 11:17:25 +00:00
Ronak Kanabar ab92f26a13 mainboard/{google,intel}: Remove SaGv hard coding
Remove hard coding for SaGv config in devicetree.cb and apply macro for
SaGv config for CNL variants boards

Change-Id: If007589d5c1368602928b1550ec8788e65f70c05
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-30 11:03:27 +00:00
Casper Chang 168f046d71 mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Arcada EVT
TouchScreen: 390 KHz
TouchPad: 389 KHz
H1: 389 KHz

BUG=b:120584026, b:120584561
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
     measure by scope

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb
Reviewed-on: https://review.coreboot.org/c/31124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-30 11:03:02 +00:00
Mario Scheithauer 9ca43191ab siemens/mc_apl2: Change SERIRQ mode
Because of Intel's faulty LPC clock, the SERIRQ mode must be corrected.
By removing this entry from devicetree, the default value (quiet mode)
is used. The problem is described in Intel document 334820-007 under
point APL47.

Change-Id: I7a45e0e5fcde17a20abd19a33282b8a9215b1480
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31138
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30 11:01:01 +00:00
Mario Scheithauer ddf84986d5 siemens/mc_apl2: Correct whitespace of devicetree
Change-Id: Ie0e11b1ce6c6acb1b74ce1196304f7e6ac4664d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-30 11:00:46 +00:00
Mario Scheithauer 67be491458 siemens/mc_apl2: Activate TPM support
The TPM chip is connected to the SPI interface of APL. The proper chip
select pin needs to be used in order to access the TPM in the memory
mapped space. This needed chip select is internally (inside APL)
routable to GPIO 106. Therefore the change of GPIO 106 mode is needed to
make the TPM work on SPI bus.

TEST=Build coreboot for mc_apl2 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.

Change-Id: I2b0d5a6f2c230187857c2428a70de61f21da6724
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-30 11:00:28 +00:00
Seunghwan Kim 1c105b0c8a mb/google/octopus/casta: Correct unused GPIO pad configuration
Real unused GPIO pad is GPIO_123, but GPIO_122 is configured as unused pad.
This patch corrects the configuration.

BUG=NONE
BRANCH=octopus
TEST=emerge-octopus coreboot

Change-Id: I4473bd66a4162f5aee3b998aacba906824728fc8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-30 06:37:47 +00:00
Shelley Chen fced3fe170 mb/google/hatch: Enable AP Wake from EC
Initialize EC_PCH_WAKE_ODL GPIO to make sure that ec events will wake
the AP from suspend.  Also create a task to initialize the hostevent
wake mask properly.

BUG=b:123325238,b:123325720
BRANCH=None
TEST=from AP console: powerd_dbus_suspend
     from EC console: hostevent (make sure wake mask set)
     from EC console: gpioset PCH_WAKE_L 0
     Make sure device wakes up
     Also, checked to make sure keyboard press wakes up
     device from S3.

Change-Id: I53d5291a6b9ab9a21e89ccd21f172180ce473bd5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-30 06:32:23 +00:00
Hao He 11af74be00 mb/google/octopus/var/phaser: Hook up Raydium touchscreen
List Raydium touchscreen in the devicetree so that the correct ACPI device
are created.

BUG=b:121105424
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
     reflash the coreboot to DUT, make sure the Raydium touchscreen can work.

Change-Id: I9ffb2a858f31a8b003086806de07f4079870cddf
Signed-off-by: Hao He <hao.he@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31116
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29 17:41:38 +00:00
You-Cheng Syu fff2ad9926 google/kukui: Move some initialization from bootblock to verstage
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.

This CL moves some initialization steps from bootblock to verstage. This
will save us about 2700 bytes (before compression) / 1024 bytes (after
LZ4 compression) in bootblock. In case of CONFIG_VBOOT is disabled,
these initialization steps will be done in romstage.

BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel

Change-Id: I9968d88c54283ef334d1ab975086d4adb3363bd6
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/30331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-29 13:10:47 +00:00
Tristan Shieh 1e504f7811 google/kukui: Implement HW reset function
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW
reset for SoC and H1.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; manually verified the do_board_reset() on
     Kukui P1

Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31118
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29 12:30:47 +00:00
Tristan Shieh e6a03e0b1b mediatek: Separate WDT reset function from WDT driver
Separate WDT reset function from WDT driver, then we can use the common
WDT driver and have a board-specific reset function on different boards.

In Kukui, we plan to use GPIO HW reset, instead of WDT reset. Add config
"MISSING_BOARD_RESET" in Kukui to pass the build for now.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot; emerge-kukui coreboot;

Change-Id: Ica07fe3a027cd7e9eb6d10202c3ef3ed7bea00c2
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31121
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-29 12:30:34 +00:00
Peter Lemenkov 06ca4c5209 mb/lenovo/z61t/Kconfig: Select I945_LVDS
This board has almost the same schematics as [xt]60 so this should work.

See also commit 7971582e with Change-Id
Iff6dac5a5f61af49456bc6312e7a376def02ab00.

Change-Id: I8dc9b122eb64b5c1dcd0dbc99ac41aa0f8dd9766
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-29 12:29:04 +00:00
Subrata Banik c1bf8ccdbc mb/intel/icelake_rvp/../icl_y: Enable SaGv
This patch enables SaGv on Intel ICL-Y RVP board.

TEST=Able to build and boot to Chrome OS.

Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-29 04:30:16 +00:00
devmaster64 3f888ef845 mb/asus/h61m-cs: Add ASUS H61M-CS
Working:
 - USB (Partially. Check "Not working")
 - PCIe
 - PCIe graphics
 - All SATA ports
 - Native memory init
 - On-board audio (back and front)
 - S3 (Sleep and wake)

Not working:
 - Fan control
 - USB (If the keyboard has a USB Hub or if the keyboard
        is connected through 2 or more hubs then it doesn't
        initialize in time. A simple reboot allows the
        keyboard to be used in SeaBIOS and the bootloader)

Untested:
 - PS/2
 - On board graphics

Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-28 13:37:50 +00:00
Shamile Khan 6afeef829f mb/google/octopus: Fix termination for unused dual voltage pins
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIOTermination
Configuration.

BUG=b:79982669
TEST=Checked that code compiles with changes.

Change-Id: If3cadc000ec6fc56019ee3f57e556dc819d5e0a5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28 13:37:18 +00:00
Seunghwan Kim 6dda1e0556 mainboard/google/octopus/variants/casta: Decrease touchpad I2C CLK frequency
ELAN touchpad supports up to 400KHz, so we need to limit its CLK
frequency to 400HKz.

BUG=b:123376618
BRANCH=octopus
TEST=built and verified touchpad I2C clk frequency gets be lower than 400KHz

Change-Id: If7a43fe20c7e5abdf23c8c36e34c072c371563bf
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-28 13:36:49 +00:00
Arthur Heymans 36ced10364 mb/lenovo/thinkcentre_a58: Extend mb name
While branded as thinkcentre a58 this board can also be found as
"L-IG41M".

Change-Id: I06ed424138c46c6b2f29f15c7ea5c3648b26a8d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-28 13:36:29 +00:00
Chris Zhou daeaa772a2 mb/google/sarien: Using HID over I2C to enable Melf TouchScreen
Current Melfas touchscreen driver cannot unregister ifself when
connecting without Melfas touchscreen or connecting with other devices.
And Melfas touchscreen FW can use I2C and HID over I2C driver, so
switch to using HID over I2C driver.

BUG=b:122710830
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.

Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186
Reviewed-on: https://review.coreboot.org/c/31062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-28 13:36:07 +00:00
Philipp Hug 2ef569a405 mb/qemu-riscv: update to match current qemu version
Boots again to payload not found on qemu.

Change-Id: Ie107eb882cbaac5a5a06c1ff990e7b9364377640
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/30554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-26 13:40:51 +00:00
James Ye a6450d7b76 mb/lenovo/x131e: remove PMH7
This board does not have PMH7.

Change-Id: I382958f012e5f4445efc76c7f36bbdf460c29be4
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31065
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 12:44:43 +00:00
Julien Viard de Galbert cf2b72f951 soc/intel/denverton_ns: Enable ACPI using intelblock
- Port the existing denverton tables to intelblock
- Add C-States table for denverton

Note: Removed code is functionally identical to corresponding
common code.

Tested-on: scaleway/tagada

Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-25 11:24:30 +00:00
Kane Chen b933495229 mb/google/octopus: Override emmc DLL values for Ampton
New emmc DLL values for Ampton

BUG=b:122307153
TEST=Boot to OS on 5 systems

Change-Id: Iadd58d254f4bb384f483c2c3e5615f7569d5211c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-01-25 11:24:02 +00:00
Duncan Laurie 5e96399789 mb/google/sarien: Force power on after cr50 update
By default this board is configured to not power up after an
EC reset.  However in the case of a cr50 firmware update that
will reset the EC it will end up powered off.  In order to have
it stay powered up configure the board to power up.  This will
get reset to the configured default when it boots again.

BUG=b:121380403
TEST=update cr50 firmware and reboot to ensure system boots and
does not end up powered off.

Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:22:52 +00:00
Lijian Zhao 38e40414d2 mb/google/sarien: Increse BIOS region size to 28MB
Increase BIOS region(SI_BIOS) from 16MB to 28MB to make more spaces for
upcoming payloads.

BUG=b:121169122
TEST=Build and boot up fine into OS on sarien and arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I4b03e20a485cb819b468c00e68f1539e92731237
Reviewed-on: https://review.coreboot.org/c/31054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-25 11:21:39 +00:00
Lucas Chen 49c0e6416a mb/google/kahlee/variants/aleena: Add support Synaptics touch pad
Add support Synaptics touch pad for Aleena/Kasumi.

BUG=b:122549449
BRANCH=master
TEST= Check if synaptics touch pad working in ChromeOS.

Change-Id: Icab1b312f1943b27037ef458044ce9e7172919ee
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31064
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-25 11:20:18 +00:00
Jan Tatje 83a127a189 sb/intel/common: Show "Add gigabit ethernet firmware" only for boards that need it
Hide "Add gigabit ethernet firmware" option for boards that do not
use GbE firmware in GbE section.

The option is now hidden by default and can be reenabled on a
per-board basis by selecting MAINBOARD_USES_IFD_GBE_REGION in the
mainboards Kconfig.

The following boards seem to use this:
mb/roda/rv11
mb/ocp/wedge100s
mb/ocp/monolake
mb/lenovo/x230
mb/lenovo/x220
mb/lenovo/x201
mb/lenovo/x200
mb/lenovo/t530
mb/lenovo/t520
mb/lenovo/t430s
mb/lenovo/t430
mb/lenovo/t420s
mb/lenovo/t420
mb/lenovo/t400
mb/kontron/ktqm77
mb/intel/saddlebrook
mb/intel/kblrvp
mb/intel/dg43gt
mb/intel/dcp847ske
mb/intel/coffeelake_rvp
mb/intel/camelbackmountain_fsp
mb/hp/revolve_810_g1
mb/hp/folio_9470m
mb/hp/compaq_8200_elite_sff
mb/hp/8770w
mb/hp/8470p
mb/hp/8460p
mb/hp/2760p
mb/hp/2570p
mb/google/sarien
mb/facebook/watson
mb/compulab/intense_pc
mb/asus/maximus_iv_gene-z

The boards were identified by looking at devicetree.cb, but this
list is possibly still incomplete.

Change-Id: Ibfb07902ad93fe5ff2bd4f869abcf6579f7b5a79
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-25 11:19:51 +00:00
Elyes HAOUAS d2abe9314e mb/{kontron,supermicro}: Use pcidev_on_root()
Change-Id: I61b3e5c92830f02d61a108dadde25ff261099e57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-25 11:18:45 +00:00
Angel Pons e583dd3d51 src/mb/asrock/../g41m-s3: Remove spurious devices
This fixes errors regarding "PCI: Leftover static devices"

Change-Id: Ie45fe6934df4a9dad4c8f6b1af665034853c4c5a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24 22:25:05 +00:00
Arthur Heymans 2bbffc0442 mb/*/*/devicetree.cb: Move the ioapic device under the LPC bridge
This fixes spurious lines "child IOAPIC: 02 not a PCI device" and
IOAPIC as leftover device.

Change-Id: Id8010c84c45f0859508e7564c0eaa501904b7043
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-24 21:46:51 +00:00
Sumeet Pawnikar 062fdf13b8 mb/google/sarien/variants: Set tcc offset value
Set tcc offset value to 5 degree celsius for Sarien system.

BRANCH=None
BUG=b:122636962
TEST=Built and tested on Sarien system

Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-24 14:21:37 +00:00
Duncan Laurie b2e610011c mb/google/sarien: Fix recovery mode detection
In order to support the physical recovery GPIO on sarien it needs
to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO
number in the coreboot table appropriately so that depthcharge can
correctly determine the GPIO number.  The same is done for the
write protect GPIO in this table.

Additionally since we are reading a recovery request from H1 it
needs to cache the result since H1 will only return true on the
first request.  All subsequent queries to H1 will not indicate
recovery.  Add a CAR global here to keep track of the state and
only read it from H1 the first time.

BUG=b:121380403
TEST=test_that DUT firmware_DevMode

Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31043
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:55:21 +00:00
Karthikeyan Ramasubramanian 2b27e236b5 mb/google/octopus/bobba: Add support to handle PEN_EJECT event
Enable gpio_keys driver for bobba and add required configuration in the
device tree to handle the pen eject event.

BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus tools
open on pen eject. Ensure that the system wakes on Pen Eject. Ensure that
the system enters S0ix and S3 states after the pen is ejected. Ensure that
the system enters S0ix and S3 states when the pen remains inserted in its
holder. Ensured that the system does not wake when the pen is inserted.
Ensure that the suspend_stress_test runs successfully for 25 iterations
with the pen placed in its holder.

Change-Id: I768b89d2b45f4dcab6d235b11ce00544a827f22d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24 13:55:02 +00:00
You-Cheng Syu 44e9c37f35 mediatek/mt8183: Move some initialization into mt8183_early_init
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.

This CL adds a new function mt8183_early_init, which includes all
initializations that should be done in early stages. All mainboards
using MT8183 should manually call it in either bootblock or verstage.

BRANCH=none
BUG=b:120588396
TEST=manually boot into kernel

Change-Id: I35d7ab875395da913b967ae1f7b72359be3e744a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/31024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-24 13:53:16 +00:00
Maulik V Vaghela fc707892de mb/google/hatch: Enable support for WWAN
This patch enables relevant GPIOs to enable WWAN. WWAN also requires to
enable USB 2 port 6 and USB3 port 5 which is already enabled in device
tree related changes.

BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.

Change-Id: I1559bbc6168aec1a369bf3291d2c1e2f9a2fbe07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-24 13:52:28 +00:00
Maulik V Vaghela 6225a67740 mb/google/hatch: Enable PCIe WLAN and BT
Enable PCIe WLAN for hatch
1. Enable PCI port 14 for PCIe WLAN
2. Enable CLKREQ, CLK SRC 3 for PCI port 14
3. GPIO pad config for WLAN and BT
USB port for BT has already been enabled so not included in this patch

BUG=b:120914069
BRANCH=none
TEST=check if code compiles correctly and verify GPIO configuration with
schematics

Change-Id: I4f2a6eb37a467ad8b8cdde8fe6b657fabb383b04
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-24 13:52:15 +00:00
Nico Huber 845a96dfd6 Kconfig: Remove symbol names for choices
These are completely throwing Kconfig off, resulting in duplicate
entries.

Change-Id: I401467da686d5011a456b661a10170492a919c81
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-24 13:41:31 +00:00
Arthur Heymans 7701376cca cpu/intel/model_406dx: Remove the notion of CPU sockets
Change-Id: I5e8fb2e7331d02224a4199c4d05f92c603c57f78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31032
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:40:39 +00:00
Arthur Heymans 7e6946a74c cpu/intel/model_206ax: Remove the notion of sockets
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.

UNTESTED: This also updates autoport.

Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24 13:39:19 +00:00
Patrick Rudolph 4c2ce72341 mb/ocp/wedge100s: Add SuperIO support
* Enable COM1, COM2, PMC1 and PMC2

TODO: Look at additional configuration and EC space.

Tested on wedge100s. The serial works without CONFIG_CONSOLE_SERIAL.

Change-Id: Id139bf243c7e7ac3e51a0ddb19d2396452341e29
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-24 09:10:52 +00:00
Sumeet Pawnikar 3f689ca24a mb/google/sarien: Replace B0D4 with TCPU
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to
maintain consistency between coreboot and UEFI BIOS.

Change-Id: I024068c19160e1c08badef3d304ada14455c045f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31028
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 17:28:38 +00:00
Arthur Heymans b3f2323e84 mb/*/*/devicetree.cb: Make sandybridge devicetree uniform
This is a merely cosmetic change.

Change-Id: If36419fbee9628b591116604bf32fe00a4f08c17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2019-01-23 14:57:56 +00:00
Sumeet Pawnikar 01f96d78ff mb/intel/icelake_rvp: Enable dptf functionality
Enable dptf functionality for IceLake based U and Y systems.

Change-Id: I8ef396f9df8e39300d5870fd9a147ecdd6f0ba90
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/29686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-23 14:56:16 +00:00
Shamile Khan 6f86ff3ac8 mb/intel/glkrvp: Fix termination for dual voltage pins
These pins should not have pull downs configured in standby state as that
can cause contention on the termination circuitry and lead to incorrect
behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination
Configuration.

BUG=b:79982669
TEST=Checked that code compiles with changes.

Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/c/30867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23 14:55:47 +00:00
Hung-Te Lin 6e44d7c452 google/kukui: Revise FMAP layout for larger CBFS
Kukui with vboot enabled will build with `detachable_ui`, which needs
larger space in CBFS for more complicated assets. So we need to revise
FMAP sections:

- BOOTBLOCK (not really used) only needs <= 32K.
- GBB can be much smaller since assets moved from GBB to CBFS.
- FMAP is re-ordered (with the cost of less efficient in bsearch) so CBFS can
  get larger continuous space.
- COREBOOT(CBFS) should take all space left.

Since FMAP and COREBOOT have changed location, the system will need to
reflash EC (which contains the new bootblock) as well.

BUG=b:123202015
TEST=Builds and boots on Kukui P1

Change-Id: I22cff99dca8c396c5897c3f6631721af40f3ffbd
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-23 14:55:10 +00:00
Ren Kuo 03f654c8ee mb/google/poppy/variant/nami: disable unused usb2 ports
disable unused usb2 ports of bard and ekko skus

BUG=120874946
TEST=build a test firmware and  run lsusb to check usb ports

Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30986
Reviewed-by: Vincent Wang <vwang@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:54:27 +00:00
Casper Chang dfb5a58d8e mb/google/arcada: Add settings for noise mitgation
Enable acoustic noise mitgation for arcada platform, the slow slew rates
are fast time dived by 2.

BUG=none
BRANCH=none
TEST=none

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034
Reviewed-on: https://review.coreboot.org/c/31034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-23 14:54:16 +00:00
James Ye 77bcc92936 mb/lenovo/x131e: add VBT
VBT was extracted from VBIOS ROM.
Tested with libgfxinit, booting SeaBIOS into Linux.

Change-Id: Ibedb43852dc9b846850e1070b84f708c847b7dbf
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:53:52 +00:00
Arthur Heymans 84fdda3812 nb/intel/pineview: Use parallel MP init
Remove guards around CPU code on which all platforms use parallel MP
init code.

This removes the option to disable HT siblings.

Tested on Foxconn D41S.

Change-Id: I89f7d514d75fe933c3a8858da37004419189674b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:49:57 +00:00
Arthur Heymans c82950bf79 nb/intel/x4x: Use parallel MP init
Use parallel MP init code to initialize all AP's.

Also remove guards around CPU code where all platforms now use
parallel MP init.

This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.

Tested on Intel DG41WV, shaves off about 90ms on a quad core.

Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:47:53 +00:00
Arthur Heymans f266932836 nb/intel/i945: Use parallel MP init
Use the parallel mp init path to initialize AP's. This should result
in a moderate speedup.

Tested on Intel D945GCLF (1 core 2 threads), still boots fine and is
26ms faster compared to lapic_cpu_init.

This removes the option to disable HT siblings.

Change-Id: I955551b99e9cbc397f99c2a6bd355c6070390bcb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-01-23 14:46:36 +00:00
Huayang Duan ea415b335f mediatek/mt8183: Add Micron 4GB LPDDR4X DDR support
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.

Change-Id: I985c5061ce4ed4d88a17619aa5cde7d0121dd3a3
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-23 14:44:23 +00:00
Matt DeVillier b28d8b68ba mb/purism/librem_skl: add 13v3 variant
The 13v3 is just a 13v2 with TPM added, so duplicate 13v2 config
and change strings where needed. Leave MAINBOARD_PART_NUMBER unchanged
since boards were initially shipped with 13v2 firmware, and changing
it now would cause flashrom to throw a board mismatch error.

Change-Id: I1a5e4c84cc9444bb9731b6dcc4de2ce7427dbbb1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23 14:42:17 +00:00
Matt DeVillier 83e915e943 mb/purism/librem_skl: add support for 13v4/15v4 boards
Add support for Kabylake Librem 13v4/15v4 boards, reusing existing 13v2/15v3
variants since board design unchanged (only SoC).
Adjust identification strings, add Kabylake VGA PCI ID.

Change-Id: Ia795b9c7373ea2e2acd3bef309320b58e9e8449d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23 14:41:56 +00:00
Matt DeVillier f34d003c15 mb/purism/librem_skl: adjust CBFS_SIZE
Adjust default CBFS_SIZE to match that used in configs for building

Change-Id: Ibe1312560a923dcdefb8af52a721ab76c0b08a2e
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/31008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-23 14:41:47 +00:00
Ren Kuo 54fe9f62fc mb/google/poppy/variants/nami: close the FP power in S5
close the FP module power in power off (s5)

BUG=122887366
BRANCH=Nami
TEST= build test firmware and measure the fp power enable pin

Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30910
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Vincent Wang <vwang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 14:40:36 +00:00
Maulik V Vaghela e4fcc3ba2c mb/google/hatch: Enable SD card support for hatch
Enable support for SD card support for hatch
1. Enable PCI device for SD and also configure SD detect GPIO
2. Configure SD card related GPIOs in gpio.c

BUG=b:120914069
BRANCH=none
TEST=Verify GPIO configuration with schematics

Change-Id: I8ccaa28323b1e1fcc192e245347a96309227660b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-23 12:24:23 +00:00
Kane Chen d78a202843 mb/google/octopus: Override emmc DLL values for Meep
New emmc DLL values for Meep.

BUG=b:122308271
TEST=Boot to OS on 13 Meep system

Change-Id: I4247114ed69ff3aa283f0f72d5531ad0f37309ad
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31021
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23 06:42:23 +00:00
Timothy Pearson 6b239d8e08 mb/asus/kgpe-d16: Add BMC KCS to ACPI
The BMC KCS interface must be advertised to the host OS in order
for automatic load of the ipmi module to work.  Expose the KCS
interface via ACPI.

Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/c/19822
Reviewed-by: Piotr Kubaj <pkubaj@anongoth.pl>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22 22:34:21 +00:00
Timothy Pearson 5513c0a216 mb/asus/kgpe-d16: Enable IPMI KCS access
The on-board BMC contains a hardware KCS interface.  Allow
access to it over LPC.

Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac6
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/c/19821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-22 22:33:57 +00:00
Daniel Kurtz 2ea99da49d Revert "UPSTREAM: mainboard/google/kahlee: Also configure GPIO_9 in RAM stage"
This reverts commit 3278f859c3dd97a6d6d885a91dfd33d44e95d58b.

Reason for revert:
It turns out all we want to set in RAM stage is GPIO's DEBOUNCE config,
not its SCI configuration.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>

BUG=b:113880780
BRANCH=none
TEST=Boot grunt, does not go to recovery screen

Change-Id: I500934f3e03e66c97873accd4a979a23d4509675
Reviewed-on: https://review.coreboot.org/c/30997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-01-22 18:55:09 +00:00
Subrata Banik 2c64a806ee mb/google/hatch: Remove MAINBOARD_USES_IFD_EC_REGION selection
hatch shouldn't make use of internal ec.bin through IFD tool.

Change-Id: Ib1a324291b1c8ac90a7d790b63427b2e85c74fd1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-22 06:29:31 +00:00
Amanda Huang afe15f0a34 mb/google/octopus/variants: Disable xHCI compliance mode for Fleex
Some usb devices exhibits signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.

BRANCH=octopus
BUG=b:120009029
TEST=Verified usb operation successfully.

Change-Id: Ic7fa08c894397598dee3c4ff9a764e43383a0627
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-01-20 21:04:19 +00:00
Wisley Chen b3a1a44ee2 mb/google/octopus/variants/meep: Disable xHCI compliance mode
Some usb devices exhibit signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.

BUG=b:122671995
TEST=check "Disable Link Compliance Mode" bit of "SuperSpeed Port Link
control" register and usb operation successfully.

Change-Id: Ia2ae7e52391fadc8ed23b8b76c45d410757d22ec
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/30948
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-20 21:04:09 +00:00
Sumeet Pawnikar 2dfa53f80e mb/google/sarien/variants: Add Thermal Sensors information
Add available thermal sensors information for CPU throttling action.

BRANCH=None
BUG=b:120058043
TEST=Built and tested on Arcada system

Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-18 08:15:58 +00:00
Dtrain Hsu 1e7d69944d mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet spec
After adjustment on Sarien EVT
TouchScreen: 380.7 KHz
TouchPad: 379.3 KHz
H1: 392.2 KHz

BUG=b:122657195
BRANCH=master
TEST=emerge-sarien coreboot chromeos-bootimage
     measure by scope

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f
Reviewed-on: https://review.coreboot.org/c/30949
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-18 04:01:38 +00:00
Bill XIE 9cb2da45d8 mb/lenovo/x220: Add x1 as a variant
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).

Documentation added.

Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
  SeaBIOS, or Linux payload (Heads)

Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)

Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-17 17:09:53 +00:00
Arthur Heymans cf2783882f mb/kontron/986lcd-m: Implement disabling ethernet NIC in ramstage
With the i82801gx code automatically disabling devices ethernet
NICs attached to the southbridge PCIe ports can now be disabled
during the ramstage.

Change-Id: If4163f8101d37cc09c0b51b1be20bf8388ed2b89
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30245
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17 14:54:39 +00:00
Ronak Kanabar d266710d2c mb/google/hatch: Configure miscellaneous features
set SaGv = SaGv_Enabled , To Enable System Agent dynamic frequency support
set HeciEnabled = 1, To Enable heci communication
set speed_shift_enable = 1 To Enable Speed Shift Technology support

Change-Id: Iea90a65a77ef5e45a802cfe6fd31e1921163b02b
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-17 13:04:35 +00:00
Keith Short d1215269a7 src/mainboard/google/sarien: query recovery mode from Cr50
On the Sarien/Arcada platforms, the EC is not trusted to provide
the state of the ESC+REFRESH+PWR recovery combination. On these
platforms the Cr50 latches the state of REFRESH+PWR for use as the
recovery mode key combination.

BUG=b:122715254
BRANCH=none
TEST=Verify recovery mode screen shown after pressing REFRESH+PWR
Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17 13:02:08 +00:00
Shelley Chen d44fd0d04d hatch: Add sbmios_mainboard_sku function
BUG=b:122578255
BRANCH=None
TEST=mosys platform id/name/family

Change-Id: I6288ea1a4e9f692b6e04440e61f59ea53f01ebec
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17 07:28:27 +00:00
Shelley Chen 2c89923ec5 hatch: disable sw sync
Disabling software sync since EC patches haven't landed yet.

BUG=b:120914069
BRANCH=None
TEST=build bios image and make sure gbb flag 0x200 is set

Change-Id: I1661bcd6ebbee6d9aa8068efcc18b259fb4c8203
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-17 07:27:16 +00:00
John Su cc394d4d37 mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien.

BUG=b:122636962
TEST=Match the result from TAT UI

Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30808
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 21:45:51 +00:00
Daniel Kurtz 314094fea6 mainboard/google/kahlee: Also configure GPIO_9 in RAM stage
The general rule is to configure GPIOs used by coreboot in bootblock
(using the reset table), and GPIOs used by OS in RAM stage.

However, GPIO_9 will be used as both, and we need to reconfigure it to
properly set up debounce, however, it is no longer possible to change
bootblock, so we also configure it in RAM stage to make the new
debounce configuration take affect.

Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>

BUG=b:113880780
BRANCH=none
TEST=Reboot stress test grunt (>100 times); no messages in dmesg like:
  tpm tpm0: Timeout waiting for TPM ready

Change-Id: I0f1bca176ed3f9cebf6b9e9e1008905e492a2f03
Reviewed-on: https://review.coreboot.org/c/30922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-16 18:20:46 +00:00
Akshu Agrawal 8d9780f6c2 mb/google/kahlee/careena: Add 20ms delay to capture
define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.

BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture

Change-Id: I299a584ef2ba66d1e752515100cbe3919b2108f6
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 18:17:42 +00:00
Akshu Agrawal 2be9911c92 mb/google/kahlee/liara: Add 20ms delay to capture
define wakeup-delay-ms to 20ms. This avoids the pop
noise heard at the start of capture.

BUG=b:119926436
TEST=with kernel patch
https://lore.kernel.org/patchwork/patch/1029806/
no pop sound heard at start of capture

Change-Id: I2593afa69cfb955f6a2b695406855e0f31f28468
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/c/30725
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 18:17:34 +00:00
Nico Huber bd294425c8 mb/purism: Select NO_POST instead of overriding its dependencies
Declaring a Kconfig symbol ahead to override its default also always
sets implicit dependencies. If the original symbol doesn't have any,
Kconfig gets confused.

Change-Id: Ie6d9ca96e4b6037eefd432dd386cb5e540deb0ed
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16 16:46:00 +00:00
Arthur Heymans a6be58fece nb/intel/sandybridge: Remove the C native graphic init
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.

This way libgfxinit also gets build-tested by Jenkins.

Change-Id: Ic6678d3455f1116e7e67a67b465a79df020b2399
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16 16:45:26 +00:00
Subrata Banik 1ed36f9ce9 mainboard/intel: Update mainboard UART Kconfig
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged,
all mainboard using intel cannonlake,coffeelake, kabylake, skylake,
icelake and whiskeylake get affected.

Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

TEST=Intel client and IoT team has verified that LPSS uart
is working fine on CNL, WHL and ICL RVPs.

Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 16:26:56 +00:00
Lijian Zhao d4a12ec822 mb/google/sarien: Enable Camarillo Device
Whiskeylake processor have an internal device called Camarillo
dedicated for thermal management support, turn it on so processor
thermal driver can be loaded.

BUG=N/A
TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0
can be seen.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7
Reviewed-on: https://review.coreboot.org/c/30858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-16 13:39:39 +00:00
Michał Żygowski 37d4ffb0a5 src/mainboard/pcengines/apu1: Enable LPC TPM
PC Engines apu1 has a 20 pin LPC header that allows connection of
external TPM module.

Add necessary Kconfig option and devicetree entry for TPM.

Change-Id: Ic9f3d41c6e8346a12553386b9c00de6b8fd21abd
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/30354
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 13:21:43 +00:00
Kyösti Mälkki 760970fb38 AGESA fam16kb boards: Clean up devicetree
Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: Id3a161c54341d0c5c569ea6118ee6f890b7f62e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30735
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 13:20:24 +00:00
Kyösti Mälkki 872b42486a AGESA fam15tn boards: Clean up devicetree
Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: I67fcb59a63046865f660e628a61c2944b0f89a74
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30734
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: mikeb mikeb <mikebdp2@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 13:20:05 +00:00
Kyösti Mälkki 4ebdf34e13 AGESA fam14 boards: Clean up devicetree
Remove double nesting of chip northbridge/amd.
There is requirement to keep SPD address map in
the same chip block with device 0:18.2.

Change-Id: Ib212f24c3d697a009d2ca8e2c77220de4bfb7573
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30733
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 13:19:49 +00:00
Sumeet Pawnikar e97e90959c mb/google/sarien: Set PL1 and PL2 values
Set PL1 and PL2 values to 25W and 51W respectively for
processor power limits control.

BRANCH=None
BUG=b:122343940
TEST=Built and tested on Arcada system

Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/30908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-16 11:57:38 +00:00
Praveen hodagatta pranesh 0dbce4042f mb/intel/kblrvp: Fix unsigned val casting of smaller size
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I519ed4b5b403622d6bb01ad0bdd04e01dedff7d8
Reviewed-on: https://review.coreboot.org/c/30794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-16 11:57:24 +00:00
Praveen hodagatta pranesh d6e00546a4 mb/intel/kblrvp: Add new Kaby lake RVP11 support
The RVP11 is a dual-channel DDR4 SO-DIMM on skylake H platform.

This patch add following chages
- Add overridetree.cb for RVP11
- Select skylake PCH-H chipset config for RVP11.
- Add GPIO table as per board schematics.
- Add audio verb table for RVP11.
- Set the UserBd UPD to BOARD_TYPE_DESKTOP.

BUG=None
TEST= Build and flash, confirm boot into yocto OS on KBL RVP11
      platform. verified PCI, USB, ethernet, SATA, display,
      audio and power functionalities.

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Id86f56df06795601cc9d7830766e54396d218e00
Reviewed-on: https://review.coreboot.org/c/29809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 11:56:50 +00:00
Kyösti Mälkki 5c29daa150 buildsystem: Promote rules.h to default include
Does not fix 3rdparty/, *.S or *.ld or yet.

Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/17656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-16 11:51:07 +00:00
Mario Scheithauer 65ca24c02e siemens/mc_apl4: Change UART_FOR_CONSOLE index
This mainboard uses SOC internal UART 1 instead of UART 2 like all other
mc_apl1 mainboards.

Change-Id: Ib986962ed068fee019ffcec0391d43d5ab178458
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-16 07:13:39 +00:00
Lijian Zhao 59de870aa3 mb/google/sarien: Set Vref Config to 2
Accoding to desciption in FSP header, Vref Configuration will be set to
2 if VREF_CA to CH_A and VREF_DQ_B to CH_B.

BUG=N/A
TEST=Build and boot up on Arcada platform.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I02e16e141b81d766a6060ca08283f432abd96647
Reviewed-on: https://review.coreboot.org/c/30280
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16 02:07:56 +00:00
Chen, JasonX Z 5ce4c342a0 mb/google/atlas: Enable camera module NVM
Enable at24 EEPROM by adding ASL of nvm

BUG=b:122583978
BRANCH=master
TEST=Build and run for basic camera functions

Change-Id: Ifc2060c2ceb7d1a8ef490f36f484deb425a37c95
Signed-off-by: Chen, JasonX Z <jasonx.z.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/30795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-15 16:26:08 +00:00
Arthur Heymans 8bb2ed82bb mb/*/*: Use libgfxinit on sandy and ivy bridge boards
Change-Id: I41ad1ce06d9afcc99941affa232fa76ffa6631fb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-15 12:53:19 +00:00
Patrick Rudolph a649310ea4 mainboard/ocp/wedge100s: Fix uart
* Route IO 0x6e/0x6f to LPC bus
* Setup ITE8526 in early_mainboard_romstage_entry
* Fix romstage serial console by disabling internal uart default setting
* Unselect CONFIG_INTEGRATED_UART, as it doesn't use internal UARTs
* Select CONFIG_DRIVERS_UART_8250IO, as it has a SuperIO serial
* Configure UPDs related to serial

Change-Id: I59cd83ed43dbf4ee26685e4a573de153291f7074
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-15 07:46:28 +00:00
Arthur Heymans 3ef017c4d4 [RFC]util/checklist: Remove this functionality
It was only hooked up for galileo board when using the obsolete
FSP1.1. I don't see how it can be useful...

Change-Id: Ifd7cbd664cfa3b729a11c885134fd9b5de62a96c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30691
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 19:42:59 +00:00
Patrick Georgi 76f5b225e2 Revert "mb/google/kalista: Disable EC-EFS"
This reverts commit 4e3cd74449.

Reason for revert: Daisuke says "We'll keep EFS on Kalista/Karma enabled"

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I2f11ffc9dd7eb05a2560261bbf472e8488c274d9
Reviewed-on: https://review.coreboot.org/c/30857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 14:53:05 +00:00
Nico Huber 1d748c5346 console: Change BOOTBLOCK_CONSOLE default to `y`
Invert the default instead of selecting it everywhere. Restores the
ability to use its Kconfig prompt.

Beside Qemu targets, the only platforms that didn't select it seem
to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The
latter two were about to be patched anyway.

Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30891
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 12:13:55 +00:00
Angel Pons c69c8ddc2b mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
This board has more or less the same as the p5qpl-am except for DDR3
memory and different colors on the ports. Tested with Arch Linux with
kernel 4.20.0-arch1-1-ARCH.

What is tested and works:
 - 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz
     Some bugs are still present in the DDR3 raminit code though.
 - Ethernet
 - Internal programmer with both coreboot and stock firmware.
 - PCI and PCIe x1 slots
 - All USB ports
 - S3 resume
 - SATA ports
 - PEG
 - Rear audio output

Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27089
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 12:13:13 +00:00
Gaggery Tsai 25176ef022 /src/mb/google/poppy/variants/atlas: Revise SPK reset
This patch revises the pad reset config of speaker reset GPIO pin from
RSMRST to PLTRST. Audio engineer suggested to reset the amps with
warm reset.

BUG=b:122441567
BRANCH=None
TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the
     speakers are working well.

Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-14 12:05:04 +00:00
Wonkyu Kim cb5323415e mb/intel/coffeelake_rvp: Update mainboard UART Kconfig
Update mainboard UART Kconfig for Whiskylake RVP.

TEST=Build and test on Whiskylake RVP.
By default we can still get console from cbmem, and
enable CONSOLE_SERIAL can get logs from UART port2.
Select other Coffeelake RVPs and check CONSOLE_SERIAL is enabled.

Change-Id: Ic56c019a12b467e5bede5648098d3fb82b56ba7e
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-on: https://review.coreboot.org/c/30861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-14 12:04:39 +00:00
Arthur Heymans c6ff1ac29e nb/intel/pineview: Move the boilerplate mainboard_romstage_entry
The mainboard_romstage_entry function is mostly boilerplate, so move
it to a common location and provide mainboard specific callbacks.

Change-Id: I33cf1d6a60d272f490f41205ec725dee8b00242b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 12:02:01 +00:00
John Zhao 8cf6d4d7d6 mb/google/octopus/variants: Configure PLT_RST_L pad IOSSTATE masked
PLT_RST_L was asserted twice at boot-up and a glitch was observed
when coming out of suspend mode. Configure PLT_RST_L pad IOSSTATE
from HIZCRx1 to be masked.

BRANCH=octopus
BUG=b:117302959
TEST=Verified no glitch on PLT_RST_L at S3 and PLT_RST_L stays high
3.3v during S0ix.

Change-Id: I8c23aadda72be54fb45e67aab2bc8ed51e473bae
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30815
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 12:00:19 +00:00
John Zhao b318be2218 mb/google/octopus/variants: Disable xHCI compliance mode
Some usb devices exhibits signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.

BRANCH=octopus
BUG=b:115699781
TEST=Verified usb operation successfully.

Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30817
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:58:47 +00:00
Aamir Bohra e49b2f088f mb/google/hatch: Use USB2 Port 10 for BT over CnVi
Integrated BT controller in CnVi uses USB port 10 for communication.

BUG=b:122552619
TEST=lsusb shows BT device

Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30809
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:58:05 +00:00
Peter Lemenkov 522a1b526b mb/lenovo/[xtz]60: Introduce and use RCBA64 macro
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14 11:57:25 +00:00
Peter Lemenkov e23245517b mb/lenovo/*/romstage: Use macros instead of magic numbers
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead.

Note that IOTR[0123] is a 64-bit width variable.

Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14 11:57:06 +00:00
Peter Lemenkov 7b42811fa5 sb/intel: Use common RCBA MACROs
This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.

Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14 11:56:38 +00:00
Patrick Rudolph aa6d388597 soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()
Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.

Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 09:14:01 +00:00
Kyösti Mälkki 7d9016931c AGESA binaryPI: Consolidate ACPI for IMC
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18538
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 06:55:47 +00:00
Kyösti Mälkki 24aea52e29 AGESA binaryPI: Remove unused IMC ACPI methods IMSP and IMWK
Note that IMC must sleep while SPI writes are in progress.
Instead of using these ACPI methods, flashrom currently does
raw IO to achieve the same.

Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18537
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 06:55:15 +00:00
Kyösti Mälkki f40f209c15 binaryPI: Remove ACPI for IMC we don't run
IMC is used on some of the AMD reference designs, so do not
touch them yet.

Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-01-14 06:54:10 +00:00
Kyösti Mälkki 51769b2f92 AGESA: Remove ACPI for IMC we don't run
IMC is used on some of the AMD reference designs, so do not
touch them yet.

Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-14 06:53:54 +00:00
Mike Banon 7515cd0d04 AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLE
Only a few boards are using IMC for the onboard fan control,
so regarding the availability of IMC selection it should be opt-in,
not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2
because Gizmo 2 could use IMC for the onboard fan control.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16
Reviewed-on: https://review.coreboot.org/c/30756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 06:50:11 +00:00
Matt DeVillier 1d4f936f61 google/butterfly: correct northbridge selection
butterfly is a Sandybridge device, and selecting Ivybridge
breaks libgfxinit currently due to CPU mismatch

Test: build/boot butterfly w/libgfxinit

Change-Id: I1a7f5a3681d21a256834b11b545855c4365f5f78
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30820
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 19:51:24 +00:00
Matt DeVillier e2c4a3518e google/butterfly: add cpu/gpu pwm backlight register values
Required for functional internal display on butterfly using libgfxinit.

Test: boot/build butterfly, verify internal display functional
prior to OS driver loading.

Change-Id: Ib8060f2d1ad0694f0886d35c83763907f61b47b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 19:51:10 +00:00
Elyes HAOUAS c2c1dc9c76 {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
Use hexdump() instead of dump_mem().

Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13 16:24:31 +00:00
YH Lin 67618dd250 mb/google/kukui: add flapjack on top of kukui
Add placeholder for future flapjack additions/modifications.

BUG=None
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e
Reviewed-on: https://review.coreboot.org/c/30859
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 11:34:31 +00:00
Kyösti Mälkki 0377a369b9 aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
This board is the only user of these ancient chipsets,
so we'll do all in one go.

Also wipe out some extra headers.

Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-13 08:38:13 +00:00
Lijian Zhao 64925b5128 soc/mainboard: Update mainboard UART Kconfig
After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 18:59:21 +00:00
Mario Scheithauer dd217362d4 siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an
adjustment is necessary for this mainboard.

Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 18:54:56 +00:00
Jett Rink 2dbe51a17c mainboard/google/octopus: configure EC_AP_INT_ODL
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards
that support it. Also removing unnecessary IO standby support since we
don't use this pin to wake up the SoC.

BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=CTS tests with changes

Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30788
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 19:01:54 +00:00
Kyösti Mälkki 20c294884f amdfam10 boards: Simplify early resourcemap
Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.

Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 13:40:40 +00:00
Kyösti Mälkki 22521ab2e6 amdfam10 boards: Drop extern on apicid_sp5100
The value get_bus_conf() initialises this value to is
discarded.

Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 13:40:04 +00:00
Jan Tatje 82a4e27341 sb/intel/common: Show "Add EC firmware" only for boards that need it
Most boards currently do not use EC firmware from SPI flash in the
IFD, this hides this option by default and shows it only for boards
that need it.

A new config variable MAINBOARD_USES_IFD_EC_REGION is introduced to
enable this option for boards that need it.

The following list of boards requiring this was provided by
Lijian Zhao:
1. intel/cannonlake_rvp
2. intel/coffeelake_rvp
3. intel/icelake_rvp
4. google/sarien
5. google/hatch

Change-Id: I52ab977319d99a23a5e982cc01479fe801e172a7
Signed-off-by: Jan Tatje <jan@jnt.io>
Reviewed-on: https://review.coreboot.org/c/30697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10 12:37:38 +00:00
Hung-Te Lin e7184b0ad0 google/kukui: Correct boardid sources and add sku_id
Kukui is going to use ADC#4 as SKU ID, and utilizing EC BoardID as
global board_id (i.e., board revision).

BUG=b:122060615
TEST=make; manually tested on Kukui P1 board.

Change-Id: I7bba368c141a7ba6db11f24b8e8e7158f0fc729e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10 12:17:52 +00:00
Hung-Te Lin a2333c3935 google/kukui: Complete board ID ADC values
The ID from ADC on Kukui supports 16 different values and we should list
all voltage values ahead.

BUG=b:80501386
TEST=make; manually verified on Kukui P1

Change-Id: Ic3abe07abfe818ca68e180c262fd431d1167b801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10 12:17:37 +00:00
Hung-Te Lin 3f6e32a4b3 google/kukui: Correct boardid init values
From `boardid.h`, the uninitialized ID values should be BOARD_ID_INIT
instead of BOARD_ID_UNKNOWN.

BUG=b:80501386
TEST=make; manually verified on Kukui P1

Change-Id: Ie5267e575e38b92ec64a7317defbd00ee153fa0a
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-10 12:17:20 +00:00
Arthur Heymans f3e50fc681 mb/foxconn/g41s-k: Add g41m variant
Was tested with the following:
- 2 DIMM slots
- USB
- Ethernet NIC
- automatic fan control
- Libgfxinit with VGA, DVI (HDMI slot unpopulated)
- PS2 Keyboard
- SATA
- PEG
- S3 resume

What does not work:
- Using the second DIMM slot on a channel
  G41 can only handle 2 ranks per channel and on this mainboard 1 rank
  per DIMM slot. Supporting this would require too much raminit rework
  and is not worth it (at least for me)

Change-Id: I67784038ef929f561b82365f00db70a69c024321
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 12:17:10 +00:00
Duncan Laurie 13f58e47ed mb/google/sarien: Add PDR and RW_LEGACY_NVRAM to FMAP
1) Add a Platform Data Region called SI_PDR which is allocated in the flash
descriptor for this platform
2) Add a DIAG_NVRAM region for use by the diagnostic payload for non-volatile
storage.
3) Encapsulate both RW_LEGACY and DIAG_NVRAM in a region called RW_DIAG
so it is clear they are associated.
4) Move the RW_DIAG region to the start of the RW region so that once we can
re-enable a larger BIOS region this sub-region will be in the uncached area
since it is not accessed on a normal boot.

BUG=b:119435206
TEST=tested on Arcada board to ensure expected regions are present

Change-Id: Ieb8bc4cf70d0a931e4944210112cfaf5c543f9f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-10 12:15:16 +00:00
Elyes HAOUAS f5a57a883b mb: Move timestamp_add_now to northbridge x4x
Change-Id: Iacbee658a4049e1c13a120dbc21425ffb6a1cabb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 09:53:51 +00:00
Aamir Bohra cda27c2492 mb/google/hatch: enable CPU cluster device
Change-Id: I28c67fbdf2b4f371c4b533b64cad2c4376ca2bd2
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30785
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 08:46:08 +00:00
Kyösti Mälkki ec558682fc aopen/dxplplusu: Move timestamps to common code
First initialisation is already in cpu/intel/car/romstage.c.

Change-Id: If3e5068b4a9981354f0fca5fc12b6b81de1c8f4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 03:24:23 +00:00
Elyes HAOUAS 2dce923524 mb: Move timestamp_add_now to northbridge/amd/amdfam10
Also remove some commented code.

Change-Id: If2e91ad871b14b305e2181194d77b100e72f5763
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 03:14:49 +00:00
Kyösti Mälkki 879e98d1aa mainboard/amd: Drop incorrect Kconfig select
Copy-paste from fam15.

Change-Id: I87af312870063aaa498bbfc2f059f69dcdab0094
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-10 03:06:32 +00:00
Nico Huber a96e66a76f soc/intel: Clean mess around UART_DEBUG
Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.

As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.

Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09 22:15:48 +00:00
Loop_Wu 3910c4e488 Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTD
Sdram config sdram-lpddr3-hynix-4GB.inc for H9CCNNNBKTMLBR-NTD can't
boot on Mickey. It's confirmed that the right config for Hynix
H9CCNNNBKTMLBR-NTD is sdram-lpddr3-hynix-2GB-BK.inc.

BUG=b:122239609
BRANCH=master
TEST=boot on mickey

Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a
Signed-off-by: Loop_Wu <Loop_Wu@asus.com>
Reviewed-on: https://review.coreboot.org/c/30761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-01-09 16:08:26 +00:00
Kyösti Mälkki 993bc7098c amdfam10 boards: Use smp_write_pci_intsrc()
Radically reduces line lengths and splits '(bus<<2) | INT'
to separate parameters.

Change-Id: I6c924a70d00a9139719f8078bbf1e4d04b576324
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09 12:44:52 +00:00
Kyösti Mälkki 611a5f821d mainboard/h8scm_fam10: Use apicid_sr5650
Do this for consistency and to ease further
bulk-sed work on those lines.

Change-Id: Ic9706de4278d163d1ba0c0706ec5d4c6c87ffa45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09 12:44:28 +00:00
Kyösti Mälkki e9fc8fd9b6 amdfam10 boards: Use PCI_DEVFN()
Change-Id: I7b9aeaaa1cfa20efc9d187d91ece4eb9ee659c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09 12:44:11 +00:00
Praveen hodagatta pranesh cd26f08d94 mb/intel/kblrvp: Add helper function to get Board Id
Add 2 helper function get_board_id() & get_spd_index()
to read board id & spd index from EC.
Rename the old get_board_id() function to get_ec_boardinfo().

BUG=None
TEST= Tested on KBL RVP11, able to read the Board id (0x44)
      and verified in serial logs. not verified on KBL RVP8.

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ie20bf0d45a3568c2c433e5b844bea86aac07c47d
Reviewed-on: https://review.coreboot.org/c/30306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-09 10:03:05 +00:00
Praveen hodagatta pranesh 7e48b47185 mb/intel/kblrvp: Enable overridetree support for variants
This patch add devicetree.cb in baseboard and overridetree.cb
for RVP3, RVP7 and RVP8 variants.

BUG= None
TEST= build with BUILD_TIMELESS=1, static.c remains same on before &
       after enabling overridetree.

Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: Ib7d492e2a92aed10ad0426d57640d0ed56733847
Reviewed-on: https://review.coreboot.org/c/30623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-09 10:01:25 +00:00
Arthur Heymans 4513020064 cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-09 09:56:06 +00:00
V Sowmya 638dcf9a69 mb/google/hatch: Disable the SA IPU for hatch
This patch disables the SA IPU for hatch since it is
not using the IPU.

Change-Id: Ib2afc4cc4fd7ef98365b0b98130b0e8bc757ac2a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-09 09:52:57 +00:00
Tristan Shieh 26a52f492b google/kukui: Enable VBOOT_VBNV_FLASH to store VBNV in flash
Reading nvdata from non-volatile flash storage. With this patch, it will
pass the firmware test that corrupts FW_MAIN_A and boots up with
FW_MAIN_B.

BUG=b:80501386
BRANCH=none
Test=test_that --board=kukui 172.23.213.147 firmware_CorruptFwSigA

Change-Id: I9ef6bff019ee986ff018202bfd4d4a875526ec6c
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/30701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-01-09 09:51:01 +00:00
Matt DeVillier eaea9c987c samsung/lumpy: add cpu/gpu pwm backlight register values
Required for functional internal display on lumpy using
libgfxinit or Tianocore GOP driver

Test: boot/build lumpy, verify internal display functional
prior to OS driver loading.

Change-Id: If62a4ae58082548e8a645d1a2de40705bdd2946e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-08 22:36:21 +00:00
Duncan Laurie e55e61f889 mb/google/sarien: Set minimum assertion width values
Explicitly configure the minimum assertion width values to ensure
that they are set as expected and are not using unknown defaults.

Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08 19:13:13 +00:00
Duncan Laurie cae7944fc3 mb/google/sarien: Enable recovery mode GPIO
Enable the active-low recovery mode GPIO now that new boards are
available which have an external pull-up instead of a pull-down so
it can be asserted properly by servo.

This was tested on a Sarien system by holding the recovery button
on the servo board and tapping the cold reset button and ensuring
that it enters recovery mode.

Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08 19:13:03 +00:00
Duncan Laurie e11aeab132 mb/google/sarien: Remove power button ACPI device
These platforms use the standard fixed function power button
and do not need a second power button device declared or the
kernel will end up with two devices reporting the same event.

Change-Id: I6fe2b201a6a6f6307a0c4bd6a61f56cfcdd88bf4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08 19:12:54 +00:00
Arthur Heymans 6267f5dd11 sb/intel/i82801gx: Autodisable functions based on devicetree
This removes the need to synchronize the devicetree and the romstage
writing to FD.

Change-Id: I83576599538a02d295fe00b35826f98d8c97d1cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30244
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08 14:29:13 +00:00
Arthur Heymans 79a7ad6dda mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6
The southbridge has the function disable bits for port 5 and 6
strapped RO to 1 (disable).

Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-08 14:28:56 +00:00
Arthur Heymans d25109905a mb/{ga-g41m-es2l,d945gclf,rk886ex}: Fix devicetree
The devicetree was synced incorrectly with respect to the function
disable register set in romstage.

Change-Id: I189c5fdc433b5577ae008abf42878cdc6e3f2d52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30711
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-08 14:27:43 +00:00
Arthur Heymans a6ce5d3faa nb/intel/gm45: Remove the C native graphic init
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.

This way libgfxinit also gets build-tested by Jenkins.

Change-Id: I540cf08cef6ff7825694ebfa36e2e6437916e657
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/27016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07 23:08:41 +00:00
Maulik V Vaghela b6fe048910 mb/google/hatch: Enable touch panel support
Following changes are done to enable touch screen support on hatch
1. Enable I2C1 device at 400Khz at 3.3V
2. Configure GPIO for touch screen
3. Add ACPI entry for ELAN touch panel
4. update GPIO table with not connected GPIO pins for panel

BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.

Change-Id: I8dab07dad4cb197865bb9cf0e8da240810fcfabe
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-07 11:01:07 +00:00
Angel Pons 438f861663 src/mb/asus/p5qpl-am/romstage.c: Fix comment
Change-Id: I2b3ad53766bc9cef5ae00392814a03a3e177ad35
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30705
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07 10:39:08 +00:00
marxwang a3a2ffbe57 mb/google/poppy/variant/rammus: enable USB acpi
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.

BUG=b:119899987
TEST=build and flash to rammus, log into rammus and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.

Signed-off-by: marxwang <marx.wang@intel.com>
Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b
Reviewed-on: https://review.coreboot.org/c/30607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07 10:31:15 +00:00
Lijian Zhao aae963732c mb/google/sarien: Correct I2C bus clock for touchpad
Elan touchpad require connected i2c clock to be running at 400Khz, with
the modification can get 404Khz speed from Arcada EVT platform.

BUG=b:119628524
TEST=Build and boot up on Arcada platform, measure the i2c clock is
around 400Khz.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087
Reviewed-on: https://review.coreboot.org/c/30653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07 10:29:54 +00:00
John Su 08618bd2ab mb/google/sarien: Modify ELAN Touchpad i2c bus clk
Modify ELAN touchpad bus i2c clk from 466Khz to 400Khz.

BUG=b:119628524
BRANCH=master
TEST=measure ELAN Touchpad CLK

Change-Id: Ia8433c6ef320cea9a0145db4ba440d67ccd0f41e
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30588
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-07 10:29:36 +00:00
Elyes HAOUAS e414a4e5b5 src: Use "foo **bar" instead of "foo ** bar"
Change-Id: I8260424ee243c06827f2b5939e1568e52539b282
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-01-07 10:29:14 +00:00
Nico Huber 9faae2b939 Kconfig: Unify power-after-failure options
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
  0 - S5
  1 - S0
  2 - previous state

This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.

TEST=Did what-jenkins-does with and without this commit and compared
     binaries. Nothing changed for the default configurations.

Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06 15:54:19 +00:00
Arthur Heymans d2f678d3bd mb/google/slippy: Add a VBT for all variants
The vbt was extracted from the option rom found on stock images.
The vbt.bin is the same across all variants.

The VBT has a modified BDB block 43, the 'Backlight info block' such
that the inverter type for the panel in use is set to
2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE).
This only seems to matter on Windows, as without it changing the
backlight duty cycle does not work.

Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30487
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06 15:39:16 +00:00
Arthur Heymans 085a226808 superio/*: Link early initialization into bootblock
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK
bootblocks. It is likely unnecessary to do this in verstage.

This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM.

Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06 14:02:58 +00:00
Matt DeVillier 89393d633d mb/google/fizz: enable eist (enhanced speedstep)
Without eist enabled, fizz's CPU clocks are locked at the
base frequency, and don't scale up or down.  This prevents
fizz from idling properly and turbo boost from functioning,
so enable it (as is done for all other KBL boards)

Test: build/boot google/fizz, ensure CPU clocks scale as expected

Change-Id: I77dd0e1df1bf88f5bae18e9f832ca8d60fb777b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06 13:30:57 +00:00
Angel Pons 796bd74d63 src/mb/apple/macbookair4_2: move early_southbridge.c to romstage.c
This is done for consistency purposes. Also fix a small formatting issue
in a function.

Change-Id: I5dc170dbca59b7abbc912f9a26f76886b25ad82f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06 13:19:55 +00:00
Kyösti Mälkki a144e4d6fa device: Use pcidev_path_behind()
Change-Id: Iac16f9412d0e6aac908d873c61a4de3935e5318a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26518
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-06 13:10:27 +00:00
Kyösti Mälkki e7377556cc device: Use pcidev_path_on_root()
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-06 13:09:54 +00:00
Kyösti Mälkki c70eed1e62 device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-06 01:17:54 +00:00
Kyösti Mälkki de7f0736a1 mb/*/chromeos.c: Fix PRE_RAM and unify style
Change-Id: I99b9c0452ed0e6d580edb5a4f3317d776085b382
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:23:21 +00:00
Kyösti Mälkki 1de326460e mb/google/jecht: Rename save_chromeos_gpios function
We have init_bootmode_straps() defined for the same purpose.

Change-Id: Ia2692d8f8986247ea4ce889d6252d3c4c8b27bc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30398
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04 21:22:55 +00:00
Kyösti Mälkki 8803b21bbb amdfam10 boards: Use defaults for get_pci1234()
Note that while these boards had entry 0x0ff0 in comparison
to 0x0ffc of the get_default_pci1234() initialisation, the
implementation of get_pci1234() unconditionally overrides
the first entry.

Change-Id: I8bec612f84fe3c3a0c21fc1e10629368857e9c5e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:24:23 +00:00
Kyösti Mälkki f112f9f912 amdfam10 boards: Use defaults for get_pci1234()
All these boards use the same default initialiser.

As this is initialized late after device enumeration,
it can't really be used to alter platform configuration.

Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:56 +00:00
Kyösti Mälkki ee7e1300f4 amdfam10 boards: Drop array bus_sb700
Only bus_sb700[0] is evaluated.

Change-Id: Ie2cbbdebed3ae03da916d02919cd6a5d36f53562
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:44 +00:00
Kyösti Mälkki bf2d227135 amdfam10 boards: Drop array bus_sb800
Only bus_sb800[0] is evaluated.

Change-Id: I8ae0e6facbbe302b71692cf98a0292ee7d3bdca1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:31 +00:00
Kyösti Mälkki b30e2bfe34 amdfam10 boards: Drop array bus_sp5100
Only bus_sp5100[0] is evaluated.

Change-Id: I42a5040ea70a84fb674f2c616c6eba7b23dcdc29
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:23:17 +00:00
Kyösti Mälkki 6bc6c5548e amdfam10 boards: Use PCI_DEVFN()
Change-Id: I301ed4024f1dd6fb2009d59b2992830d4f17ee2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:49 +00:00
Kyösti Mälkki 651f4d231c amdfam10 boards: Drop array bus_sr5650
Values in the array are not used anywhere.

Change-Id: Iee92f903db97533709d54d1f214f2f23a1fab06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:33 +00:00
Kyösti Mälkki af9e459d12 amdfam10 boards: Drop array bus_rs780
Values in the array are not used anywhere.

Change-Id: I608b8c2e21bc515c56a27982815c1da43f3bb976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:22:04 +00:00
Kyösti Mälkki 228746b346 amdfam10 boards: Drop const variable sbdn_sp5100
Change-Id: I8756a81324ba3d4374bb6b06f7f0ddade6ba530f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:50 +00:00
Kyösti Mälkki af39e0ebc1 amdfam10 boards: Drop variable sbdn_sr5650
It mirrors value of sysconf.sbdn.

Change-Id: I3ea42280a1bdceffebb6b5c85aee18347734ee4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:38 +00:00
Kyösti Mälkki c9394017db amdfam10 boards: Drop extern on bus_sr5650 and sbdn_sr5650
Change-Id: I3b95ec5746077b49cd6dca64d0f884a3d1c362fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:22 +00:00
Kyösti Mälkki 58954d2bf3 amdfam10 boards: Drop variable sbdn_rs780
It mirrors value of sysconf.sbdn.

Change-Id: I3cb611f1ea33da19e63523bc0fe99f2792eebc57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:21:05 +00:00
Kyösti Mälkki 8052fe459c amdfam10 boards: Drop const variables sbdn_sb800 and sbdn_sb700
They evaluate to const zero and obscure PCI_DEVFN() use.

Change-Id: I8bd8dced62094d5ee8e957241ac29ead054f5c05
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:51 +00:00
Kyösti Mälkki 0571afe5d2 amdfam10 boards: Drop extern on bus_rs780 and sbdn_rs780
Change-Id: I7dc943f3376e9b706d3d486231525df85f806858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:38 +00:00
Kyösti Mälkki c0b1be0ba1 amdfam10 boards: Call get_bus_conf() just once
It has to be called once before PIRQ and MP table generation.

Change-Id: I238c6b4810404d320b36d4f6b4a161c1ff11c8d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:24 +00:00
Kyösti Mälkki a2cfe9e900 amdfam10 boards: Add Makefiles and fix resourcemap.c
Also remove global ramstage-y += get_bus_conf.c, this is
specific to amdfam10.

Change-Id: I49b604ebff6bcfe85518b2c3896ab798c3c7878d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:20:08 +00:00
Kyösti Mälkki d482c7dace amdfam10 boards: Drop global bus_isa variable
Value of the global is never evaluated.

Change-Id: I74106b0f5f033053288882a5bcd3c1dba3235ac0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-04 17:19:48 +00:00