The porting of Asus P8Z77-M mainboard required changing certain Super
I/O configuration registers that were ignored in devicetree.cb because
they aren't listed as resources. Add the declaration so they can be
changed.
This change is nowhere near enough as the current structure is
insufficient to allow changing configuration registers in the 0xE?
range, which this board also needs.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when
inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This Super I/O was not being built at all. Correct that.
Change-Id: Id053fa919cac7b2df6a6fc45aae5e34a0dc8c0ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
By undefining the configuration after use we're sure that nobody else
comes to depend on it without us noticing.
Change-Id: I7c5cfd58be643d6431989fc69cf3b397920590b9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The common PnP serial port DSDT code is intentionally included twice for
two serial ports with different LDNs. Undefine LDN and the PM register
name before redefining for second serial port so iasl doesn't complain.
Change-Id: I031905479c66698fb01da028e3f37d923396d2d9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41095
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMSC SCH5545 is very similar to the publicly available
datasheet for the SCH5627.
TEST=use PS2 keyboard and mouse, serial port, runtime registers and
Embedded Memory Interface on Dell Optiplex 9010
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If8a60d5802675f09b08014ed583d2d8afa29fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40350
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Really old versions of W83977TF Super I/O had an IR logical device, but
is no longer the case. It does not exist in the newer W83977EF version,
installed in some Asus P2B family boards, and served by this same code.
Add a config option on the off chance we may see board with it (as if
we would) and don't include this device unless it is set. Saves us from
the need to declare a not-present device off and/or extraneous PNP
device errors about a not-present device.
Change-Id: I761ebc41f1735a03e768339a68ca139167edc095
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41004
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Add LPC read/write functions for access aspeed's memory, also
create config data table to config memory and SIO. These
functions are used at early stages to configure devices.
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: Ib59c29a042b2c7bf196b8a5bd5218704d8075855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40483
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
.acpi_fill_ssdt() does not need to modify the device structure. This
change makes the struct device * parameter to acpi_fill_ssdt() as
const.
Change-Id: I110f4c67c3b6671c9ac0a82e02609902a8ee5d5c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40710
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Providing an explicit no-op function pointer is only necessary for
`.read_resources` and `.set_resources`. All other device-operation
pointers are optional and can be NULL.
Change-Id: I3d139f7be86180558cabec04b8566873062e33be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These two identifiers were always very confusing. We're not filling and
injecting generators. We are filling SSDTs and injecting into the DSDT.
So drop the `_generator` suffix. Hopefully, this also makes ACPI look a
little less scary.
Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: David Guckian
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Spec says if any object to control the power state exists, at least
D0 and D3 must be supported. And it seems Windows complains about the
missing D3 support: https://ticket.coreboot.org/issues/257
Windows reported `*** STOP: 0x000000A5` with the first parameter
`0x000000000000000D` (refers to a missing ACPI object) and the
third parameter `0x000000003353505F` which is the name of the
object in ASCII, little-endian (`_PS3`).
Change-Id: Ifa28a7c56575848e76e4a1c542866413b4c44d50
Signed-off-by: Nico Huber <nico.h@gmx.de>
Closes: https://ticket.coreboot.org/issues/257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Sometimes coreboot needs to compile external code (e.g.
vboot_reference) using its own set of system header files.
When these headers don't line up with C Standard Library,
it causes problems.
Create stdio.h and stdarg.h header files. Relocate snprintf
into stdio.h and vsnprintf into stdarg.h from string.h.
Chain include these header files from string.h, since coreboot
doesn't care so much about the legacy POSIX location of these
functions.
Also move va_* definitions from vtxprintf.h into stdarg.h where
they belong (in POSIX). Just use our own definitions regardless
of GCC or LLVM.
Add string.h header to a few C files which should have had it
in the first place.
BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I7223cb96e745e11c82d4012c6671a51ced3297c2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Define a chip option to explicitly soft reset all enabled GPIOs to
default state.
TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration
using nctgpio module and check whether GPIOs are reset after reboot
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iae4205574800138402cbc95f4948167265a80d15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.
Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is no reason to not disable the controller during resume. That
way, no ASL is needed.
Change-Id: I282a03647ee0958abb118fafe306abe5782db71c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace DSDT ACPI code and DSDT injection with a SSDT only solution.
The current implementation shows some issues on current Linux, which
might be due to external ACPI objects, which are then injected into
DSDT or the fact that those objects only use 3 characters.
Replace all the DSDT code with an SSDT generator.
Tested on HP Z220:
Boots into Linux with no ACPI errors. The SSDT can be disassembled.
Change-Id: I41616d9bf320fd2b4d8495892b8190cd2a2d057f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
As the SSDT generator for LDNs expects a "parent" PNP device
for proper ACPI code generation, validate that it is present.
Make sure the devicetree looks as expected and print a BUG message
if that's not the case.
Tested on HP Z220:
No BUG message was printed.
Change-Id: I6cbcba8ac86a2a837e23055fdd7e529f9b3277a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The specified PNP registers PNP_MSC0-E (F0-FE) are part of the iLPC2AHB
bridge's index/value interface. They are no one-time config registers
so we can't specify a sane value in the devicetree.
Thus, drop them to stop coreboot from complaining about the missing
entries.
Change-Id: I7d7f16845c755592317f140cca66cca12032f7a6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The datasheet uses "SWC" as shortcut for "System Wake-up Controller",
thus rename it in the code.
Change-Id: I8b3a14946e37f805d1c4e3df343dfcd7f67f6dc8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The authors from the header of the files are added in a previous commit.
Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the specification the register offset must be 0x71 instead
of 0x70.
Change-Id: Icf69ffc701a42a31a4545ce53c13e2c2554863e1
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now, Super I/O GPIOs can also be controlled directly through
access to I/O registers. VLDN 108 and specific I/O port from a range
<100h; ff8h> may be enabled in mainboard devicetree.
Change-Id: I4ce99bb44e6f5db684170f4190bdc38a944849f6
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35849
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
So far, only hard power off could reset GPIOs state to defaults:
IN, Open-drain. Now, defaults are set with every boot to ensure
that GPIOs are not in unknown/unwanted state.
Change-Id: I67878dbab2ddf0deaaa8f5d79416368c6164ba1d
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path
ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.
Fixes BSOD seen on Windows 10.
Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Always write a _HID, even for disabled PNP devices.
Fixes a BSOD on Windows 10.
Change-Id: I419a08bd6a3570fb4e1ae31bef4f9ccd6836fe1b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation
Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.
Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add functions to write ACPI SSDT code for entering and leaving
the config mode.
To be used by ACPI generators.
Tested on Linux 5.2 using the Aspeed SSDT generator.
Change-Id: I14b55b885f1c384536bafafed39ad399639868e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The AST2500 is similar to the AST2400, but it also supports ESPI mode.
In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable.
Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-1 shouldn't be assigned to an unsigned variable, so use an otherwise
unused constant here. Since 7 is the highest virtual LDN number, using
0xffff as PNP_SKIP_FUNCTION marker has no unwanted side effects.
Change-Id: I5e31e7ef9dad5fedfd5552963c298336c533a5e9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use the functions defined in device/pnp.h instead of using the
conf_mode directly.
This will make future refactoring easier.
Change-Id: Ibb94d86b3ee861f44cded469ff58b545dd7311fd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If multiple devices are behind a dev, we would only recognise port 0. We
need to scan the complete 'bus'.
Tested on ASpeed AST2500
Change-Id: Id80a2ae6e82c151b8d8adc9c5f35f38362d538fa
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37607
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Working on some other code, I noticed that superio/aspeed was added as
an include path even though I wasn't using it. I investigated and found
that NOTHING is using it. The files in the aspeed directory all
reference files in their own directory.
The supermicro x11-lga1151-series boards are the only ones using this
SIO.
TEST=util/abuild/abuild -t supermicro/x11-lga1151-series
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I377066451a50452c17c9bfaa0f815f69e039984e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some mainboards with an ASPEED BMC do the serial routing setup in the
BMC boot phase on cold boot. This results in scrambled console output
when this is not finished fast enough.
This adds a delay of 500ms as workaround in the BMCs uart setup that
can be selected at mainboard level.
A user may disable the workaround when using another BMC firmware like
OpenBMC, u-bmc or some custom BMC bootloader with fast serial setup.
Change-Id: I7d6599b76384fc94a00a9cfc1794ebfe34863ff9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36591
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This port is based on NCT6776
Change-Id: Ib8d64e8faa74802ab0213d87881e57d4d9bd1c35
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35028
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change d3a1a417 "src/superio: Remove unused superio chips" removed
all unused devices except for ones used on mainboards still under
review. The SMSC 1036 was inadvertenly also removed as well. This
device is used in debug cards that may be connected to AMD CRBs.
This patch restores the smsc1036 directory as-is and then corrects
the following lint messages.
* WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
* ERROR: else should follow close brace '}'
* WARNING: braces {} are not necessary for single statement blocks
Change-Id: I851826e12032f802b9b2ff86d5a0eb99871bee6d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36119
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These SIOs are not being used or tested by abuild, so remove them from the
tree. The only 3 currently unused SIOs that don't get removed here have board
ports in review.
src/superio/fintek/f71805f
src/superio/fintek/f71872
src/superio/intel/i8900
src/superio/ite/it8671f
src/superio/ite/it8716f
src/superio/nsc/pc87309
src/superio/nsc/pc87360
src/superio/nsc/pc87366
src/superio/nsc/pc97317
src/superio/smsc/dme1737
src/superio/smsc/lpc47b272
src/superio/smsc/lpc47b397
src/superio/smsc/sch4037
src/superio/smsc/sio1036
src/superio/via/vt1211
src/superio/winbond/w83697hf
src/superio/winbond/wpcd376i
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I61d486d2c1e2b85eb292eaa78316c36e1735ebf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Nuvoton and Winbond use the same off-by-5 indirect address space to
access their hardware monitor/environment controller in the SIO chip, so
move this to a common location and replace the inb/outb calls with the
corresponding inline functions from device/pnp.h
Change-Id: I20606313d0cc9cf74be7dca30bc4550059125fe1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The new name should reflect better what this function does, as that
is only one specific step of the scanning.
Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found by Coverity Scan #1405310
Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35433
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ITR2 is specified twice here, which leads to the following error message
in Linux:
[ 0.263591] ACPI BIOS Error (bug): Failure creating named object
[\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633)
Add comments and fix duplicated field.
As there are no users of this code yet, just rename the fields.
Tested on Supermicro X11SSH-TF.
Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35294
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the new SuperIO ACPI generator to make includes in DSDT obsolete.
Manually tested on X11SSH-TF and verified that ACPI tables are correct.
Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33253
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.
It generates a device HID based on the decoded I/O range.
Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.
Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
resource settings on specific LDNs
Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.
Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add f81803A plus the capability to control the fan with any fintek SIO.
This will be done through a common API, though currently only F81803A will
have it implemented.
BUG=none.
TEST=Tested later with padmelon board.
Change-Id: I3d336e76bccc38452b1b1aefef5d4a4f7ee129a8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SUPERIO_NUVOTON_NCT6776_COM_A symbol should only be visible if
SUPERIO_NUVOTON_NCT6776 is selected as well.
Change-Id: I9c52d596080360bf3fc25265749ced66ec44f5dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33440
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Like the NCT6776, the NCT6791D has muxed COMA/GPIO8 functions. Since it
requires setting different bits, add a new Kconfig symbol to do it.
Change-Id: I62dc18810026f9b1550da19950f66af605600ec8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on IT8786E-I V0.4.1 datasheet with following remark:
"Please note that the IT8786E-I V0.4.1 is
applicable only to the D version."
Signed-off-by: Kyösti Mälkki <kyosti.malkki@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add more registers and make them optional, so they keep untouched/
their default if omitted.
Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change adds support for the SuperIO chip IT8613E. This chip uses
FANs 2-5 and has SmartGuardian always enabled (no ON/OFF control) so
it relies on support in common ITE code. LDNs were taken from IT8613E
Preliminary Specification V0.3.
Change-Id: I73c083b7019163c1203a5aabbef7d9d8f5ccb16a
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some ITEs have more than 3 independent FAN controller outputs. As the
initial implementation assumed only 3 outputs some registers are not
consequently numbered. This change adds macros for accessing those
registers.
Additionally some chips have SmartGuardian always enabled, without the
option for turning it off. For these chips bits that were responsible
for ON/OFF control are either reserved or have different meaning.
Another Kconfig option is added to disable ON/OFF functionality on
platforms that do not support it.
Change-Id: Icd60a16b6b5583a3b981bdc220aac472c2a8f40f
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/31616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There was CONFIG_ prefix missing in SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
option, this patch fixes it.
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I52919671569175141560cb73e42344aa1725c112
Reviewed-on: https://review.coreboot.org/c/31674
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c
Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for the SuperIO part of IT8528E
* Based on the IT8528E datasheet and tests on vendor firmware
TODO: Add support for accessing EC space, which should be
implemented in src/ec/ instead, as it's a separate logical unit.
No datasheet is publicy available.
Tested on wedge100s.
The serial works under the OS without CONFIG_CONSOLE_SERIAL.
Change-Id: I72aa756e123d6f99d9ef4fe955c4b7f1be25d547
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The two IO regions of the keyboard controller are 1 byte long, not 8.
Change-Id: I7319ce9f84181759f4dc7b59c0020f3a5dd5dc03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The IO mask shouldn't contain zeros inside the block of ones.
Change-Id: Icfebbf1d1d88ceef58800339bf899931fdc61ab7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/30954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows to set up the SuperIO in the C_ENVIRONMENT_BOOTBLOCK
bootblocks. It is likely unnecessary to do this in verstage.
This also renames COMMON_ROMSTAGE to COMMON_PRE_RAM.
Change-Id: I3d999611baa1e79c79fe6b1f01822ebaa5f85daf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There are no public datasheets for this SuperIO. The results are from probing
the registers manually.
Change-Id: Ie5659533c5f224603f918d17942a7057e6701222
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no public datasheet available for this SuperIO so the resources are
guessed by looking at other ITE SuperIO's and the register dumps while running
vendor firmware.
The only board with this SuperIO in the tree is the asus m5a88-v. Most of the
devicetree entries would have been invalid here so one should not worry too much
about regressions.
Tested with Foxconn d41s.
Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The existing code for modifying the power state after power loss of the system
only implemented the transitions from power off to either power on or power keep
properly.
Since I don't have a board with this chip, I couldn't test the patch on real
hardware. The two cases described above were tested before the original patch
was merged, so I'd expect this to work.
Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The implementation of wpcd376i in coreboot is based on the
superiotool output which apparently was incorrect. This
patch refines the implementation to match the datasheet.
Change-Id: I0108e912dc4f603276074f0999c6d3146c3b13f9
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
By defining SUPERIO_KBC_PS2M, ACPI code is added to show the PS/2 mouse.
This has been tested on an ASUS P8H61-M LX with Linux 4.9.110 and
4.17.8. In each case, the PS/2 mouse works automatically, whereas it was
not detected before.
Change-Id: I7983f85b3fd23547950f1f75a81bbca63c63d52b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When compiling for the ASUS P8H61-M LX, IASL 20180531 emits the
following remark: "Control Method should be made Serialized (due to
creation of named objects within)". Making the appropriate methods
Serialized eliminates these remarks.
Change-Id: I8e95d9a00a629a2f904c79b78fac20810327ed37
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27796
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Exposing the parallel port via ACPI causes Linux to automatically detect
the parallel port and load the appropriate modules. Tested on an ASUS
P8H61-M LX with Linux 4.9.110 and 4.17.8.
However, no parallel port device has been tested.
Change-Id: I2529a074e24433d093ad0650a45c7b29238620f3
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The constant used in the ACPI code is NCT6776_SHOW_KBC, so update
the comments to reflect that.
Change-Id: I9ba69384866088f84a516557d76864104a024968
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/27794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch makes it possible to enter the config mode of the super IO chip, so
that changes can be made to the configuration registers.
Change-Id: I7e31eaf217b3af2226c1e7d2f14f2ef7b0d7ddbe
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I4311834f3970bd3471f2f5a73ca7da3c03936d37
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The pnp ops struct is already passed to the pnp_enable_devices function and it
is used if no override is supplied in the elements of the pnp_info struct array
Change-Id: I14dbeda9832a25116cf53c36197615e9d02d5134
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
