Commit Graph

459 Commits

Author SHA1 Message Date
Patrick Georgi 88f55b2c12 some progress on kconfig:
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
  the socket it has, and the CPUs are pulled in automatically. There is
  some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
  - intel/eagleheights
  - intel/jarrell
  - intel/mtarvon
  - intel/truxton
  - intel/xe7501devkit
  - sunw/ultra40
  - supermicro/h8dme
  - tyan/s2850
  - tyan/s2875
  - via/epia
  - via/epia-cn
  - via/epia-m
  - via/epia-m700
  - via/epia-n
  - via/pc2500e
(PPC not considered, probably overlooked something)

All of them only _build_, but some options are probably completely
wrong. To be fixed later

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 18:43:02 +00:00
Myles Watson ed03556fbf src/Kconfig: Remove HT-specific options.
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.


Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 21:29:32 +00:00
Myles Watson a74ae635ca failoverR.diff: Revert my failover change since Kconfig only supports fallback.
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 18:53:50 +00:00
Rudolf Marek eed10364ce As more users of Asus M2V-MX SE emerged. Here is long pending patch I wanted to
write. It boots the SB/NB V-link performance to full duplex 533MB/s. (in fact x2
for FDX)

The default was 266MB/s but half duplex only. If you encourage any stability
issues we need to look into fine tuning the bus. The values are VIA recommended.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-01 15:29:12 +00:00
Ronald G. Minnich 6ed39d9786 This is the final set of changes to allow rumba to build. Rumba is not
tested. I also addressed questions raised by Uwe: 
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
UDELAY_TSC

Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in 
the mainboard Kconfig. The remaining question of Uwe's is a deeper 
problem:

---
We'll have to check if this works. From a quick glance
the Rumba does not have the mmx related lines (which _are_ in
Makefile.romccboard.inc, though):

crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
---

We're going to need a whole variant of this standard mainboard OR
we're going to have to make (some) of the unconditional includes above 
conditional. 


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-29 02:59:35 +00:00
Arnaud Maye 5b1d51ba2e This patch adds VGA and PS/2 Keyboard/mouse support to the already existing intel truxton (ep80579) dev board.
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.

Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 20:42:21 +00:00
Uwe Hermann 84a0f54b3b Add kconfig support for all Intel 82810 (i810) boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:38:42 +00:00
Ronald G. Minnich 07b8c2d26b This is the beginning of support for Geode and Kconfig in v2.
It also brings in the vsm from v3, which was a much cleaner cut. 

Over time, I hope to bring all the code back from v3. I have 
some rumbas at home and want to use them.

I have a patch which comes in next that makes the rumba build. 

Note that I am holding the src/*/amd/Kconfig patch until these get merged.
These have no impact on the current system. 

Note that this is not complete but I want to fill in the blanks bit 
by bit. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 14:46:59 +00:00
Uwe Hermann 05c1e9c81c Silence unneeded #warnings, change to code comments (trіvial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 13:42:24 +00:00
Cristi Măgherușan ea906b0e4e Added support for the AMD RS690 and SB600 southbridges in Kconfig
Signed-off-by: Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4601 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 21:39:20 +00:00
Carl-Daniel Hailfinger 5a5b8f5ba9 The new resource allocator helped me find a bug in SB600 diagnostics.
The SB600 SATA code printed that two BARs had the same address because
it didn't mask the correct number of bits in the BAR.
Functionality was not affected, but the debug output was incorrect.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-27 04:30:47 +00:00
Patrick Georgi 62b3513d63 Remove a couple of CONFIG_ prefixes that shouldn't have happened.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 18:14:30 +00:00
Libra Li f608205c35 Enable Direct TMDS for the RS690, which allows to display on HDMI and DVI
monitors.

Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 16:04:47 +00:00
Uwe Hermann 5ec2c2b998 Various Kconfig and Makefile.inc fixes and cosmetics.
- Whitespace fixes, remove trailing whitespace, use TABs for identation
   (except in Kconfig "help" lines, which start with one TAB and two spaces
   as per Linux kernel style)

 - Kconfig: Standardize on 'bool' (not 'boolean').

 - s/lar/cbfs/ in one Kconfig help string.

 - Reword various Kconfig menu entries for a more usable and consistent menu.

 - Fix incorrect comment of NO_RUN in devices/Kconfig.

 - superio/serverengines/Kconfig: Incorrect config name.

 - superio/Makefile.inc: s/serverengine/serverengines/.

 - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.

 - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.

 - mainboard/via/epia-n/Kconfig: Fix "bool" menu text.

 - console/Kconfig: Don't mention defaults in the menu string, kconfig
   already displays them anyway.

 - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 00:53:22 +00:00
Myles Watson 50d0b8ce17 Add support for Nvidia Southbridges to Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-24 18:36:02 +00:00
Ronald G. Minnich dc9cabd6c3 Add via south support. Correct usage of conditional variables.
Note the makefile.inc may be out of date given the new commits of code
today, but this is what was signed off ...

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4551 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-18 17:14:58 +00:00
Jon Harrison 9c2e738653 Add the rest of the files.
Thanks Jon.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-18 15:12:13 +00:00
Jon Harrison 1825be291f Get the Via EPIA-N(L)/CN400 to a reasonable level of maturity::
Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
kernel) from SATA HDD.

ACPI is working for PCI interrupt routing, some memory stuff and
Soft-Off.
USB/SATA Working
VGA Console Working
X Working via Onboard AGP

Removed dsdt.c, fixed some whitespace.

Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-17 17:09:46 +00:00
Stefan Reinauer 109ab317e7 drop extra whitespace at end of line for i945 + ICH7 (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 16:08:05 +00:00
Ronald G. Minnich fd4519b5ef This now builds.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:56:17 +00:00
Ronald G. Minnich 9a94843820 Missing files from last patch.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:26:31 +00:00
Patrick Georgi 0588d19abe Kconfig!
Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:00:51 +00:00
Patrick Georgi dec1b47bd7 Add some more CONFIG_* prefixes that were missing.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-05 12:24:23 +00:00
Luc Verhaegen aeb6c9870f sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
and through the general vga infrastructure i committed a month or two ago.
Add videoram_size option for k8m890 and the Asus M2V-MX SE.

Now the Asus M2V-MX SE will magically come up with a working standard VGA
80x25 textmode.

Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
of its components; this vga bringup was a breeze thanks to your hard work
for this excellently supported board. And separate thanks to Rudolf Marek
for spurring me on and for providing a register dump.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-23 16:04:58 +00:00
Stefan Reinauer aecf2511c6 Another include file slipped. This gets via/epia-m building again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 22:01:21 +00:00
Stefan Reinauer 573f7d40be Intel ICH7 updates
- code restructuring (move ich7 out of i945)
- ACPI fixes 
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:50:34 +00:00
Stefan Reinauer 925b6c0c43 * cleanup ricoh rl5c476 code:
- drop duplicate udelay function
  - simplify code flow
  - some cosmetics on comments

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 20:27:00 +00:00
Myles Watson 28f17dbf6b Add legacy I/O region for vt8237r southbridge.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4443 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-20 19:42:15 +00:00
Patrick Georgi 85a94f66b2 Rename some preprocessor symbols. I have no idea why
those symbols were left alone before, after this, they're
somewhat more in line with the rest of the tree.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-20 19:34:47 +00:00
Stefan Reinauer 3839a8ebd8 trivial fixes to function declarations (and build system test)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-14 19:10:10 +00:00
Ed Swierk e42e142d9f Apparently I'm not the only one who forgets which way the outb and
outl arguments go.

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10 15:05:35 +00:00
Zheng Bao 7d4fd2c108 This seems to be a more official, common, simple way to check if the CPU is dual core or
single core.


Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-10 03:42:13 +00:00
Myles Watson 29cc9eda20 Move the v3 resource allocator to v2.
Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-02 18:56:24 +00:00
Thomas Jourdan 1a692d8176 Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 17:01:17 +00:00
Jon Harrison 9a7368d4b7 I missed three files.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 13:19:25 +00:00
Stefan Reinauer 0867062412 This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:17:49 +00:00
Harald Gutmann 62cfe169fa ChangeLog:
Add initial ACPI support for M57SLI.
	Activates/Enables:
		* native Coreboot ACPI for M57SLI
		* Soft-Power-Off
		* PowerNow!
		* High Precision Event Timer
		* Windows booting with ACPI support

Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-19 12:03:40 +00:00
Carl-Daniel Hailfinger 87e7050bff die() does never return. Annotate it as such.
Any endless loop after die() can be eliminated.
Dereferencing a NULL pointer is bad. die() instead.
Replace endless loops with die().

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 11:41:51 +00:00
Zheng Bao 28d71b9445 After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.

Tested on dbm690t.

Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.

http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-05 10:00:07 +00:00
Zheng Bao d11bd003c6 This patch is about some noticable bugs which was made by no reason.
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
  (1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
      In rpr 5.10.2, step 2, step 2.1 & step 2.6
  (2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
      instead of PCIEIND_P: 0x20.
      In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-04 01:57:03 +00:00
Luc Verhaegen a9c5ea08d0 Revert "CMOS: Add set_option and rework get_option."
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.

Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 14:19:33 +00:00
Luc Verhaegen 9ceae905f1 CMOS: Add set_option and rework get_option.
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.

get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.

The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.

build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 10:47:19 +00:00
Zheng Bao a922b3195b Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 03:15:05 +00:00
Rudolf Marek a519fe77b6 Following patch moves all vt8237 fadt.c from mainboard/* file to chipset
directory just with one common file.

Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
Change the compiler to CORE , its revision to 42. 

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-31 17:00:25 +00:00
Joseph Smith 60f0f1b18f enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-29 13:45:22 +00:00
Stefan Reinauer 069385fcb3 ops can not be const because of the pci conf1/conf2 hackery we do. trivial
patch, just removes the warnings like
coreboot-v2/src/southbridge/intel/i82801xx/i82801xx_ac97.c:73: warning: initialization discards qualifiers from pointer target type


Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-26 12:58:00 +00:00
Joseph Smith 5f0482dd8b Oops forgot small part. Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-13 02:47:14 +00:00
Myles Watson 0520d55f5b This patch adds high table support to qemu. It was already added to
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c

It also adds a driver for the ISA device that is found when using
0.9.1  If you look in a log without this patch you won't find the RTC
init lines.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-11 22:44:14 +00:00
Joseph Smith 4f0154c937 Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 21:30:57 +00:00
Stefan Reinauer 88e71e8859 Run dos2unix on all files:
find . -type f| grep -v svn | xargs dos2unix

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 12:42:30 +00:00
Joseph Smith a0dbddff17 Trivial, update email address.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 00:59:03 +00:00
Joseph Smith 03c65ef4e7 This is a patch to use another IRQ besides IRQ12 to fix conflicts with i8042 - PS/2 Mouse.
Signed-off-by: Joseph Smith <joe@settoplinux.org> 
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-01 04:53:58 +00:00
Myles Watson fa12b67771 Remove warnings from compilation of the s2892 with and without CBFS.
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.

For shadowed variable declarations I renamed the inner-most variable.  

The one in src/pc80/keyboard.c might need help.  I didn't change the
functionality but it looks like a bug.

I boot tested it on s2892 and abuild tested it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 22:45:41 +00:00
Stefan Reinauer 870f0133f4 fix warning: no return statement in function returning non-void
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4226 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-28 14:49:50 +00:00
Mondrian nuessle d9b1c4f42f This patch adds support for the BCM21000 (aka HT-2100)
PCIe bridge.

Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4182 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 20:27:53 +00:00
Rudolf Marek 299a00feb8 Fix the build. This error was introduced by change in acpi.c, the acpi_slp_type exists only conditionally.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
 


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 21:42:49 +00:00
Rudolf Marek 497c8effce Following patch adds support for resume on VT8237 based motherboards. The NB
part of this patch adds support for resume well NVRAM. In which DQS values are
stored.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-13 18:00:09 +00:00
Stefan Reinauer df77f345e7 (trivial) fix some warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4076 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-06 14:00:53 +00:00
Stefan Reinauer 85107f28da two more totalimpact briq fixes. Gets us back to the romfs breakage on PPC
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-05 08:39:13 +00:00
Stefan Reinauer dd0b6ff4dd fix this warning for the embedded planet ep405pc
/tmp/ccilLWBf.s: Assembler messages:
/tmp/ccilLWBf.s:144: Warning: setting incorrect section attributes for .rodata.pci_driver

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-04 22:24:23 +00:00
Rudolf Marek 9e9fa825fd To make use of HAVE_HIGH_TABLES following patch is needed. Also, it moves
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-21 11:50:20 +00:00
Stefan Reinauer be7f79867e This, ladies and gentlement, is commit #4000.
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 15:42:27 +00:00
Stefan Reinauer cc46e73a02 ACPI implementation for i945, ICH7, Kontron 986LCD-M
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-13 00:44:09 +00:00
Stefan Reinauer a8e1168064 This patch contains some significant updates to the i82801gx component and will
be required for a series of later patches. Roughly it contains:

* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info 
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
  some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-11 14:54:18 +00:00
Myles Watson 283a494521 This patch adds common elements for ck804-based boards.
changes by file:
src/northbridge/amd/amdk8/northbridge.c:
	Add high tables code ala Stefan's code for the i945.

src/southbridge/nvidia/ck804/ck804_lpc.c:
	Enable High Precision Event Timers.
	Add pm_base for ACPI.

src/southbridge/nvidia/ck804/ck804_fadt.c:
	Since fadt is only dependent on the Southbridge, add it here.

src/southbridge/nvidia/ck804/Config.lb:
	Compile in ck804_fadt.c

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-10 20:39:27 +00:00
Stefan Reinauer 3b387458b5 * fix a minor power state issue in the ich7 smm handler
* move mainboard dependent code into a mainboard SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:52:36 +00:00
Stefan Reinauer ae762b5d3b use include file for i8259 where appropriate (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3980 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 18:39:54 +00:00
Carl-Daniel Hailfinger 51001fbd81 I just went on a bugfix frenzy and fixed all printk format warnings
triggered by the AMD 690/SB600 targets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-04 01:06:41 +00:00
Stefan Reinauer 2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
Stefan Reinauer 5389c7f72b - Fix up amd pistachio and dbm690t.
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
  on some platforms.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-15 02:53:18 +00:00
Myles Watson 552b327ca3 This patch converts __FUNCTION__ to __func__, since __func__ is standard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-12 21:30:06 +00:00
Myles Watson c4ddbff706 Remove some warnings, mainly from format strings which didn't match the
arguments.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-09 17:52:54 +00:00
Dan Lykowski 4505948fae Use the correct device for switching on HDA.
Reorder HDA (HD Audio) init:
The reordering was based on what order things happen in the BIOS
Developers guide, RPR, and SATA driver. I fixed the order of the devices
that didn't matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec

The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.

Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
bits.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>

Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.

Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
but some warnings remain.

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-05 02:18:42 +00:00
Maggie Li cab81c03eb Fix rs690 bug about GPPSB configuration.
Signed-off-by:  Maggie Li <maggie.li@amd.com>
Reviewed-by:    Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-23 22:16:13 +00:00
Stefan Reinauer 679c9f9299 forgot to svn add
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> 



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:54:59 +00:00
Stefan Reinauer 54309d637a Update Kontron board
- use new features of the ich7 update
 - move rambase above 1M to avoid memory trashing through SMM relocation
 - enable superio HWM

Update ICH7 driver

 - minor smi cosmetics (in progress)
 - add real ac97 driver
 - add real azalia driver
 - fix some interrupt issues
 - fix some sata issues 
 - include Patrick's fix for _lpc.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 22:53:10 +00:00
Stefan Reinauer 269563a423 First shot at factoring SMM code into generic parts and southbridge specific
parts.

This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19 21:20:22 +00:00
Dan Lykowski 6912846dda Adds a retry/faildown to SB600 SATA detection logic.
SATA port status kept returning 0x1: BAR5+po+28h
1h = Device presence detected but Phy communication not established

This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g.

Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-15 02:35:30 +00:00
Carl-Daniel Hailfinger 1d7db86b6b The SB600 RPR documentation does not mention what to do if SATA_BAR0+6
is no longer 0xA0 or 0xB0. It simply assumes that will never happen.
My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the
first init after poweron.
The current code hangs forever with my drive. Fix this by rerunning the
init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0.

Add support for SATA port 2-4 (Primary Slave, Secondary Master,
Secondary Slave).

If only the 2nd SATA port is connected and the hardware acts strangely
(contrary to documentation), it will print the error message below and
continue anyway. The official AMD asm code behaves the same way.
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 23
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
[8 repetitions]
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
Primary Slave device is not ready after 10 tries

Activate and improve debug messages for SPEW log level.

Fix some comments.

New log messages look like this:
PCI: 00:12.0 init
sata_bar0=3020
sata_bar1=3060
sata_bar2=3030
sata_bar3=3070
sata_bar4=3000
sata_bar5=fc309000
SATA port 0 status = 23
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
[... 281 repetitions ...]
0x6=0, 0x7=50
drive no longer selected after 2820 ms, retrying init
drive detection done after 0 ms
Primary Master device is ready after 2 tries
SATA port 1 status = 23
drive detection done after 0 ms
Primary Slave device is ready after 1 tries
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3

With this patch, my Asus M2A-VM boots into Linux without problems.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-29 09:35:00 +00:00
Carl-Daniel Hailfinger 33f9633184 Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.

Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>

Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 17:20:46 +00:00
Maggie Li b96af1ea60 Fix implicit declarations of pci_read_config32 and pci_write_config32 in
the SB600 code.

Signed-off-by: Maggie Li <Maggie.li@amd.com>
Reviewed-by: Zheng bao <Zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-23 02:22:07 +00:00
Carl-Daniel Hailfinger eb30bf8ba2 Fix implicit udelay src/southbridge/nvidia/mcp55/mcp55_aza.c
Fix imlicit mdelay in src/southbridge/nvidia/mcp55/mcp55_nic.c

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-22 16:19:02 +00:00
Corey Osgood e562f7258e Fix a LOT of implicit function declarations before they become errors.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 03:36:48 +00:00
Corey Osgood 809242a715 Fix implicit declaration in cn700/vt8237 code
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 19:37:11 +00:00
Myles Watson 43bb9cdddd This patch gets rid of all the implicit definition warnings for serengeti except get_nodes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-18 18:24:11 +00:00
Zheng Bao bb069e1f69 Add 690G and 690(MT) internal graphics support.
The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F

This fixes booting on 690G.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-17 02:14:24 +00:00
Stefan Reinauer 045c348cf3 Move mainboard specific changes to the coreboot memory table into the
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-13 20:51:34 +00:00
Carl-Daniel Hailfinger 42f03e5647 Improve comments in early SB600 setup, handle non-LPC strapping and
document verification against the data sheets.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Maggie Li <maggie.li@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-12 03:40:21 +00:00
Rudolf Marek 31e52e61aa The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.

Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.


Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-04 23:37:12 +00:00
Joe Bao 40d46ba383 Add AMD rs690 VID DID reporting and some minor cleanups.
Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 19:49:57 +00:00
Joe Bao 164463c551 Add AMD sb600 HPET setup and some minor cleanups.
Signed-off-by:  Joe Bao <zheng.bao@amd.com>
Reviewed-by:    Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-01 19:37:21 +00:00
Stefan Reinauer e35d5e3fa2 drop dead code in sb600 hda
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3752 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-14 13:43:26 +00:00
Uwe Hermann 65ebc791c1 Drop #defines for registers that are not existant on the ICH7.
Also, fix BIOS_CNTL, which is 0xdc on ICH7.

Build-tested with kontron/986lcd-m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:24:05 +00:00
Uwe Hermann 556801eb61 The enable_hpet() code in intel/i82801gx will not work with the
ICH7 southbridge (but it might work with ICH4/ICH5 or so).

The ICH7 needs a different init code. Drop the non-working code for now.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-06 22:23:05 +00:00
Uwe Hermann 91df5619db Trim down the list of southbridges supported by the i82801xx driver
to only a set of reasonably similar ones, namely (for now) ICH0* - ICH6*,
and C-ICH.

All later ICH* southbridges (ICH7-ICH10) are _very_ different and were surely
not working with this driver anyway (and there's no chance to support
them reasonably with this driver without ending up in #ifdef hell).

ICH7 now has an extra driver in svn, whether ICH8-ICH10 are similar
enough to be supported by that ICH7 driver remains to be seen.

This patch was informally acked by Stefan Reinauer
<stepan@coresystems.de> on IRC.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-11-02 14:33:51 +00:00
Uwe Hermann 5d7a1c844e Revert i945/ICH7 PCI IDs to be hard-coded numbers instead of #defines.
Build-tested on kontron_986lcd_m.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-31 18:41:09 +00:00
Uwe Hermann bddc693e8d i945/ICH7: Use #defines from pci_ids.h (trivial).
Build-tested with the kontron/986lcd-m target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 13:51:31 +00:00
Stefan Reinauer debb11fc1f Support for the Intel ICH7 southbridge.
This includes an early SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:46:52 +00:00
Uwe Hermann 039255c59c I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'.
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.

Build-tested with the AMD dbm690t target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 16:27:38 +00:00
Uwe Hermann 97f56a4b7e Add missing license header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-21 15:07:53 +00:00