Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.
Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.
Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.
BUG=b:62200225
Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.
Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.
Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable without an initializer will default to 0 hence no
need of an explicit initialization.
Change-Id: I208d5e475600b102cd3d972919b170c10c790b32
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.
TEST=Build and boot on soraka/eve/reef/cnl-rvp
Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.
Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some prototypes types don't match the actual function type, though there's
no error message due to the types being alias. For clarity, types should
match between prototypes and actual functions.
BUG=b:68007655
Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.
Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.
BUG=b:66339938
Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
An upcoming PSP firmware change will allow coreboot to load the two
SMU firmware blobs (one runs in SRAM and the other in DRAM). The
traditional method is for the PSP to control most of the process,
e.g. loading the SRAM version prior to releasing the x86 reset.
Add a new command that can instruct the PSP to load a firmware blob
from a location in the flash.
The definition for commands 19 and 1a differ from others in that they
do not use a command/response buffer. Instead, the PSP will look in
the command/response pointer registers directly for the blob's
address.
BUG=b:66339938
Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.
BUG=b:62241048
Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Convert functionality to use coreboot-centric functions and defined
values. This change should have no functional effect.
BUG=b:62241048
Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add APIs and required parameters for creating Dialog da7219 SSP
endpoints in NHLT table.
The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render vs capture) along with
their supported formats.
BUG=b:68686020
TEST=check that NHLT table for da7219 is created properly
Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.
Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.
Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Remove the definition for the PSP PCI device from the common PSP
code. Any APU using this source should have its own definitions,
and this allows for the device to move within the config space.
Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Take the existing scattered around address space defines
and put them in iomap.h.
Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.
Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have macros for register addresses. Use it for MMIO_CONF_BASE
instead of duplicating a literal again.
Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Hex constants need '0x' prefix. Clearly these weren't being used,
but they should be fixed properly.
Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
By definition in C, fields that are not explicitly initialized will
be zero'd out. Therefore, remove the redundant struture field
initialization.
Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Global variables that are unitialized in C programs reside
in the .bss section. By definition, this section is cleared
to 0. Therefore, remove the explicit NULL initialization because
it's completely unnecessary.
Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
memset() exists for a reason. There's 0 reason to duplicate the
functionality but add extraneous parameters that do nothing. This
is just poor coding practices. Remove LibAmdMemFill() usage.
BUG=b:62240746
Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos"). Avoid this bug in the future.
Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
`NULL` already has that type in coreboot.
```
src/include/stddef.h:#define NULL ((void *)0)
```
Change-Id: I73aeaef178be8779020c436732952aa732e90c46
Reported-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Use the correct conversion specifier for `size_t` to fix the error
below.
```
from src/soc/intel/quark/spi.c:18:
src/soc/intel/quark/spi.c: In function 'xfer':
src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \
of type 'long int', but argument 3 has type 'unsigned int' \
[-Werror=format=]
printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
^
```
Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the warning below by making the integer literal unsigned.
```
CC bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
alignment = 1 << (log2_ceil(window_size));
~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)
Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Make the format of two multi-line comments compliant with the coding
style.
Change-Id: I8bc7b1eb175957b76ca19acdcb29b06ae86429b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add Apollo Lake CPU device ID for E0 stepping.
Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.
Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Delete the LPC I/O decode configuration from fixme.c. This code is
superseded by early_setup.c.
Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #defines that will allow easy use of PCI devices across stages.
Future work can convert soc/amd/stoneyridge to use these and clean
up the DEV_D18F4 macro still in place.
Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.
Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #define values for the HPET device. In Stoney Ridge, the base
address is fixed and cannot be relocated.
Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses common SCS library to set up sd card.
Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
