Fix the warning below by making the integer literal unsigned.
```
CC bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
alignment = 1 << (log2_ceil(window_size));
~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```
Found-by: Clang static analyzer scan-build
(clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)
Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Make the format of two multi-line comments compliant with the coding
style.
Change-Id: I8bc7b1eb175957b76ca19acdcb29b06ae86429b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add Apollo Lake CPU device ID for E0 stepping.
Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.
Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Delete the LPC I/O decode configuration from fixme.c. This code is
superseded by early_setup.c.
Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #defines that will allow easy use of PCI devices across stages.
Future work can convert soc/amd/stoneyridge to use these and clean
up the DEV_D18F4 macro still in place.
Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.
Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add #define values for the HPET device. In Stoney Ridge, the base
address is fixed and cannot be relocated.
Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses common SCS library to set up sd card.
Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change increases the spd read performance by using smbus word
access.
BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm
Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it is fairly uncommon, add a weak call that may be done by
the platform if it has the support.
BUG=b:66690176
BRANCH=none
TEST=coreboot builds.
Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using common p2sb driver instead of private one.
TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.
Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add common p2sb driver support.
TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.
Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake
in the AGESA spec and the function is in the wrong section.
bug=b:66690176, b:67210418
branch=none
test=none
Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch adds the C state and P state configurations for
cannonlake soc.
TEST = Boot and test the CPU states for all the cores are
present in "powertop" tool output.
Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Common PMC code comes with its own.
Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
intel/common's pmclib already keeps track of the power state (since
commit f073872e22 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.
BUG=b:67976359
BRANCH=none
TEST=builds
Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.
This change fixes the above issue by reducing the size of unused
array.
BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.
Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allows explicit ordering for vendors that share a common configuration
that must be sourced last.
The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.
Note: intel and amd soc chips now need to be added manually to the new
Kconfig file
BUG=b:62235314
TEST=make lint-stable
Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092
Increase the stack size from 4kiB to 8kiB to prevent stack overrun.
TEST=No stack overrun is observed and it boots to OS properly.
Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Librem13v2 needs to set this parameter to work around
power-related issues with some SATA devices.
Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22045
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ME status is the interpretation of the status registers, but
having the actual status registers printed is important and it doesn't
hurt to show them.
Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and
rely on the cbfs search 100% of the time. The change was initially
put in to avoid a hang when vboot presearched memory for the blob.
The implementation now supports early cbmem init and cbmem_top() is
careful to return 0 if DRAM has not yet been set up. As a result the
hang no longer occurs and the hack may be removed safely.
BUG=b:67747902
Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add functions for configuring the GPE ACPI SCI events.
BUG=b:63268311
BRANCH=none
TEST=With the Kahlee GPE setup patch, test lidswitch powers
the device on and off at the login screen.
Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets
the GPEs.
In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.
Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Include common platform.asl to have generic indication of power
transition state of system.
TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.
Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
- Call sgx_fill_gnvs to update GNVS data, if
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.
- With this patch SGX ACPI device would get pached with enumaretd values
of ECP device status, base address and length
Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
driver would let loaded
Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't
set it to VOID. 0 works for either UINT32 or VOID *, as demonstrated
by the other 7 places in this file where it's already set to 0 instead
of NULL.
Change this location to 0 to support either version of the headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* Change all calls to PCI_DEVFN to macros
* Remove CBB and CDB Kconfig since these are static for stoneyridge
BUG=b:62200746
TEST=build
Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Replace southbridge registers and register values from magic numbers to
literals, provided these registers are currently defined publicly or in
NDA datasheet.
Registers available only internally to AMD are left unchanged.
BUG=b:62199625
Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.
TEST= Force global reset from FSP and read back HECI bar in debug print.
Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().
This patch avoids one extra calculate_dram_base() call.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.
Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
