The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here.
Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten.
The fix included crota and omnigul BT offload work successfully.
BUG=b:264834572
TEST=test Bluetooth offload playback/capture in SCO profile.
Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not
get called when postcar was loaded from TSEG stage cache on
ACPI S3 resume path. Resume failed as MP init attempts to
access microcode update from unverified FW_MAIN_A/B section.
In a similar fashion, for POSTCAR=n, loading ramstage from
TSEG stage cache would bypass the call to vboot_run_logic().
TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able
to complete S3 resume.
Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add fw_config and configurate AUX pin for MB USB Type-C.
MB USB3 doesn't have re-timer, thus have to configurate the AUX pin.
BUG=b:275335023
TEST=build pass
Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
EDK2 seems to have problems at least with the resource allocation for
Intel's IGD. While the investigation is ongoing, disable top-down
allocation by default if the payload is known to be EDK2.
Change-Id: I771d8a3b74b54a043624843a00498225d1f509ad
Signed-off-by: Nico Huber <nico.h@gmx.de>
Ticket: https://ticket.coreboot.org/issues/499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76373
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
This patch fixes the boot hang due to commit 053a45bcdb ("cpu/x86/lapic: Fix X2APIC_ONLY regression") on platform which selects X2APIC_LATE_WORKAROUND config.
[EMERG] Switching from X2APIC to XAPIC mode is not implemented.
Without this patch: Boot gets stuck inside at BS_WRITE_TABLES when enable_lapic() gets called after X2APIC mode has been enabled. The fix is to change enable_lapic() to track when late enablement for X2APIC mode happens with X2APIC_LATE_WORKAROUND.
TEST=Able to build and boot google/rex to chromeos.
Change-Id: I41e72380e9cfb59721d0df607ad875d7b6546974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76384
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current design of the `ucode-<variant>.bin` file combines all
possible microcode per cpuid into a unified blob. This model increases
the microcode loading time from RW CBFS due to higher CBFS verification
time (the bigger the CBFS binary the longer the verification takes).
This patch creates a provision to pack individual microcodes (per CPUID)
into the CBFS (RO and RWs). Implementation logic introduces
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config which relies on converting
Intel CPU microcode INC file into the binary file as per format
specified as in `cpu_microcode_$(CPUID).bin`.
For example: Intel CPU microcode `m506e3.inc` to convert into
`cpu_microcode_506e3.bin` binary file for coreboot to integrate if
CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled.
Another config named CPU_INTEL_UCODE_SPLIT_BINARIES is used to specify
the directory name (including path) that holds the split microcode
binary files per CPUID for each coreboot variants.
For example: if google/kunimitsu had built with Intel SkyLake processor
with CPUID `506e3` and `506e4` then CPU_INTEL_UCODE_SPLIT_BINARIES
refers to the directory path that holds the split microcode binary
files aka cpu_microcode_506e3.bin and cpu_microcode_506e4.bin.
Refer to the file representation below:
|---3rdparty
| |--- blobs
| | |--- mainboard
| | | |--- google
| | | | |--- kunimitsu
| | | | | |--- microcode_inputs
| | | | | | |--- kunimitsu
| | | | | | | |--- cpu_microcode_506e3.bin
| | | | | | | |--- cpu_microcode_506e4.bin
Users of this config option requires to manually place the microcode
binary files per CPUIDs as per the given format
(`cpu_microcode_$(CPUID).bin`) in a directory. Finally specify the
microcode binary directory path using CPU_UCODE_SPLIT_BINARIES config.
Additionally, modified the `find_cbfs_microcode()` logic to search
microcode from CBFS by CPUID. This change will improve the microcode
verification time from the CBFS, and will make it easier to update
individual microcodes.
BUG=b:242473942
TEST=emerge-rex sys-firmware/mtl-ucode-firmware-private
coreboot-private-files-baseboard-rex coreboot
Able to optimize ~10ms of boot time while loading microcode using
below configuration.
CONFIG_CPU_MICROCODE_CBFS_SPLIT_BINS=y
CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/
$(CONFIG_MAINBOARD_DIR)/microcode_inputs"
Without this patch:
10:start of ramstage 1,005,139 (44)
971:loading FSP-S 1,026,619 (21,479)
> RO/RW-A/RW-B CBFS contains unified cpu_microcode_blob.bin
Name Offset Type Size Comp
...
cpu_microcode_blob.bin 0x1f740 microcode 273408 none
intel_fit 0x623c0 intel_fit 80 none
...
...
bootblock 0x3ee200 bootblock 32192 none
With this patch:
10:start of ramstage 997,495 (43)
971:loading FSP-S 1,010,148 (12,653)
> RO/RW-A/B CBFS that stores split microcode files per CPUID
FMAP REGION: FW_MAIN_A
Name Offset Type Size Comp
fallback/romstage 0x0 stage 127632 none
cpu_microcode_a06a1.bin 0x1f340 microcode 137216 none
cpu_microcode_a06a2.bin 0x40bc0 microcode 136192 none
...
...
ecrw 0x181280 raw 327680 none
fallback/payload 0x1d1300 simple elf 127443 none
At reset, able to load the correct microcode using FIT table (RO CBFS)
[NOTE ] coreboot-coreboot-unknown.9999.3ad3153 Sat May 20 12:29:19
UTC 2023 x86_32 bootblock starting (log level: 8)...
[DEBUG] CPU: Genuine Intel(R) 0000
[DEBUG] CPU: ID a06a1, MeteorLake A0, ucode: 00000016
Able to find `cpu_microcode_a06a1.bin` on google/rex with ES1 CPU
stepping (w/ CPUID 0xA06A1) (from RW CBFS)
localhost ~ # cbmem -c -1 | grep microcode
[DEBUG] microcode: sig=0xa06a1 pf=0x80 revision=0x16
[INFO ] CBFS: Found 'cpu_microcode_a06a1.bin' @0x407c0 size 0x21800 in
mcache @0x75c0d0e0
[INFO ] microcode: Update skipped, already up-to-date
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch changes the default behaviour of the MICROCODE_UPDATE_PRE_RAM
config for the platform with FIT (CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
enabled. If FIT is enabled then microcode update will be taken care of
by FIT at pre-cpu reset hence, microcode update at pre-ram phase can be
skipped.
BUG=b:242473942
TEST=Able to build and boot google/rex with MICROCODE_UPDATE_PRE_RAM
remains disabled. No functional impact.
Without this patch:
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
With this patch:
CONFIG_MICROCODE_UPDATE_PRE_RAM is not set
Change-Id: I603e064115869aba2bffa5589ffe47a44a90b848
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit cde4f3b279 ("acpi/gnvs.c: Drop unused pointer to the cbmem
console") removed writing the coreboot memory console pointer to the
GNVS and kept the CBMC field as reserved. Since those fields aren't
needed any more and there are no dependencies on the absolute position
of the different fields in GNVS as long as both GNVS definitions on the
C and the ASL side match, remove the deprecated and unused CBMC field
from the GNVS structs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iadfaf5a4ec1401b027dbfb6a7c6ce74a1dcecdfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76351
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The function ux_locales_get_text() should expect to have a correct
preram_locales region to read, hence we need to adjust the log levels
inside lib/ux_locales.c:ux_locales_get_text():
* If the region does not exist or is not in a correct format, we should
print in BIOS_ERR
* If the arguments are not correct but we have a good workaround (e.g.
the lang_id from vboot API seems weird), we should print in
BIOS_WARNING.
Also change some minor syntax issues.
BUG=b:264666392, b:289995591
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ic8a8856c883f6ca78fed69542a7d388f57c5c508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76316
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Fix below build error after DISPLAY_UPD_DATA is selected:
src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable]
131 | const FSP_S_CONFIG *old;
| ^~~
src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable]
130 | const FSP_S_CONFIG *new;
Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove BUILD_TIME_STAMP_SIZE macro from coreboot because FSP 3223
version have BUILD_TIME_STAMP_SIZE macro defined as part of
`FspProducerDataHeader.h`.
Ref change:
9c28ab1d1a vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80
BUG=b:285110116
TEST=Able to build google/rex.
Change-Id: I52707adf1aa6dadca8dcf82102f76916a0cfe346
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Use the _tohex function to convert values to hex instead of 'shell
printf'
TEST=timeless builds identical for grunt,dalboz,guybrush,chausie,birman
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic7f7d1b764479088cc0980b208d8d603bc712832
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76314
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into
an APCB for phoenix platform.
The tool makes several assumptions:
* Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero.
* Each block is 64 bytes.
* Dimm and socket are always 0
* Unused SPD entries are zero'd
BUG=b:281983434
BRANCH=None
TEST=build, flash, boot myst
Change-Id: Ifb50287de77138170714a702ab87d56427aacfef
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
tis_plat_irq_status() function is used only by Google TPM. It should
be moved to drivers/tpm/cr50.c. The name of the function was changed
to cr50_plat_irq_status().
BUG=b:277787305
TEST=Build all affected platforms
Change-Id: I78dc39f2c7b44232b06947d3dfe6afa52807ced8
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75917
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Fix regression introduced with commit 01af0f8ac8 ("acpi/acpi.c: Reduce boilerplate").
DSDT table is not to be listed within RSDT/XSDT, ACPICA and/or OSPM may
try load it twice raising conflicts in the namespace and effectively ignoring all or most of the AML.
Change-Id: I0e6d07b35522f2bf9a51cef0a7e3181b15087d88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Always exit 4-byte addressing mode to prevent errors when the spi flash
is not left in 4-byte addressing mode.
TEST=boot with PSP releases that leave the flash in both 4-byte
and 3-byte mode and verify flash writes
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9884b85bc3b0a9b654a2cb91fb314b0869abd622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76094
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO GPP_B5 is used as input on this mainboard. For a full-populated
DRAM configuration, the input signal is connected to ground and for a
half-populated configuration it is connected to 3.3 V.
BUG=none
TEST=Use different HW configurations and check coreboot log
GPP_B5 = 0:
[DEBUG] 2 DIMMs found
GPP_B5 = 1:
[INFO ] meminit_channels: DRAM half-populated
[DEBUG] 1 DIMMs found
Change-Id: I48b4a3bea7f1ff804b78b7c648a7ea1925627b8a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76245
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There can be mainboard variants, which are only equipped with
half-populated DRAM. For this reason, the meminit parameter for
populatation should be adjustable. The default setting remains at
full-populated DRAM. At mainboard variant level a different selection
via individual input paths can be made.
Change-Id: I390bbfa680b5505bb2230fa0740720bd9dd1fafb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76244
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align implementation with real hardwares, such that ECAM
(PCI configuration via MMIO) is available for use when
console is initialised.
Change-Id: I288991f31d3f1678132aa4315168c09eabbbe98d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76206
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
At the time of writing SMM runtime does not make register
accesses to LAPIC registers, but such breakage has been
reported.
S3 resume failure, where OS switched back from X2APIC
to XAPIC mode, can be reproduced with a sandybridge SKU
that has VT-d disabled.
Change-Id: I300ba87c3d8fde548dbaf95703bd7e2fe54cff57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Some ancient CPUs may have had LAPIC disabled at power-up, so
semantically enable_lapic() should always come before attempting
to access the register banks.
With X2APIC_ONLY option it is necessary to ensure enable_lapic()
is called prior to any other lapic register space accesses,
since the XAPIC mode MMIO accessors are optimised away build-time
and CPU's do not yet initialise for X2APIC mode at reset.
Change-Id: I96eaa5c43108c802375e184e0c68b5091ca0198f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76195
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This devices is always present so hooking up the ops in devicetree makes
more sense.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I369129e365ce8596cad25b97d12168bb08e3ed0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76241
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
None of these boards have an RTC battery, so this option has no
effect. Remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9a55227f74c0b9ae9b56bdef4b8f53b2425b331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It is not needed, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I606d0a76926e90e4ce321163400aa50ea961c2a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75342
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL (Samsung)
2. K4UBE3D4AB-MGCL (Samsung)
BUG=b:289873670
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7a262ac62c24cfb43c0283c9730c177a242342e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76240
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rather than repeat the same line multiple times, save it in a variable
once and use that variable in the rest of the file.
TEST=timeless birman build identical
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I4eb262adb3bbda04add79b2e2b8bee9a609a1e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76197
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Pass the APOB NV address as a flash offset instead of x86 address.
TEST=boot birman and verify APOB_NV is working
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76162
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Attempting to use X2APIC MSRs before the call to enable_lapic()
is made raises exception and double-faults.
Change-Id: Ib97889466af0fbe639bec2be730784acc015b525
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Updating some submodule pointers to their latest commit causes some
builds with default configuration to fail since all required components
don't fit into 2MB anymore. Specifically, this has been experienced with
the microcode and FSP submodules.
So, increase the default CBFS size to 4MB to make sure builds succeed
with updated submodules.
Change-Id: I2fc16240bef36c057608acadf3cb7c65e7f0d244
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
VP2420 (vault_ehl) has only 1 DIMM slot present. Set the DIMM_MAX to 1
to optimize the common libraries to not attempt to read and parse more
SPD than needed.
TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory properly and fastboot is working.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I29a99f387ffe2df1060547e0818c5c5b66a27061
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73819
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature for ovis.
BUG=b:270664854
TEST=Build and boot google/ovis.
Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch adds a power limit for Ovis with 28W Intel Meteor Lake
silicon.
Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982
BUG=b:289854108
TEST=Able to boot google/ovis with power limit being overridden as
appropriate to 28W.
Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Currently, boards with ES2 silicon are unable to boot with crashlog
enabled because crashlog driver is unable to handle invalid data.
Temporarily disable the crashlog to unblock development until the issue
is fixed.
BUG=b:289749310
TEST=Able to boot to the OS on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Use IOMMU_CAP_BASE_[LO,HI] instead of magic values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7032d9f032a22649951ef1535f39b918eb8bd539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie155cab1f659e9f7b64cd87ba8a77260056656d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76222
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBMEM can contain log in different forms (at most one is present):
- coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
LB_TAG_TPM_CB_LOG)
- TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
- TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
The last two follow specifications by Trusted Computing Group, but until
now cbmem couldn't print them. These formats were added not so long ago
in:
- commit 4191dbf0c9 ("security/tpm: add TPM log format as per 1.2
spec")
- commit 53db677586 ("security/tpm: add TPM log format as per 2.0
spec")
These changes make cbmem utility check for existence of TPM1.2/TPM2 logs
in CBMEM and add code necessary for parsing and printing of their
entries.
TEST=`cbmem -L` for CONFIG_TPM1=y case
TCPA log:
Specification: 1.21
Platform class: PC Client
TCPA log entry 1:
PCR: 2
Event type: Action
Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
Event data: FMAP: FMAP
TEST=`cbmem -L` for CONFIG_TPM2=y case
TPM2 log:
Specification: 2.00
Platform class: PC Client
TPM2 log entry 1:
PCR: 2
Event type: Action
Digests:
SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
Event data: FMAP: FMAP
Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c
Ticket: https://ticket.coreboot.org/issues/425
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables BT offload feature for soundwire audio over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=build and verify BT offload on rex soundwire audio
Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3
Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Follow the Project_Uldren_Thermal_paramters_list_2023_0626.xlsx to
modify DPTF parameters and tcc_offset.
- Set tcc_offset to 3.
- Update Critical Policy trip point.
- Update Power Limits PL1 minimum step size to control limits (in mW).
BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and pass thermal test.
Change-Id: Ic5bbb3aa3b036a1eae8a95f63b570db2dc6da978
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76105
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
In next phase, joxer will remove external fivr.
BUG=b:285477026
TEST=emerge-nissa coreboot and boot to OS, suspend/resume
work normally.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I7fd7ad90e1544966170df402243604379f5790db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This reduces boilerplate. One functional difference is that SSDT no
longer has oem_revision set to 42.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Adding tables to R/XSDT, aligning current pointer, computing checksum is
a lot of boilerplate that needs to be done for each table.
TESTED on foxconn/g41.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Phoenix is an x86 soc that supports sha256 instructions.
TEST=boot birman to chromeos
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id228399ba02708b97110d524ce12c2626588762d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76166
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Always send the Exit 4-Byte Address Mode (E9h) command before the first
access to the SPI flash in all stages when the SPI flash is
memory-mapped. This is useful for x86 mainboards that do not access SPI
flash in bootblock yet still need to exit 4-byte addressing mode in
romstage or ramstage.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace `CBFS_SIZE` with FMD files to declare regions and sizes. This
will be used to lock BIOS region (except SMMSTORE) on boot.
`CBFS_SIZE` was incorrectly set to 10 MiB, so this also corrects the
BIOS region size to match the FIT values.
Change-Id: I0f068f4d9b376f12b46faa5bb0c6a08e6cb744d8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76155
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Fixes building when `USE_OPTION_TABLE` is selected.
Change-Id: I4fb017aa549b24eda6b9e0356bc1776d4044c95d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Multiple users have requested to have the DMI values for product UUID
and serial number be populated. Enable the drivers so that we may set
them when flashing or updating firmware.
Change-Id: I710363d9df626d51756a265f0099f26ef28411c2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
The Infineon chip occasionally fails Startup or Resume. Adding the
delay makes it work more reliably.
Change-Id: I4a8f98633154888e2167a3d55192b86e13ffcb62
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76095
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System76 EC since system76/ec@99dfbeaec3 sets PL4 values through PECI
based on AC state for all boards. Remove the static PL4 values from
coreboot since they won't be used.
Ref: https://github.com/system76/ec/pull/353
Change-Id: I66bc547ef1b3419fc677fcbdd5ba5d8cc8e14189
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75333
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Resetting the device will cause the keyboard backlight and airplane LED
to lose their state.
Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the EC to detect C10 using eSPI instead of a dedicated pin.
Change-Id: I58c03d91466b869d53c9ee2cbbe50adc32539494
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable D3cold to prevent issues with Thunderbolt not working after S3
suspend.
Change-Id: Ib4362783546aa01f0f8f5baaad817ee76be9c39c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Move this function to the root Makefile.inc since other Makefiles use
the exact same function call. Will allow for deduplication in AMD SoC
Makefiles in a follow-on commit.
Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76167
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update SX9324 register settings based on tuning value from SEMTECH.
BUG=b:279510275
TEST=Check i2c register settings on Pujjoteen5 and confirm P sensor function can work.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idc9a2dc817e027551e209c0a26eeebad398f710c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75900
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been decided not to use any of the USB 3.0 ports on this board.
This patch disables the remaining USB 3.0 port 0, after the port 1
has already been disabled in commit d0627c7595
("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1").
BUG=none
TEST=None of the USB 3.0 ports functional anymore after boot,
the USB 2.0 ports continue working.
Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75836
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the previous instruction the complete register was set to '0'.
Correctly, only the bits 23:16 must be masked.
Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76177
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.
Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The offset '0xa8c' for the High Speed I/O Transmit Control Register 3
refers to SATA port 1 only. To make this clear, change the name of the
define from 'TX_DWORD3' to 'TX_DWORD3_P1'.
Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76174
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.
Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Set the WIFI_SAR_ID field in FW_CONFIG to selcet the correct SAR table.
BUG=b:285477026
TEST=emerge-nissa coreboot and check the SAR value
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibea62c77ecad9b2c475452b706779e4cfc6b06d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76144
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:283245785
BRANCH=firmware-grunt-11031.B
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the kb8010 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The kb8010 retimer does not support this
feature, so let the SoC do the flip.
BUG=b:267589112
TEST=verified DP-ALT mode works in both cable orientations on rex with
reworked kb8010 DB by flykt@
Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Secure OS was disabled on Grunt devices since it isn't used.
This reduces the attack surface and is meant to mitigate potential
security risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.
BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881
Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
New port based on autoport.
Autoport worked with minor tweaks, but fan speeds went almost
immediately to the maximum. They are controlled by the NPCD379
Super I/O which isn't supported by coreboot.
But coreboot already has code for NPCD378,
which HP Compaq 8200 SFF makes use of.
So SuperIO configuration was copied from the 8200 SFF port.
It seems to work without any issues in "normal" use.
Most importantly, fan speed control seems to work correctly.
However this means that some of the SuperIO LDNs may be configured
incorrectly. See the comments on Gerrit for more information.
The following is tested and is working:
* Native raminit with both DIMMs
* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
* External USB2 and USB3 ports: they all work
* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
* Ethernet
* Mini-PCIe WLAN
* SATA: 2.5" SSD and optical drive bay
* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
* GRUB (with Libreboot config)
* PS/2 keyboard and mouse
* S3 suspend and resume, wake using USB keyboard
* Headphone output, line out, internal speaker
* Wake on LAN
* Rebooting
* CMOS options & nvramcui
Untested:
* mSATA slot. The SATA port needs to be enabled on devicetree
too, but I'm unable to test due to lack of hardware
* Line in, mic input
* MXM graphics card
* EHCI debug
Not working:
* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
maybe it just isn't present
* PS/2 keyboard wake from S3
Change-Id: I2dc31778c2aa1987d5acdf355973a203dd0bb3a3
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74906
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- remove usb2_ports[5] since taranza doesn't have PL2303.
- add usb2_ports[6] and usb3_ports[1] for Type-A Port A4.
BUG=b:288094807, b:278167978
TEST=emerge-dedede coreboot chromeos-bootimage
verified all the USB port works
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7b411c21271497ba386143140aa8cfbb17a1a111
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76186
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch performs below operations to enable LAN0.
- Complete the LAN PEREST power sequencing
- Program the SRC_CLKREQ (GPP_D20) with correctly.
- Add overridetree.cb entry to configure the LAN0 device.
BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.
Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch performs below operations to enable LAN1.
- Add overridetree.cb entry to configure the LAN device.
- Complete the LAN1/SD PEREST power sequencing
BUG=b:289395519
TEST=Able to boot google/ovis with LAN1 being enabled.
Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the
Ovis schematics dated June'23 to ensure LAN port is not in sleep.
BUG=b:289395519
TEST=Able to measure SLP_LAN PIN and confirm it's deasserted.
Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis
schematics dated June'23 to ensure LAN ports having power.
BUG=b:289395519
TEST=Able to measure LAN port power is enabled with this CL.
Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The taranza removed the APW8738BQBI and "disable_external_bypass_vr" should be set to "1" to disable.
BUG=b:288978340
TEST=emerge-dedede coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I0a849fbfacba1d200c969c66bb058863d7ab3085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch updates the mux connection to reflect the Ovis schematics
dated June to ensure Type-C1 is able to work in DP-ALT mode.
BUG=b:289300284
TEST=Able to get display over Type-C1 port.
Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This was missed recently when adding the table. Linux complains about
the missing checksum, e.g.
[ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173)
Tested with QEMU/Q35, albeit with changes to the special handling for
ACPI with QEMU. The warning goes away.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 90464073e4 (acpi: Add SPCR table)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dimm_num shall be dimm, not channel.
BUG=b:288520486
TEST=In kernel, see output from `dmidecode -t 17`.
Observe that Locator reflects proper location of the module.
Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
So, this patch removes unused code related to
MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE
ADL also removes this code, see cl:62861
BUG=b:288976547
TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume
Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds CPU ID for C0 stepping (aka QS).
DOC=#723567
TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log.
Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83
Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ramstage.c in Makefile.inc and update Dibbi power limits in
Dibbi ramstage.c.
BUG=b:281479111
TEST=emerge-dedede coreboot and check psys and PLx value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75681
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With newer dedede design, it's required to config corresponding
psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of
adapter.
BUG=b:281479111
TEST=emerge-dedede coreboot and check correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I583c930379233322c41027805369f81d02000ee7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
ALL_MONITOR_OFF command is sent using DPOF.
TBT controller needs to be notified about ALL_MONITOR_OFF(TBT Displays OFF) only when Firmware Connection Manager(FWCM) is in use during S0ix Entry/Exit. When configured for SWCM this command should not be sent.
BUG=b:288536417
TEST= Build and boot Rex Proto-1. Verify S0ix working.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75717
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Utkarsh H Patel <utkarsh.h.patel@intel.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Update system_configuration to 3 for 15W. Specification "FT6
Infrastructure Roadmap #57316" incorrectly lists system config index of
4 for 15W. Setting to 4 will cause an additional call to the SMU that is
not needed and will add boot delay. Both SMU and FSP interpret configs >
3 as 3.
BUG=b:267294958
TEST=Confirm extra message "Service Request 0x5F" not in log.
Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Update system_configuration to 3 for 15W. Specification "FT6
Infrastructure Roadmap #57316" incorrectly lists system config index
of 4 for 15W. Setting to 4 will cause an additional call to the SMU
that is not needed and will add boot delay. Both SMU and FSP interpret
configs > 3 as 3.
BUG=b:267294958
TEST=Confirm extra message "Service Request 0x5F" not in log.
Change-Id: I1f3e305c48801b4e499de56d06c0dcd3eeacc626
Signed-off-by: Jason Glenesk <jason.glenesk@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76091
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
The SOC/IOE SRAM device is used to store crash logs. Previously, the
crashlog enablement was hardcoded in the baseboard.common module.
This commit moves the crashlog enablement logic to the baseboard
module, so that it can be enabled or disabled based on the specific
baseboard.
Additionally, the SOC/IOE SRAM is now enabled by default in the
baseboard devicetree.cb file. This prevents the system from hanging
if the SOC/IOE SRAM device is not present.
BUG=b:262501347
TEST=Able to build and boot google/screebo with this patch.
w/o this patch:
[ERROR] SOC SRAM device not found!
[ERROR] IOE SRAM base not valid
Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch enables SaGv with fixed frequency and gears for Ovis.
Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/ovis using debug FSP logs
Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some payloads tend to need bigger space than what our current defaults
allow. Linuxboot is a good example.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I7029ca3360d936b67ff9873fa13cf9cc60445e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Set tcc_offset value to 20 in devicetree for Thermal Control
Circuit (TCC) activation feature for rex variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: I0567b6240fcb53f38158c381b700169475cf3795
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Hades uses GL9755 not GL9750. Select the right driver for ASPM.
BUG=b:283721798
TEST=check the coreboot log.
GL9755: configure ASPM and LTR
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia5b3b17d76f02d5114af24535f9a1eecc14358a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76118
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When probing the resource with the IOMMU_IOAPIC_IDX index, we need to
use the PCI device 0 function 0 on the first bus in the domain for
probing and not the domain device, since the resource isn't on the
domain device, but on the northbridge device which is B0F0D0 in the case
of the APUs.
TEST=This fixes the following error on Mandolin with Picasso:
AMD-Vi: [Firmware Bug]: : IOAPIC[1] not in IVRS table
AMD-Vi: Disabling interrupt remapping
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76117
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
TESTED works on IO and MMIO console with linux using 'earlycon=' in the
commandline argument.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75685
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bytedance bd_egs is a dual socket MB with Intel Sapphire Rapids
Scalable Processor chipset.
It's utilising:
- 2 SPR sockets
- Max 32 DIMMs
- 33x CPU PCIe slots
- AST2600 for VGA and BMC remote management
Test:
The board boots to Linux 5.10 with all 192 cores available.
All PCIe devices and DIMMS are working.
# sudo dmesg --level alert,crit,err,warn
[ 46.636896] netlink: 'consul': attribute type 1 has an invalid length.
Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d
Co-authored-by: Jinfeng Li <lijinfeng01@ieisystem.com>
Co-authored-by: Long Cao <caolong01@inspur.com>
Co-authored-by: Hao Wang <wanghao11@inspur.com>
Co-authored-by: Chenyu Lan <lanchenyu@inspur.com>
Co-authored-by: Lay Kong <lay.kong@intel.com>
Co-authored-by: Kehong Chen <kehong.chen@intel.com>
Co-authored-by: Ziang Wang <ziang.wang@intel.com>
Co-authored-by: Dong Wei <weidong.wd@bytedance.com>
Co-authored-by: Chenchen Li <lichenchen.carl@bytedance.com>
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Reviewed-by: Haitao Nie <niehaitao@bytedance.com>
Reviewed-by: Shijian Ge <geshijian@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Hades uses DDR5 which can't read SPD from coreboot yet. Use smbios
dump to print memory information.
TEST=check the coreboot log.
memory Channel-0-DIMM-0 type is DDR5
memory part number is MTC8C1084S1SC56BG1
memory max speed is 5600 MT/s
memory speed is 5200 MT/s
memory size is 16384 MiB
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ica44081228a3a1edc36e2110e84686582fbe8f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Option name strings should not end with a period, remove it.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Id61d8961cad2cd311db7d9da3bdb86f0f28b57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Don't rely on vendorcode to set enable bit on IOMMU.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I1805a20656b7fb3915f8cc93c618ee074461840f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Print crashlog size information in hex to be consistent with
other prints.
BUG=b:262501347
TEST=Values printed in hex.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Ieb5498e702497bfbc2b4d5396d5b760a0010f5de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75910
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have found inconsistencies in turn of FW_CONFIG settings/definitions,
so sync setting to vell config.star
BUG=b:282189358
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I676b719ecc711a6f59e76465a3566bf63924d90f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75913
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While we are at it:
- Don't use _kb version of declaring resources
- Use cbmem_top instead of probing for memory again
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iaaee41aec7806287ef1881372ec8ec47a4cd57d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The sign of 'char' is not standardized and with GCC is architecture
dependent.
This fixes warnings when compiling this file on arm64.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I53b99835b2ffec5d752fc531fd59e4715f61aced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zero-initialize the ivhd_range and ivhd_entry structs to make sure that
the whole struct is in a defined state.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iccacc89bfc497449ad0716a3436949505b65f748
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76079
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To determine the length parameter of memset, use sizeof with the
instance as argument instead of the type. The behavior is the same, but
it clarifies parameters in the memset call a bit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63674fbed7097a583cd77fa6e700652d6dcc5565
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Assign the current address casted to acpi_ivrs_ivhd[11,40]_t pointer to
*ivhd_[11,40] at the beginning of acpi_fill_ivrs[11,40] and then use
memset on *ivhd_[11,40] to zero-initialize the structs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I70b12fee99d6c71318189ac35e615589a4c8c629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76077
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BIOS Vendor in SMBIOS Type 0 would be who built the firmware so create a
config string with default "coreboot" to make it changeable. Vendors
could update it by adding a Kconfig in the site-local directory.
Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24
Signed-off-by: Yiwei Tang <tangyiwei.2022@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
No matter what DRAM calibration is performed, DRAM scramble should be
enabled as long as MEDIATEK_DRAM_SCRAMBLE is set to y. Currently, DRAM
scramble is enabled only if full calibration is performed. Correct the
behavior by adding DRAMC_CONFIG_SCRAMBLE to the header config in fast
calibration flow.
BUG=b:285474337
TEST=Check the scramble feature is disabled on serial build
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I907bccd4e68e040179e1971db6bf7a57b88dec1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75818
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Description of POST_EXIT_PCI_SCAN_BUS indicates the opposite of what
its name suggests. Secondly, POST_ENTER_PCI_SCAN_BUS and
POST_EXIT_PCI_SCAN_BUS have identical comments, which appears to be
a copy-paste issue.
Change the description accordingly.
Change-Id: Ifc920651255bacf033cac39f0208d817f9ee84fc
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76047
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zero-initialize the ivhd_hpet struct right at the beginning of the
ivhd_describe_hpet function to make sure that the whole struct is in a
defined state.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If4d3563c485eed4a7cb0526a62f7b6c80f763bfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76074
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Allow the caller to specify the HID that gets written to the
ivrs_ivhd_f0_entry_t struct.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I830f1fbbd535b100c88997ece10142a5d553950f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76073
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Zero-initialize the ivhd_f0 struct right at the beginning of the
ivhd_describe_f0_device function to make sure that the whole struct is
in a defined state.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6750b58dacb9b9192ed21128eb6e3a4495b96d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
The eMMC entry in the IVRS table should only be generated if an eMMC
controller is present in the SoC.
Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There
is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO
device and not a PCI device, but this is what the reference code does.
My guess would be that it mainly needs to be a unique PCI device that
won't collide with any existing PCI device in the SoC. Add a comment
about this too.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Commit d054bbd4f1 ("Makefile.inc: fix multiple jobs build issue")
added a dependency on $(obj)/fmap_config.h to all .c source files in all
stages, so it's not needed any more to add it as a dependency to files
that include fmap_config.h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75679
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Super Ni <super.ni@intel.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
src/commonlib/include/commonlib/console/post_codes.h;
myArray=`grep -e "^#define POSTCODE_" \
src/commonlib/include/commonlib/console/post_codes.h | \
grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;
for str in ${myArray[@]}; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r POST_$splitstr src | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
grep -r "POST_$splitstr" util/cbfstool | \
cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
done
Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Rename shared SRAM aliases for IOE and PMC to make them more readable.
pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram.
pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram.
Rename them in SOC code as well as mainboard to make sure the patch
builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CNVi PCI device is required for the system to boot properly.
By ensuring that this device is enabled, we can prevent the below
error message from appearing and ensure that the system boots successfully.
BUG=b:274421383
TEST=Able to build and boot google/ovis without any error.
w/o this patch:
[ERROR] CNVi WiFi is enabled without CNVi being enabled
[ERROR] CNVi BT is enabled without CNVi being enabled
Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
This patch introduces a newer config to store the CSE RW FW version into
the CBMEM. Prior to that CSE RW FW version was fetched unconditionally
and ended up increasing the boot time by 7ms to 20ms depending on the
SoC arch (including CSE arch).
The way to retrieve the CSE firmware version is by sending the HECI
command to read the CSE Boot Partition (BP) info. The cost of sending
HECI command to read the CSE FW version is between 7ms-20ms (depending
on the SoC architecture) hence,ensure this feature is platform specific
and only enabled for the platformthat would like to store the CSE version into the CBMEM.
TEST=Build and boot google/rex to avoid getting CSE RW FW version
to save 18ms of the boot time.
w/o this patch:
10:start of ramstage 722,215 (43)
17:starting LZ4 decompress (ignore for x86) 741,415 (19,200)
w/ this patch:
10:start of ramstage 722,257 (43)
17:starting LZ4 decompress (ignore for x86) 723,777 (1,520)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I94f9f0f99706724c7d7e05668390f3deb603bd32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Add the HSPHY region required by INCLUDE_HSPHY_IN_FMAP option. It is
needed in case CSME/HECI is disabled or not visible to keep the
PCIe 5.0 root ports functional.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic4793fc9457f58e914ef3e18cce1294f230462bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68988
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.
TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When moving the code to allocate at the top level in commit 9260ea60bf
(allocator_v4: Use memranges only for toplevel), a call to restrict the
limit of the resource was dropped. Probably by accident in one of the
earliest rebases. Without this call to effective_limit(), 64-bit resour-
ces at the top level, i.e. PCI bus 0, were always placed above 4G. Even
when this was not requested with the IORESOURCE_ABOVE_4G flag.
Tested on kontron/ktqm77 where the issue could be reproduced with
x86_64. Without the fix, boot hangs when trying to access the GMA
MMIO registers of PCI 00:02.0, which were placed above 4G.
Change-Id: Ied3a0695ef5e91f092bf2d442c1c482057643483
Signed-off-by: Nico Huber <nico.h@gmx.de>
Found-by: 9elements QA
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76090
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces CBMEM ID to store the MRC version (similar to
existing implementation that stores the FSP-M version inside CBMEM ID)
inside cbmem so the version information is available across the
different coreboot stages. For example:
* romstage: Use the CBMEM ID version information to check if the MRC
cache is valid and need to erase the MRC cache
* ramstage: Use the CBMEM ID to store the MRC cache into the
non-volatile space.
BUG=b:261689642
TEST=Able to build and boot google/rex and dump the MRC version as
below.
cbmem --list
CBMEM table of contents:
NAME ID START LENGTH
...
21. MRC VERSION 5f43524d 75ffeb60 00000004
...
localhost ~ # cbmem -r 5f43524d | hexdump
00000000 01 12 07 00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I91f735239b33c6f8ba41c076048903e4b213c6a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75921
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses the "generic" variable name as "version" while storing
the MRC cache data instead referring to the FSP-M version or MRC
version. Hence, updated all the instances of `fsp_version/fspm_version`
with `version`.
Also introduces the new option to the MRC cache
version that allows SoC users to store the MRC cache version based on
the supported EDK2 version. Intel FSP built with EDK2 version 202302
onwards has support to retrieve the MRC version by directly parsing
the binary.
Additionally, added the helper function `fsp_mrc_version()` and
corresponding header file to read the MRC version from the FSP binary.
BUG=b:261689642
TEST=Able to build and boot google/rex and google/omnigul.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8af53aed674ad4a3b426264706264df91d9c6b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
SMBIOS is not specific to architecture, and this is mostly a generic
implementation. Therefore, move it to common code, having
architecture-specific code define some functions to fill this data.
Change-Id: I030c853f83f8427da4a4c661b82a6487938b24e6
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75886
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to clean up the post code macros, move them to a separate
header away from unrelated code. The new header file is included in
the file where the post codes are moved out of, so that the current
state remains unchanged.
Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Run with "-device pci-bridge,chassis_nr=1" argument to add a bridge and
see that it gets found and picked up by the resource allocator.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iad5d87731066a4009d2c4930a01bc15543d9447a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75925
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update_bridge_resource() already gets the type passed as part of
the resource.
Change-Id: I6b3c9809caecdd1bad5b98891a00c3392190a3e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Inline functions that are only called once to improve readability. The
calling functions still have rather short bodies, and the reader won't
have to look down yet another layer to understand what they are doing.
Change-Id: Ib4aa5d61dfa88c804a1aaee028185e00c5fbb923
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Won Chung