Crota360 is using a Cirrus CS42L42 for its audio codec; it requires the
reset pin to be deasserted in ramstage for proper power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ica3467fbc8639526bee071d56af854de5e07091e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With the PMC set to hidden, on certain Operating Systems,
including ZorinOS 16 and Manjaro 21.2.5, it would get stuck
at a black screen when exiting from S3.
With the PMC set to on, this issue no longer occurs.
Signed-off-by: Stephen Edworthy <stephen@starlabs.systems>
Change-Id: I0cf1be7f6919d974614f2196a0eb611cc40abe3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Commit 198cc26e49 (soc/amd/common/block/
psp/psp_gen2: use SMN access to PSP) changed how the PSP registers are
accessed. Since the new method doesn't need to rely on a MMIO base
address to be configured, the read will always be successful and so
soc_read_c2p38 doesn't need to return an error status and can directly
return the value instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1abace04668947ba3223a107461a27dddc0a9d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
A few ACPI device path name handlers are missing. Add handling
to ensure that these names are returned during acpi_device_path()
calls.
TEST=Built and tested on brya
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I37d6dd5df921c931af72dd469c3f4067c61b0df3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently coreboot will hang on ASPM on pcie_rp 6,
so disable ASPM to let it go into kernel.
BUG=b:231400217
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I79a80d97d168f40e58774e5652967d659daa323c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The eSPI decode range defines aren't and shouldn't be used directly from
outside of the common AMD eSPI code which provides functions to abstract
the register access, so move the defines from amdblocks/espi.h to
espi_def.h inside the common AMD LPC/eSPI support directory to limit the
visibility. The special I/O range decode bits need to stay in
amdblocks/espi.h since those are used in the devicetree. Also update the
indentation in espi_def.h so that the defines line up properly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4ea30a1a6f10e94d88bf3b29f86dee2da6b39b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64053
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those
registers are however not in one block where it's easy to calculate the
addresses of a register from the index of the decode range. Within one
group of decode range registers it's still easy to calculate the
register address, so move the base address from within the macro to the
instantiation of the macro as a preparation for adding the support for
the additional ranges.
TEST=Timeless build results in identical binary for Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id309d955fa3558d660db37a2075240f938361e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.
Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Looks like the `set_power_limits()` declaration is copy-pasta leftovers
from `cpu/intel/model_206ax`. As it's unused, get rid of it.
Change-Id: I81704e883e52fea42488f52be116b6fcc2c6af4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch removes unused i2c7 settings. Accroding to EVT schematic,
i2c7 is reserved for AMP but resistors are unstuffing.
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Ifc1e0085064a13149ebc7e70184d1f40462e0fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch calls into the PMC IPC function that informs about PMC
enumeration.
Note: Alder Lake FSP Notify Phase 1 callback missed to send this PMC
IPC, hence, this patch is considered as an improvement over FSP Notify
Phase API.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS without any PMC IPC
error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I43cfad25a5861c5aa5dae293ff42c9cefe862ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch sends an IPC to PMC to inform about PCI enumeration.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77d428f9501feaccab8bb431090d10ce8d3af9b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Crota360 is using a Cirrus CS42L42 for its audio codec; it
requires the reset pin to be deasserted in ramstage for proper
power sequencing.
BUG=b:230074351
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ie942b3c553823510dfa6f6fb70a7b13881fc4c14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
pmc_prev_sleep_state() isn't handling the case where acpi_sleep_from_pm1()
returns ACPI_S4. Pass that value along so it can get set as a
prev_sleep_state. Without this, consumers see prev_sleep_state as 0
and always treat resume as a cold boot. With this, consumers can
correctly do behavior specific to S4 resume, like skipping the
disconnect IPC command to the PMC on Alderlake systems.
BUG=b:230031158
TEST=Resume from S4 on Primus4es
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I3fb3dc428a749db80293e51a04a2096514a7b689
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Fix power sequence according to datasheet:GL9750S-OIY04 rev1.24.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: Iea729d43d10a3f8353b4fe540146d00975f4d422
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The per-file hash for CBFS_VERIFICATION, stored as a CBFS file
attribute, would increase the total RO metadata size by 75% (3796->6656
for corsola). Therefore, in order to make RO metadata cache fit into
CBFS_MCACHE, enlarge it from 8K to 16K.
Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K
(only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also
shuffle the regions in SRAM with better comments.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel
BRANCH=none
Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Since we can't rely on the MMIO base address in the PSP_ADDR_MSR MSR to
access the PSP mailbox registers, switch to using the SMN mapping of the
PSP mailbox registers. The PSP SMN base address is taken from the amdgpu
driver in the Linux kernel.
BUG=b:229779018
TEST=Mandolin still boots successfully and there are no errors/warnings
about possibly PSP-related things.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9d17e523e9ae8d8e14ecedc37131a81f82351487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64034
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Functions that are intended to override weak ones defined in the
baseboard should not also be declared weak, otherwise how would
the linker know which copy to keep.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia2ceee77d00a5baa915fd1f306d76e79aa609e65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on the schematic bernadino 14 adl-p 20220318.pdf to set
GPP_D16 to enable webcam power
BUG=b:230289857
BRANCH=none
TEST=build and notice log kernel v5.10
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I01c73006d24b00be348655334232bea5eeb312e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add entries to the devicetree override for brya0 and enable the Kconfig
to ensure the Chrome OS EC Mux driver is build tested.
BUG=b:208883648
TEST=None
BRANCH=None
Change-Id: Icf841cd32587f6bd98b15747283b0d331f013532
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some platforms have retimers which can be configured via the EC. Add a
handle to these retimer devices to the Type C connector device, using
devicetree references.
BUG=b:208883648
TEST=Verify disassembled SSDT on brya.
BRANCH=None
Signed-off-by: Prashant Malani <pmalani@chromium.org>
Change-Id: Ic0480b08c6d6a7562cca57192e49b8ea2a33b51e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use common ASL defines for POST code handling.
Change-Id: I5b4c11860a8c33e56edaea0f6de378cbaa63a8c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63989
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move ASL POST code declarations into a common file to avoid redundancy.
Also, provide a dummy implementation when `POST_IO` is not enabled, as
the value of `CONFIG_POST_IO_PORT` can't be used.
Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Align POST code ASL elements with existing code in newer southbridges.
The main differences are that `NoLock` is changed to `Lock`, and that
names have been changed. The lock type change should not be a problem
because the field is only used once in the _PTS method.
Change-Id: I8aa362007ff98e5b42add6c7908a8f7beac2222b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
To pave the way for future refactoring commits, drop POST code elements
from the debug.asl file. Only msi/ms7721 includes debug.asl and it does
not use any of it anyway.
Change-Id: Icd73e5c1f700fd7e735bed1668f02da8f9a3adf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CORE_2_PSP_MSG_38_OFFSET and CORE_2_PSP_MSG_38_FUSE_SPL are only used in
psp_gen2.c, so move them into this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67cc2ff63d1c0322b514521975f3ce0f9b1cf5b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
ADL-S CPU has maximum 3 PCIe interfaces when the x16 link is bifurcated
into two x8 links. ADL-S PCH has up to 28 PCIe Root Ports, 18 CLKOUT and
CLKREQ signals. ADL-S CPUs do not have Thunderbolt.
Based on the Intel DOC #619501 and #619362.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I408c815d5a43c081beb3f84d795c2b863ce33eb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add display on and off notifications which call mainboard hooks if
present. This allows to handle some board specific functions in user
absence or presence (when display goes off from inactivity or on from
activity).
TEST=Use Display on/off notification on Clevo NV41 to tell EC about
laptop inactivity. It is necessary to properly handle S0ix entry (stop
the fans and start blinking the power led).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Change-Id: Ie80f631ecffa74467ab6d6162e552ba977f7e3f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch just adds some comments to the recently merged mem_chip_info
struct for communicating memory type information to the payload/OS, to
clarify the expected format in which values are to be written into the
fields.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2c28b3bdcdb13b7f270fb87a8f06e2cf448cddec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Per Microsoft's spec for HID over I2C [1], interrupts must be level
triggered. Switch GPIOs and the devicetree config to conform to this.
Touchpad and multitouch gestures were already working, so no behavior
changes are observed in normal use.
[1]: http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
Change-Id: I485e616ae00e10bc3620ff3fa1fc1e903653c5cc
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It's useful to know how many attempts were made at polling the status
bit.
BUG=b:228289365
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc79a339707fbaab33e128807d4c0b26aa90108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The previous code required a bit too much effort to read. It also didn't
print out the actual duration.
BUG=b:228289365
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia620e789c5186f2e1d3cf3c548bda00a294d23bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
I find it difficult to constantly decode the registers when reading
them. Let's print out something that's easier to parse.
BUG=b:228289365
TEST=boot guybrush and see status codes printed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6c9d98cf43f340cf50e12c93b4c35187de9bb750
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Silently failing makes it hard to debug when something goes wrong.
BUG=b:228289365
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7423a7011e7656414155386c014a9a0f2fad4abf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the datasheet, we can safely increase the SPI frequency of
sc7280 to 50 MHz.
BUG=b:190231148
BRANCH=None
TEST=build and boot BIOS with this config on herobrine boards
Change-Id: I84420d7d8ab0cb979fc606fcf05147197bc51c35
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The MT8186 platform fails to suspend due to premature wakeup by USB.
In MT8186, we use low level latch to keep USB wakeup signal. However,
hardware could latch a wrong signal if it debounces more than one time.
As a result, it would enable wakeup function too early.
To prevent this issue, we do the following modification:
- Delay about 100 us to enable wakeup function in kernel drivers [1].
- To guarantee 100 us is enough, we need to disable the USB debounce by
default in coreboot.
According to section register 0x404 and 0x420 in
"(CODA) MT8169_PERICFG_REG.xls" which is only for MediaTek internal use:
The current default value of debounce register for MT8186 USB IP0 and
IP1 is incorrect. The reason we add in coreboot is that the default
value should be correct when SoC is booting up.
This modification is only for MT8186. The subsequent SoCs will adjust
the wakeup function to correct register value by default.
[1]: 0d8cfeeef3f5 (usb: xhci-mtk: fix random remote wakeup)
TEST=after stress test, not found premature wakeup by USB
BUG=b:228773975
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I296c4491c5959670a39fa8bd6ef987557bbc459f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63858
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop struct pspv2_mbox and access the PSP mailbox via their offsets into
PSP MMIO region.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib665d7ae19deae07d6a69c11ba8cf44e45ea4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63966
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't use unnamed redefinitions of the pspv2_mbox_command union when the
union definition can be used instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3757db45272f11bb47e5106ad9054c0a9ca0cd52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The pspv2_mbox struct contained an unnamed union that covered the 32
bits of the command register of the PSP v2 mailbox. Since the pspv2_mbox
struct is mainly used for hardware register accesses and the union part
is mostly used to access the different bits before/after writing/reading
the command register, split this functionality. For the register access
a command field is added to the pspv2_mbox struct instead of the unnamed
union and for accessing the separate bits of the command register a new
named union is added.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If3f00b6fd73c3f749154b77b940e6d5aa385ec49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The cmd_response field in the pspv2_mbox struct is the buffer used to
pass data to the PSP and back to the x86 side, so rename it to buffer.
This also aligns the code a bit more with the reference code. Also
rename the wr_mbox_cmd_resp function to wr_mbox_buffer_ptr.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22c8971b07b3dedcc2e6e50e93c98d69ec7379e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63962
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pspv[1,2]_mbox struct is only used in psp_gen[1,2].c, so move those
definitions from the common psp_def.h to the specific psp_gen[1,2].c
files. Also fix the struct name in the comment about pspv1_mbox.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0c95e9a6e292b90e0d147c57f59828a9b41e4b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63960
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size. intel/apl is an exception since the
bootblock size is limited to 32K.
Change-Id: I5e02961183b5bcc37365458a3b10342e5bc2b525
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch enforces disabling of the CSE device if CSE stays in
SOFT TEMP DISABLE state. The recommendation is to make CSE function
disable to avoid receiving any CSE commands from the OS layer.
BUG=b:228789015
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I77c254195895a93a5606adee8b6f43d8b7100848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch removes redundant DISABLE_HECI1_AT_PRE_BOOT config check for
heci1_disable(), once by caller (from various SoC) and again inside the
callee (heci1_disable) function.
As all callers of heci1_disable() function are doing
DISABLE_HECI1_AT_PRE_BOOT config enabled check, hence, the second check
inside the callee can be dropped.
BUG=b:228789015
TEST=Able to build and boot google/redrix with this change. CSE PCI
device is getting function disabled upon selecting
DISABLE_HECI1_AT_PRE_BOOT from SoC config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I47d7a9989e355987618d089f79c3340fcf4953ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:228789015
TEST=Able to build google/redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Agah USB-C port 0 is non-retimer port and it connects to TCSS port 2.
Bit[5:4] is for TCSS Port 2, so re-configure "TcssAuxOri" to 0x10 and "typec_aux_bias_pads" to 2 to correct the port.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I2d26777e850187aee0b676de13dff915474fed7b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This allows for the option to persist the serial number and other
device-specific information when switching from stock ChromeOS and
upstream coreboot firmware images.
Change-Id: I12711f678259390fe9e31b7ca728344cc2875b0e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The header file <inttypes.h> includes <stdint.h> and defines some
additional PRI* macros. Since elog.h and elog.c do not use any of the
PRI* macro, we should include <stdint.h> directly.
Change-Id: Iac1f4f53e43f171ecef95533cd6a3bf5dff64ec4
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The ITE EC used on Nereid can take a long time to update, and especially
too long to erase. There is a 1 second timeout enforced on the EC erase
command, but Nereid's IT81302 will typically take about 5 seconds to
complete erase, and could take as long as 30.
Since this affects any Nissa variant using an ITE EC and it's nice to
make the entire Nissa project consistent, this change disables early
sync for all Nissa boards.
BUG=b:222987250
TEST=EC software sync is no longer attempted (and thus does not fail) on
Nereid.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I55d36479e680c34a8bff65776e7e295e94291342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This patch enables TBT PCIe root port 3.
BUG=b:230464233
TEST=emerge-brya coreboot chromeos-bootimage and $lspci -t and
ensure 07.3 is in the list.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I118facd45f54c8ed2843a85c0aa61b6571077a5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Read the EEPROM to detect the DDI type.
BUG=b:225139014
TEST=Boot chausie and correctly detect display card type
Change-Id: I3ddd8789e75d5da2ea1e6ce9a81e5ebb2cf3c007
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Revert CdClock setting and use default value 0xff.
Previous problem was fixed by Jasperlake FSP in version 1.3.09.31,
so we can use the original CdClock setting in baseboard.
BUG=b:206557434
BRANCH=dedede
TEST="Built and verified on magolor platform to confirm FSP solution works"
Cq-Depend: chrome-internal:4662167
Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support for the chausie EC. Use EC to configure default board GPIO
settings.
Change-Id: I3e59e17644cddf1a508614f90c20561bde2691fb
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Chausie uses the spi1 pads for eSPI
Change-Id: Iee9b92dd9b4e84764568ec3cc8d1fce731e0d1a7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63866
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To read data from an I2C EEPROM that uses 2 byte offsets or any other
I2C device that uses 2 byte offsets, first the two offset bytes are sent
to the device and then the data bytes are read from it. The main
difference to the existing i2c_read_bytes is that that function will
only send one offset byte to the I2C device.
TEST=Reading the contents of an EEPROM on the AMD Chausie board works
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224e434bb2654aabef6302c1525112e44c4b21fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The lowest bound for L2 cache size on Socket P is 512 KiB.
This allows the use of cbfs mcache on all platforms.
This fixes building when some debug options are enabled.
Change-Id: I0d6f7f9151ecd4c9fbbba4ed033dfda8724b6772
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is plenty of cache available to increase DCACHE_RAM_SIZE to
allow the use of cbfs mcache.
Tested on Gigabyte GA-D510UD, still boots and resumes.
Change-Id: I1487ba9decd3aa22424a3ac111de7fbdb867d38d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 28e61f1634 "device: Use __pci_0_00_0_config in config_of_soc()"
significantly reduced the size of the bootblock. This makes the space
saving options, required to make to bootblock fit in the 32K SOC
limit, unnecessary.
TESTED: with configs/config.google_octopus_spi_flash_console the .text
size is 0x29c8 bytes which is still well below the 0x8000 SOC limit.
Change-Id: I208211d30cc2805113a16a02cdab957b8c584c92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
`sa_lockdown_cfg` function ensures locking the PAM register hence,
skip dedicated calling into `sa_lock_pam()` from the SoC
`finalize.c` file. Dropped sa_lock_pam() call from ADL/CNL/EHL/JSL
and TGL.
Additionally, this patch enforces SA lockdown configuration for SKL
and ICL as well.
BUG=b:211954778
TEST=Able to build google/brya with these changes.
> localhost ~ # lspci -xxx | less
00:00.0 Host bridge: Device 8086:4601 (rev 04)
Bit 0 for all PAM registers a.k.a, PAMx_0_0_0_PCI.LOCK bit is set
(meaning locked).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd464d2507393ed0c746eb1fbd10e36092ed5599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit 211be9c03 (soc/intel/cmn/{block, pch}: Migrate GPMR driver)
drops `dmi` prefix from `lockdown_cfg` function name.
This patch adds the `gpmr` prefix to the lockdown_cfg function to make
it meaningful.
BUG=b:211954778
TEST=Able to build google/brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idaa0e089131ab125348e2430355041c4ee7971de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig
to skip FSP notify API (Post PCI Enumeration) and make use of native
coreboot driver to perform SoC recommended operations prior booting to
payload/OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
[INFO ] coreboot skipped calling FSP notify phase: 00000020.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie28dde8f62adc5bafc4a42e608827f51da82570c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch performs locking of the PMC soft strap message interface.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified Bit 0 of PMC
MMIO register 0x104c is set as below.
> localhost ~ # iotools mmio_read32 0xfe00104c
0x00000001
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1ae972a203affa54c03de71f0f702356334cbf7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This area is used for storing AP RO verification data.
BUG=b:229670703
TEST=emerge-corsola coreboot
TEST=cbfstool /build/corsola/firmware/kingler/coreboot.rom layout
BRANCH=none
Change-Id: Id0a3304920c80987319d8072b8e443c41c1f1c47
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
MT62F1G32D4DR-031 WT:B
MT62F512M32D2DR-031 WT:B
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I183b74e66786c378cc227ee1e53ea422986b672a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The unit of dram speed is MT/s so append it on variable name.
BUG=b:229549930
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I83c780440613050c0202f95d5f64991b61d9c280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
- enable CPU PCIe VGPIO for PEG60
- enable GPP_C3/ GPP_C4 native function
- set unused GPIO to NC
BUG=b:229584785
BRANCH=none
TEST=build and boot into kernel v5.10
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I5d4ef92623ce6b0a36e6df23b232b35b498ce964
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When using LPDDR5 on a Type-C PCB, the Intel ADL-P PDG (Rev. 2.0.1)
page 121 recommends a maximum DRAM speed of 4800 MT/s.
BUG=b:229549930
BRANCH=none
TEST=build and pass memory training
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: I38f0006d478702afb382d30338f20b46641964ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
BUG=b:229547171
BRANCH=none
TEST=pass memory training with error
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If6acf8cb9474f816374743fd1e800da46958993d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
If set OEM string as "", it shows "Not Specified" with dmidecode.
Use default string if it is empty.
BUG=b:230039300
TEST=set OEM string "" and show google with dmidecode -t 2.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I097e1be696ae974aadc47feb8d0c1dae672a5c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Camera LED flicker 3 times or so as sensor is being probed
during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot preventing camera LED flicker.
Corrects that by explicitly sequencing the reset GPIO and power GPIO
BUG=b:219644184
TEST=Build and boot on vell, observe whether camera LED flickers
Change-Id: I846ec4cb5c4527f5664699b31d0d561d390d938c
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63441
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set native function (SD_AUX_RESET_L), and drive it high.
BUG=b:229181624
TEST=Build and boot to OS in Skyrim. Ensure that the SD Controller
and SD Card are enumerated fine.
02:00.0 SD Host controller: Genesys Logic, Inc GL9750 (rev 01)
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I03d88d90acc03cdebcb1e83ed2e799dda8b5b735
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There is a bug floating around where communciation with the PMC fails
after transitions through S3/S4/S5. This CL does not address that issue.
However in working with error cases presented by a failing PMC, we're
forced into an early return in read_pmc_lpm_requirements(), which sets
up _DSM buffers in the SSDT for the PEP device.
The function itself returns void, so the error is swallowed regardless.
However returning early is not the appropriate action because it causes
the size of the buffer written into the _DSM method to change. This causes
the SSDT to change size and layout across an S3 or S4 transition, which
results in mayhem in the kernel, as the kernel is not expecting these
tables to change out from under it.
Instead of returning early, it's better to simply print the error and
keep going, attaching a zeroed out buffer for the substate requirements.
This results in an empty requirements mask for all states. From what I
can see in the kernel this is no more broken than today's behavior, as
this buffer seems to only be used for printing a debugfs file.
In fact in this particular case the kernel doesn't even notice, as this
buffer is copied out at boot, and not refreshed at resume.
BUG=b:230031158
TEST=hibernate and resume on Primus4ES
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ibe35d50b350b1b96dea313dfcbd00745970c16ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
We need to include the SMM handler to enable SCI events when ACPI is
enabled.
With this enabled we now see we have EC timeout problems while in SMI:
[SPEW ] SMI# #1
[WARN ] SMIx88 => 0x800
[DEBUG] Chrome EC: Set SMI mask to 0x0000000000000000
[DEBUG] Chrome EC: UHEPI supported
[ERROR] Timeout waiting for EC QUERY_EVENT!
[DEBUG] Clearing pending EC events. Error code EC_RES_UNAVAILABLE(9) is expected.
[ERROR] EC returned error result code 1
[DEBUG] Chrome EC: Set SCI mask to 0x00000000186601fb
We still need to debug that. I suspect we have problems reading from
the ACPI IO decodes 0x62 or 0x66.
BUG=none
TEST=Verify SMI handler runs
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ida0fcd634e620274e124a8669836f3974e0a2bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
* Use GPE 24 since it doesn't conflict with any existing GEVENTS.
* Remove IRQ 12 mapping since it's not used.
* Unmask IRQ1 in PM registers.
* Use the new SMITYPE_ESPI_SCI_B SCI.
BUG=b:227282870
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e9816d67500365ed1d2ee39ef184a1f60321ca1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Sabrina added the ALERT_ENABLE bit. Set it to enable the eSPI_ALERT#
line.
BUG=b:227282870
TEST=Boot skyrim and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2a193ca454692bf13b707401079bd9edf026ef5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This bit is new on sabrina. We need to enable it after initialization
has completed.
BUG=b:227282870
TEST=Boot skyrim to OS and verify keyboard works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I795275993589e20c1d09674232ecff782c491335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
We don't currently have ALIB plumbed through. Disable the ALIB call to
remove ACPI errors during boot.
BUG=b:228496169
TEST=Boot skyrim and no longer see ALIB errors
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad45bcda326597ebfc8b9c403de5b4a934b0bbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63841
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
hardwaremain.c is the common ramstage entry to all platforms so move
out ACPI code generation (x86 specific) to boot state hooks.
Another reason to do this is the following:
On some platforms that start in dram it makes little sense to have
separate stages. To reduce the complexity we want to call the ramstage
main function instead of loading a full stage. To make this scheme
more maintainable it makes sense to move out as much functionality
from the 'main' function as possible.
Change-Id: I613b927b9a193fc076ffb1b2a40c617965ce2645
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63414
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_ONBOARD_SAMSUNG_MEM is not used anymore.
Remove CONFIG_ONBOARD_SAMSUNG_MEM.
This patch was intended to be part of CB:59754, but was not included in
the latest patchset.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: Id351bcafe005cc1b3319d7186ece2b5b9a7f49ac
Signed-off-by: Frans Hendriks <fhendriks.eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
There is a firewire chip TSB43AB22A mounted on the PCI bridge.
Add its definition to the device tree and mention it in the comment.
Change-Id: Iaa702b1efc15818ade2b1cd15aa6d415c3850e4b
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some devices/settings doesn't have helpful description in comments.
Update comments to describe the physical device on the board.
Change-Id: I479f41d71342104e74f862cf37b967963bc54877
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If a combo bootblock+romstage was created, it may
not have ENV_ROMSTAGE set, while the timestamp of
(embedded) romstage should remain in its place.
Change-Id: I713732a291b6a6c0d8fcb23266f765fd33816db8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With the purpose of linking ramstage inside the bootblock we likely
want to skip some ramstage CBMEM hooks and keep those only for
recovering data from earlier stages.
Change-Id: I317173d468073906d76228d1c8cc7bc28aae9e75
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.
Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current configuration is masking off IRQ 1 and IRQ 12 to the PIC.
This for some reason causes problems when using level triggered
interrupts. This change updates the PIRQ_MISC0 value to match what
skyrim is doing. This will enable level interrupts to work correctly.
BUG=b:218874489, b:160595155
TEST=Boot zork and verify keyboard still works. Boot with patch train
and verify keyboard works as expected.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I46b1fd68915c6f7aa4c34cdba57d24425752bc38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This removes the need for a tool to generate simple identity pages.
Future patches will link this page table directly into the stages on
some platforms so having an assembly file makes a lot of sense.
This also optimizes the size of the page of each 4K page by placing
the PDPE_table below the PDE.
Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Follow-up patches will add more to this makefile.
Change-Id: I8da6265b4c810e39a67f5ec27e26eeb26e3679a4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The patch adds support to control CSE Lite firmware update dynamically.
In order to disable the CSE firmware update functionality, offset 0xf00
in the coreboot binary be updated with 0x1.
Run below command on the binary to disable CSE firmwar update
printf '\x01' | dd of=image-brya4es.serial.bin bs=1 seek=3840 count=1
conv=notrunc
BUG=b:153410586
TEST=Verified CSE firmware update functionality is not getting
triggered after updating the offset:0xF00 in the coreboot binary.
........................ CB Logs ......................................
[DEBUG] prev_sleep_state 5
[DEBUG] cse_lite: Number of partitions = 3
[DEBUG] cse_lite: Current partition = RW
[DEBUG] cse_lite: Next partition = RW
[DEBUG] cse_lite: Flags = 0x3
[DEBUG] cse_lite: RO version = 16.0.15.1752 (Status=0x0, Start=0x2000,
End=0x19bfff)
[DEBUG] cse_lite: RW version = 16.0.15.1752 (Status=0x0,
Start=0x205000, End=0x439fff)
rt_debug: pre_mem_debug.cse_fw_update_disable=1
[DEBUG] Boot Count incremented to 956
.......................................................................
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9f234b142191eb83137d5d83f21e890e1cb828ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The patch fixes the buggy code which tries to access the Descriptor
Region. The existing code doesn't use correct APIs to access the
Descriptor Region. Hence, error message is getting displayed during
the boot.
BUG=b:229003612
TEST=Build and verify no errors seen while accessing the Descriptor
Region.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib144cc0845b7527e5a3032529b0802f961944b87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
PSP verstage can start at address 0 and use 200KB of PSP SRAM for
execution. Modify both the PSP SRAM start address and size for use by
PSP verstage.
BUG=b:220848544
TEST=Build Skyrim BIOS image with PSP verstage enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73e13b82faa0f443570a0c839e7699a79bdae024
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Create the mithrax variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:223091246
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MITHRAX
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I7c2fa6a74cc8e37397dea7e67e8cfa6506a49bdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
A new iteration of Google's TPM implementation will advertize a new
DID:VID, but otherwise follow the same protocol as the earlier design.
This change makes use of Kconfigs TPM_GOOGLE_CR50 and TPM_GOOGLE_TI50
to be able to take slightly different code paths, when e.g. evaluating
whether TPM firmware is new enough to support certain features.
Change-Id: I1e1f8eb9b94fc2d5689656335dc1135b47880986
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
<arch/cpu.h> is chain included through <cpu/cpu.h>.
Change-Id: I54a837394f67ac2a759907c7212ab947d07338dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
In Sabrina, PSP verstage uses a unified SVC call ID with sub-commands.
Update the SVC calls for Sabrina to pass the SVC_VERSTAGE_CMD (command
ID) with individual subcommands and the corresponding parameters.
BUG=b:220848545, b:217414563
TEST=Build the Skyrim BIOS image with PSP verstage enabled.
Change-Id: I56be51aa1dfb00e5f0945014600de2bbbec289db
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Include <stddef.h> since we need it for 'size_t'.
Unused <stdlib.h> found using:
diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/)
Change-Id: I3c2668013c16d6771268e8739b1370968c2e120b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.
BUG=b:211954778
TEST=Able to build google/redrix with these changes and boot to OS.
> localhost ~ # iotools mmio_read32 0xfe0018c4
0x85000000 (bit 31 is set)
> localhost ~ # iotools mmio_read32 0xfe001024
0x00062610 (bits 4, 17 and 18 are set)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic96da4638aa689b5fa47a3356986ca5a0343fe36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch implements the required operations to perform prior to
booting to OS using coreboot native driver when platform decides
to skip FSP notify APIs i.e. Post PCI Enumeration.
The smbus `.final` operation ensures locking the TCO register when
coreboot decides to skip FspNotifyApi() calls.
BUG=b:211954778
TEST=Able to build google/brya with these changes and coreboot log with
this code change as below with ADL SoC skip calling into FspNotifyAPIs:
[INFO ] Finalize devices...
[DEBUG] PCI: 00:1f.4 final
> localhost ~ # lspci -xxx | less
00:1f.4 Intel Corporation Alder Lake PCH-P SMBus Host Controller
(rev 01)
Offset 8, Bit 12 a.k.a TCO Lock bit is set (meaning locked).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie945680049514e6c5d797790a381a6946e836926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch drops SoC specific lpc lock down configuration as commit
63630 (soc/intel/cmn/pch/lockdown: Implement LPC lock down
configuration) implements the lpc registers lock down configuration in
common code.
BUG=b:211954778
TEST=Build.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I99ec6d63dfe9a8ac8d9846067a9afc3ef83dc1c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch implements a helper function to perform LPC registers lock
down configuration.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified LPC PCI
configuration register offset 0xDC bits BILD and LE are set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Typically, the SPIBAR_HSFSTS_W1C_BITS macro is used to clear all HSFSTS
register bit-fields with the W1C attribute.
So far SPIBAR_HSFSTS_W1C_BITS is 1 byte width hence, missed to clear
SAF_CE (bit 8).
This patch expands the `SPIBAR_HSFSTS_W1C_BITS` macro to include
SAF_CE (bit 8).
BUG=b:211954778
TEST=Able to build google/brya with this patch and clear SPI controller
HSFSTS_CTL register Bits 0 to 4 and 8.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifb58cef61118ca967e85226c1cf9db585e9ae4f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Terry Chen