Commit Graph

6674 Commits

Author SHA1 Message Date
Peter Stuge c6f0997ffc Northbridge: i945: Native VGA init: print the GMA and GTT addresses
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: Ieaaaa2611f7bb8968f01b16daefe7e2afe870f72
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:51 +01:00
Peter Stuge 03e4ac6671 Northbridge: i945: Native VGA init: use UMA address
The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: I4e88c26b70ea8cb249d7613c749b3edc5e3b5e7f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4000
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:38:02 +01:00
Peter Stuge c882d93054 Lenovo X60: Native VGA init: Get rid of the memory corruptions.
Without that fix the GTT points at 0x00000000.

The patch was made by Peter Stuge, I just split it
  and added a commit message.

Change-Id: Ia378b600ba2faf00d42635c6503b94ff0cb1bc8c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/4002
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:37:36 +01:00
Denis 'GNUtoo' Carikli 2186b6538e lenovo/x60: native vga init: fix code style issues.
Change-Id: I054edffbb38b13559da10180fc2c6cd9929ba162
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3999
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:37:02 +01:00
Andrew Wu 33b09567d2 dmp/vortex86ex: Move DMP specific POST code defines into one file
Move into src/cpu/dmp/dmp_post_code.h

Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:36:36 +01:00
Denis 'GNUtoo' Carikli 099b914dcd lenovo/x60: export reboot_bits nvram configuration.
This permits any software running after the ramstage to tell coreboot that the
  boot was successfull.

Change-Id: I6b19160dcf1ea1948360db71d02e344a3bcb44ef
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3992
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:35:38 +01:00
Duncan Laurie 25b8b7b881 haswell: Put each logical processor in its own P-state domain
The recommendation from Intel is to report each core as a
separate logical domain in the _PSD table.

This goes against the recommendation in the ACPI specification
because all of these cores are on the same package and share a
VR so they will do voltage transitions together.

The reasoning is that with a larger number of logical processors
the P-state often ramps too quickly resulting in higher power
consumption.  By exposing each core as a separate domain the OS
can manage them individually allowing the socket to select the
optimum frequency.

$ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
$ iasl -d /tmp/SSDT

Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000000,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000001,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000002,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000003,
      0x000000FE,
      0x00000001
    }
  })
}

Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:34:25 +01:00
Duncan Laurie 77647b33cf haswell: Update microcode for ULT/40651 to rev 8
$ cat /sys/devices/system/cpu/cpu*/microcode/version
0x8
0x8
0x8
0x8

Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4129
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:31:06 +01:00
Duncan Laurie 7a91816bdb Fix compile error in chromeos by adding stddef.h
Compile was failing with the following error:

In file included from src/vendorcode/google/chromeos/vboot_handoff.h:22:0,
                 from src/vendorcode/google/chromeos/chromeos.c:22:
vboot_reference/firmware/include/vboot_api.h:388:18: error: unknown type name 'size_t'
src/vendorcode/google/chromeos/chromeos.c: In function 'vboot_get_payload':
src/vendorcode/google/chromeos/chromeos.c:50:23: error: 'NULL' undeclared (first use in this function)

Change-Id: I13f9e41ef6a4151dc65a49eacfa0574083f72978
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48289
Reviewed-on: http://review.coreboot.org/4131
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:30:10 +01:00
Vladimir Serbinenko d26558cf5b Lenovo hotkeys support
Implement proprietary lenovo ACPI hotkeys

Change-Id: I36a6d3a280b0ac76d9ea063cdc10197a57e306f9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4055
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 00:20:04 +01:00
Vladimir Serbinenko 219f068ae3 Change EC GPE on X201
X201 has GPE at 0x11 (17) instead of 28.

Tested on X201.

Change-Id: Ib6306e6f085c4f6811df0789aa402a0d6901ed13
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4053
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-23 23:41:12 +01:00
Vladimir Serbinenko 617f853ae4 lib/coreboot_table: set type and size of framebuffer tag after fill_lb_framebuffer
When testing Ron's patch on qemu I found out that fill_lb_framebuffer
overwrites size and tag fields. We need either to fix/check all
fill_lb_framebuffer implementations or write tag/size after fill_lb_framebuffer.
I prefer later as it's more robust.

Change-Id: I98f5bac14f65fb4d990cb21426d402b27f2e8a48
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4263
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-23 18:40:40 +01:00
Vladimir Serbinenko 71f35ebdaa Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
2065x is with nehalem and not sandybridge.

I don't care much eitherway but it clears some confusion.

Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4046
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-23 14:32:29 +01:00
Vladimir Serbinenko e2b6795e04 Call X201 dock hooks in EC code
Unlike on X60/T60 dock has to be inited at the same time as EC.

Change-Id: If6eb3140c871859ce99027a50908f72bcc560243
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4082
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-23 13:09:56 +01:00
Vladimir Serbinenko 75b90a1f50 Remove MRC variables from 2065x CAR init.
2065x boards don't use MRC. And the space in question isn't used either.

Read number of variable range MTRRs from MSR rather than hardcoding it.

2ff is still zeroed out as unless you zero-out undocumented bits as well
boot fails.

Tested on Lenovo X201.

Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4080
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-23 13:08:50 +01:00
Vladimir Serbinenko 533ad10583 Don't wait on 2065x
The mdelay is not necessarry on 2065x.

Tested on X201 that it works without delay.

Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-22 22:35:58 +01:00
WANG Siyuan 87bdd86fe0 AMD f15tn, f16kb: Remove CDIT table and DMI table
On AMD Trinity and Kabini boards errors similar to the following are
shown.

	ASSERTION FAILED: file 'src/mainboard/asrock/imb-a180/agesawrapper.c',line 431
	DmiTable:100123f7, AcpiPstatein: 10010129,AcpiSrat:0,AcpiSlit:0, Mce:10010de9,Cmc:10010eab,Alib:1002111c, AcpiIvrs:0 in
	agesawrapper_amdinitlate agesawrapper_amdinitlate failed: 5

The reason is that on f16kb boards, the CDIT and DMI table are not
created. On f15tn boards, only the DMI table is not created.

Until the root cause is found, disable the table generation to remove
the errors.

Thanks to Wei Hu for debugging and reporting this issue on the list [1].

[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076607.html
    CDIT table is not created

Change-Id: I837e3c322bb5331a9b950a72397796a60642c3f3
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4092
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-11-22 20:29:06 +01:00
Vladimir Serbinenko fe6bdd96d8 Fix error message on wrong compiles of 2065x
Current error message refers to sandybridge chipset. Instead error
should be that 2065x needs Ibex Peak.

Change-Id: I8cc8a34f496aec7af0ce95b4b65fd25e165f43fb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4202
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-21 00:30:41 +01:00
Rudolf Marek 38c78889c5 Asus F2A85-M: Fix S3 memory power cut-off
The power to memory is lost during the the suspend, activate
the 3VSBSW# which switches the power during S3 suspend sequence.

As a result resuming from suspend to RAM works now, but now the
GPP ports of the Hudson southbridge are gone after resume from S3.
The devices 15.0 and 15.1 are disabled (decode as ffff) and
therefore anything behind them too [1].

[1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html
    fam15tn hudson PCIe GPP ports off after resume

Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4041
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-19 23:21:16 +01:00
Vladimir Serbinenko 113a366848 Add GRUB2 payload to build system
Since a long time GRUB 2 is a viable payload alternative to SeaBIOS and
FILO. So make it easy for coreboot users to use GRUB 2 as a payload by
integrating it into coreboot’s build system, so it can be selected in
Kconfig.

As the last GRUB 2 release 2.00 is too old and has several bugs when
used as a coreboot payload only allow to build GRUB 2 master until a new
GRUB release is done. The downside is, that accidental breakage in
GRUB’s upstream does not affect coreboot users.

Currently the GRUB 2 payload is built with the default modules which
results in an uncompressed size of around 730 kB. Compressed it has a
size of 340 kB, so it should be useable with 512 kB flash ROMs.

Tested with QEMU.

Change-Id: Ie75d5a2cb230390cd5a063d5f6a5d5e3fab6b354
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4058
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-19 01:07:25 +01:00
Ronald G. Minnich ef4020957e cbfs: 64-bit cleanups
cbfs used u32 in a number of cases where uintptr_t was
correct. This change builds for both 64-bit and 32-bit
boards.

Change-Id: If42c722a8a9e8d565d3827f65ed6c2cb8e90ba60
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4037
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18 21:22:38 +01:00
Ronald G. Minnich 7fda0e8e61 cbfs: remove unused code and prototype
The code is wrong (it's calling ntohl on an entry point that is actually
already le due to an old cbfs bug) and nothing calls it any more anyway.

Change-Id: Ief2c33faf99e3d2fc410524a5aae7bde378f088b
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4090
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-11-18 18:41:57 +01:00
Gerd Hoffmann e851a685ef qemu: set smbios entries from fw_cfg
Qemu makes the guest uuid (qemu -uuid $uuid) available
to the guest via fw_cfg.  Other smbios fields can be
configured in qemu using the -smbios command line
switch (check the qemu manpage for details).

This patch adds coreboot support for this, so the
values provided by qemu will actually show up in the
smbios table.

Change-Id: Ifd9ae0d02749af4e7070a65eadbd1a9585a8a8e6
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-18 12:50:42 +01:00
Gerd Hoffmann 06262743c7 smbios: make manufacturer, product_name and uuid runtime settable
Make manufacturer, product_name and uuid smbios fields (type 1)
configurable at runtime, simliar to version and serial number.

Change-Id: Ibc826225e31fa42aa944fa43632dd6a406d5c85d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-18 12:49:29 +01:00
Gerd Hoffmann d69da8475e qemu: load acpi tables from fw_cfg.
Starting with release 1.7 qemu provides acpi tables via fw_cfg.  Main
advantage is that new (virtual) hardware which needs acpi support
JustWorks[tm] without having to patch & update the firmware (seabios,
coreboot, ...) accordingly.

So if we find acpi tables in fw_cfg try loading them, otherwise fallback
to the builtin acpi tables.

Change-Id: I792232829b870ff6ed8414a3007e0af17f6c4223
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4040
Tested-by: build bot (Jenkins)
2013-11-15 12:43:35 +01:00
Paul Menzel 55b059385a Lenovo T60/X60: cmos.layout: Replace tabulators with spaces for consistency
Change-Id: Iec0abae8a4b18ac737e9ebb3eac219182729be0f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4057
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-15 01:04:52 +01:00
Vladimir Serbinenko d8cfd23f6a intel/2065x: Use TSC for udelay()
For the ram init of Intel Nehalem ram init we need a udelay implementation.
Use common TSC framework for it as Intel Haswell already does.

Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4043
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-13 00:38:45 +01:00
Zheng Bao 7b4a99c665 AMD Hudson: Move function s3_resume_init_data to southbridge
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also
change the final configuration. We need to make sure the settings in FchParam
in resume stage are the same as they were in cold boot stage, otherwise the
board can not wake up more than once.

Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180.

(USB keyboard doesn't work when board wakes up. It is not introduced by this
patch. It needs more debugging.)

Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/3932
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2013-11-12 16:40:48 +01:00
Gerd Hoffmann baa782020e qemu: load e820 from fw_cfg
qemu 1.7+ provides a fw_cfg file named "etc/e820" with e820-like entries
for reservations and ram regions.  Use it for ram detection if present,
otherwise fallback to the traditional cmos method.

Change-Id: Icac6c99d2a053e59dfdd28e48d1ceb3d56a61bdc
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4030
Tested-by: build bot (Jenkins)
2013-11-11 12:14:42 +01:00
Gerd Hoffmann 289b45fdff qemu: add fw_cfg files support
Qemu can provide files using the firmware config interface.
This is used to pass config options, virtual machine config
info and option roms into the guest.

This patch adds support for reading the file index and loading
files from qemu.

Change-Id: I57d4a734527c4117239f355121cf1fb8a390ab0d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4029
Tested-by: build bot (Jenkins)
2013-11-11 11:56:37 +01:00
Gerd Hoffmann a91daa5ba1 add memory clobber to ins{b,w,l}
Change-Id: Ia710eb59f23a52afba2a8ef6e0ff2b2306107245
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4033
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-11-10 20:41:52 +01:00
Marc Jones 04134a52b2 sio1007: Properly build '.c' files
Properly build the super i/o .c files.  This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.

Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4014
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-10 14:19:28 +01:00
Marc Jones c4b6f3bacb emeraldlake2: Clean up COM port enable
Remove the COM port enable loop. There is no need to
search for the port when it is needed and known by the
GPIO function.

Change-Id: Ie4e533fd9e49ed9ae62b209317b4b9853ff9926a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-10 14:12:55 +01:00
Marc Jones af0cd0921a console: Add hexdump32 function
Add a function to display memory locations in the console
logfile.

Change-Id: Iddb8d2e7a24357075f32c2fdf7916ae7a732247d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4013
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-11-10 14:12:31 +01:00
Marc Jones 2a58ecde78 Add new finalize functions for devices and chips
Many chipset devices require additional configuration after
device init. It is not uncommmon for a device early in the devicetree
list to need to change a setting after a device later in the tree does
PCI init. A final function call has been added to device ops to handle
this case. It is called prior to coreboot table setup.

Another problem that is often seen is that the chipset or mainboard
need to do some final cleanup just before loading the OS. The chip
finalize has been added for this case. It is call after all coreboot
tables are setup and the payload is ready to be called.

Similar functionality could be implemented with the hardwaremain
states, but those don't fit well in the device tree function pointer
structure and should be used sparingly.

Change-Id: Ib37cce104ae41ec225a8502942d85e54d99ea75f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4012
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-08 19:55:17 +01:00
Paul Menzel 0ce5ebf0a0 northbridge/intel/i945/raminit.c: Remove set but unused variable `reg16`
Change-Id: Id4a758644a7b799e7662113c07d395e053525934
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05 21:35:13 +01:00
Paul Menzel bf22338a09 southbridge/via/vt8237r/ctrl.c: Remove set but unused variable `regm3`
Change-Id: I6bb652419a54b7b7190e417346581f38335425ae
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3985
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05 21:33:38 +01:00
Kyösti Mälkki b0aec8f070 usbdebug: Fix build for ROMCC boards
Header file is not compatible with romcc, just drop it as a romstage
built with romcc cannot use usbdebug anyway.

Change-Id: If7f8f22d6a8fa1f02157df281f82f02b72b6a609
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4006
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-05 16:50:15 +01:00
Paul Menzel d0299e4b51 southbridge/intel/i82801ix/lpc.c: Remove unused variable `dummy`
Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for
QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail
with the following error.

	src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic':
	src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable]
	cc1: all warnings being treated as errors

Removing `dummy` should be safe as GCC probably optimizes it away before
anyway. That no dummy variable is used for an RCBA [1] access in Intel
Lynx Point supports that this can be dropped safely.

[1] root complex base address
[2] src/southbridge/intel/lynxpoint/early_pch.c

Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3982
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-30 16:18:04 +01:00
Andrew Wu 1ce4860405 vortex86ex: Defer checking PS/2 keyboard controller system flag
Don't check keyboard controller system flag until before calling
pc_keyboard_init(). This makes waiting time shorter.

Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3958
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-22 22:48:34 +02:00
Kyösti Mälkki ac16405799 usbdebug: Fix boards without EARLY_CBMEM_INIT
The main usbdebug file lib/usbdebug.c was removed from romstage
build with commit f8bf5a10 but the chipset-specific parts were not,
leading to unresolved symbol errors for AMD platforms.

Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient
use of this feature.

Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-22 21:35:05 +02:00
Jonathan A. Kollasch 553fe1cbc7 winent-mb6047: initial WIN Enterprises MB-60470 board port
What works:
 - ACPI interrupt routing for onboard devices
 - onboard devices including USBs, ATAs, NICs, COM1

What almost works:
 - SMI720 VGA BIOS needs forthcoming VGA BIOS hooks in SeaBIOS to work

Untested:
 - Interrupt Line Register interrupt routing
 - PIRQ interrupt routing
 - MPBIOS/MPTABLE interrupt routing
 - unpopulated on board revision 1A AC97 audio
 - unpopulated PCI-E x16 slot
 - unpopulated ExpressCard slot
 - HT expansion board

Thanks to WIN Enterprises for providing boards.

Change-Id: I7787f89b3ab454b668c3b75d0d1cde55b8d53c48
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3975
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-10-19 16:10:56 +02:00
Jonathan A. Kollasch e1ffd9ef7a winent-mb6047: copy tyan/s2891 mainboard directory
Change-Id: I382e30c92a4c428ec53dd959a5fda4927797fb9b
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3974
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-19 16:10:44 +02:00
Paul Menzel 6a4e9b547a get_bus_conf.c: reindent with indent
Change-Id: Ia0c37339aa69b92a1b518fa5e49adc4a7628ae5d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3979
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-10-18 17:44:56 +02:00
Andrew Wu cd9abf95e7 arch/x86/Makefile.inc: Pass $(AS) and $(CPP) to SeaBIOS
SeaBIOS’ Makefile requires cpp (C Preprocessor) to build. Modify
the xcompile script to search for cpp program path, and pass it to
SeaBIOS’ `Makefile.inc`. Also pass the program path for as (GNU assembler).

This is needed, so the crossgcc toolchain to build the SeaBIOS payload
under Mac OSX. OSX ships a cpp program, but it works differently
from GNU CPP, so we need to override it.

Change-Id: If996ffbb76ec4bd16079b54b41f3fac07bfe25be
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3896
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-17 01:59:50 +02:00
Kyösti Mälkki 697927cc35 CBMEM: Define cbmem_top() just once for x86
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.

Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:18:22 +02:00
Kyösti Mälkki 2644793ef4 Have option of timestamps, CBMEM console and usbdebug for most boards
As boards without EARLY_CBMEM_INIT do not initialize CBMEM in romstage,
and have no CAR migration, these features are available for ramstage only.

Change-Id: Ic3f77ccdedd4e71ba693619c02c9b98b328a0882
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:15:18 +02:00
Kyösti Mälkki 082c19ea89 CBMEM: Fail builds on missing get_top_of_ram()
Dummy get_top_of_ram() is removed from romstage to fail already at
build-time for cases where cbmem_initialize() would not complete.

The mechanisms behind CAR_GLOBAL migration only work correctly when
romstage can succesfully make the cbmem_initialize() call.

Change-Id: I359820fb196ef187b9aa2e8a3e8f658a0550f237
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3969
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:14:57 +02:00
Kyösti Mälkki 1a279046cd intel/i82371: Remove HAVE_ACPI_RESUME
This is needed to apply a rule that get_top_of_ram() in romstage is
required to select HAVE_ACPI_RESUME, otherwise chipset/board has no
means to backup low memory to CBMEM on s3 resume.

Only board affected is asus/p2b.

Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3971
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:14:29 +02:00
Kyösti Mälkki 29e9c22eb7 timestamps: Fix some lost timestamps for romstage
Timestamps from cbfs_and_run, TS_START_COPYRAM and TS_END_COPYRAM,
were lost with commit b766b1c7.

Reason is variable ts_table was referencing CAR storage after CAR
is torn doesn. Add use of car_get_var() / car_set_var() so the
references go to migrated storage in CBMEM.

Change-Id: I5a942ad7fd59a04e3a5255f4a3636d37dcfc1591
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-15 13:14:03 +02:00
WANG Siyuan 4ca721399c AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
resolve this issue.
I have tested on Ubuntu 13.04 with AMD Catalyst 13.4 Proprietary
Linux Display Driver[1].

[1]. http://support.amd.com/us/gpudownload/linux/Pages/radeon_linux.aspx

Change-Id: I5d2dddb1b7469d56cd64e3c1e0f4c6c6f095b4ab
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3934
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-15 05:02:25 +02:00
WANG Siyuan 2c86fc4343 ASRock IMB_A180: fix Ubuntu HDMI audio issue
Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can
resolve this issue.
I have tested on Ubuntu 13.04 with latest graphic driver.

Change-Id: I09c19b8925eedee03cfb1d8c0831a84e8aeeba4f
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3937
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-10-15 05:02:06 +02:00
WANG Siyuan f38145e81c AMD Olive Hill: fix Windows 7 HDMI audio issue
Windows 7 cannot find HDMI audio device because of acpi setting.
I have tested on Windows 7. I can play music.

Change-Id: I90ade7e7be79f65783922333c2cbb2d3cc6557ea
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-10-15 05:01:36 +02:00
WANG Siyuan 7b6d412dbc vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-15 05:01:11 +02:00
Kyösti Mälkki f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Jonathan A. Kollasch cf18c856aa ck804: hide IOAPIC base address in PCI_BASE_ADDRESS_1
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is
0xfec00000 (that is, outside the range of bus 0 address space).  This
causes IOAPIC interrupts to fail to work under Linux.  This issue was
originally unnoticed by me when testing as sanity checking such as
this is not done by NetBSD.

Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've
checked.

Change-Id: I736db163750f709d68c988fac075597a50b29ab7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3963
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14 02:22:07 +02:00
Jonathan A. Kollasch 948dede9c5 ck804: obtain stored IOAPIC address from allocator instead of register
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3961
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14 02:18:48 +02:00
Jonathan A. Kollasch b679525538 ck804: obtain I/O APIC base address for ACPI MADT from allocator
Change-Id: I67192c8ae99e396ea4b17e03c658f31dbb5c1800
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3960
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-14 02:17:03 +02:00
Andrew Wu 3fa1a13f62 dmp/vortex86ex: Initialize PS/2 keyboard.
Call pc_keyboard_init function in southbridge. It makes PS/2
keyboard work in coreinfo payload.

Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3957
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-13 19:11:48 +02:00
Paul Menzel 7a00ca75d7 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable `reg` in `setup_mtrr_dqs()`
Change-Id: I7fc7819c329c058472031e82237be5c170b277f4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3965
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-13 19:10:10 +02:00
Jonathan A. Kollasch 772d026076 ck804 lpc: use PCI_BASE_ADDRESS_1 instead of 0x14
Change-Id: I752a4a890e1f610651a2c688cf42350ce8e9deaa
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-10-13 18:13:56 +02:00
Stefan Reinauer fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Jonathan A. Kollasch 8ad6e78778 Nvidia boards: acpi_tables.c: Remove intermediate variable in ACPI interrupt routing initialization
Change-Id: I6cb4ad5ea5ad40284f8e88ff440f2605d3b83359
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-10-12 16:13:59 +02:00
Kyösti Mälkki 4f9bf7e2fb AMD hudson yangtze: Fix corruption of a global ramstage variable
A late for loop may reference over the current array allocation
and corrupt an unrelated global variable. As a quick fix bumb the
size of the array allocation uniformly to 6.

We missed these boards for commit 9c7d73ca because the arrays
had been renamed.

Change-Id: Iff2f2a0090d9302576bc72195d2a3f6fa37ce29a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3954
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-07 19:09:34 +02:00
Paul Menzel 11b47801b2 cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`
When building coreboot with the Clang static analyzer scan-build,
it reports »Value stored to 'type_index' is never read«. Indeed,
in `memranges_each_entry()` `type_index` is assigned a value
before being read. So remove that line.

Change-Id: I6da2fb8be7157bb98c57281babd4a08ca0d9f7a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3953
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-03 15:17:05 +02:00
Gerd Hoffmann b142a51542 qemu: q35: avoid address conflict
Qemu has the fw_cfg interface at 0x510, which conflicts with 
power management base address in coreboot.  Move the pmbase to a
non-conflicting address.  No need to worry about speedstep, it
is not supported by qemu and isn't enabled in the qemu config.

Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-10-01 18:31:42 +02:00
Allen Martin 681d17e0bf exynos5420: Fix build warning
Fix "set but not used" variable warning with gcc 4.7.3

Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-on: http://review.coreboot.org/3949
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-09-28 22:25:14 +02:00
WANG Siyuan 616e6fb252 ASRock IMB_A180: fix Windows 7 HDMI audio issue
Windows 7 cannot find HDMI audio device because of acpi setting.
I have tested on Windows 7. I can play music.

Change-Id: I53177ce00b676824a903a3397d69338e8c1a38af
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3936
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-27 12:11:27 +02:00
Kyösti Mälkki a1179cafdb usbdebug AMD: Add choice of EHCI controller
Chipsets sb700 and sb800/hudson have more than one USB EHCI controller,
implement the selection logic using already existing Kconfig option.

Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-25 07:50:37 +02:00
Corey Osgood 5a7e127cd4 southbridge/cimx/sb900: Rename headers to match sb700 & sb800
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 & 
sb800, and points agesa/family12 and amd/torpedo to the new file 
names.

Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-24 01:20:02 +02:00
Kyösti Mälkki cbf5bdfe67 CBMEM: Always select CAR_MIGRATION
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.

This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.

Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:34:55 +02:00
Kyösti Mälkki de1fe7f655 CBMEM: Always have early initialisation
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.

If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.

Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:26:54 +02:00
Kyösti Mälkki a2f6af3330 ROMCC boards: Fix builds with CBMEM console, timestamps or usbdebug
These features depend on CAR_GLOBAL region, which is not available
when romstage is built with ROMCC. Exclude these from romstage, keep
them available for ramstage.

A follow-up patch will fix the dependencies and allows enabling these
features in menuconfig.

Change-Id: I9de5ad41ea733655a3fbdc734646f818e39cc471
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:22:33 +02:00
Kyösti Mälkki 52a2722389 CBMEM console: Support late init
It is not compulsory to have CBMEM console initialised in romstage,
so try add the CBMEM table entry again in ramstage, if not found.

Change-Id: I96ab502df7f05d6bf1d6e6fa84d395ef6306b525
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3915
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:21:53 +02:00
Kyösti Mälkki f56ff9069e timestamps: Only collect from BSP CPU
We only have one table to collect timestamps into.

Change-Id: I80180fe9a05226f0351c3e66eacaf2d0cb82c924
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:21:30 +02:00
Kyösti Mälkki c0beb6d418 timestamps epia-m850: Cleanup without enabling timestamps
Remove the existing hack, platform needs a fix for EARLY_CBMEM_INIT.

Change-Id: I7ce373c9698878d9fa056983e4fb571a68239c52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3913
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:21:13 +02:00
Kyösti Mälkki 3d45c40776 timestamps: Stash early timestamps in CAR_GLOBAL
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3910
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:44 +02:00
Kyösti Mälkki b766b1c76a timestamps: Use stash before CBMEM is usable
Change-Id: I9e927abdb1d7d9c233de5620a9a65b419e803ebf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:21 +02:00
Kyösti Mälkki e28bd4ade6 timestamps intel: Move timestamp scratchpad to chipset
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.

Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:02 +02:00
Kyösti Mälkki d2dac0a7d6 usbdebug: Allow an USB hub on the debug dongle
Some development kits with USB 2.0 HS OTG have an USB hub instead
of being directly connected to the USB host/device controller.

Send the necessary initialisation sequence, using HUB CLASS requests
of PORT_POWER and PORT_RESET to enable a pre-selected port number
where a device supporting debug descriptor is located.

This also adds the Kconfig option for BeagleBone.

Change-Id: I7a5d0ba0962a9ca06bf3196232ed4a03bdfb2b06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3925
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-20 14:22:29 +02:00
Rudolf Marek 8f485dee0d ASUS F2A85-M: Correct and clean up PCIe config
Assign the lanes correctly to the physical slots
on the motherboard in `PlatformGnbPcie.c`.

• UMI is connected to SB via 4x PCIe bridge 8.
• The blue x16 slot is not shared with DDI and is routed
  through PCIe bridge 2.
• The black x8 slot is in fact a x4 slot and uses all 4 GPPs
  from the CPU.
• Assume that DDI is on out-of-PCIe-band lanes.

Change-Id: I44c4c83e6a8e31d6150a602a0993972ac63105bd
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-09-19 19:53:30 +02:00
Gerd Hoffmann ad690f2e81 qemu: q35: fix pci bar placement
Without this coreboot may (depends on the amount of memory) place the
pci bars below 0xb0000000, then the linux kernel goes move them around
so they are inside the window declared in the acpi tables.

This breaks vesafb as the vga framebuffer gets moved after vgabios
initialization.  It's also not exactly nice to expect the OS fix our
mess ;)

Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3927
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-09-18 12:07:02 +02:00
Kyösti Mälkki ecd8424919 Fix whitespace leaked into tree
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.

Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 21:04:35 +02:00
Gabe Black 73cffd6999 beaglebone: Stop reinitializing the console in bootblock.c.
The console has already been initialized in the generic bootblock code, and
reinitializing it causes the same banner line to be printed twice and lots of
artifacts in the actual output. This same change had been made to the other
ARM boards but not for beaglebone.

Change-Id: I72e3be1326b1a52b7ec438a44e4fd5f87e4ec717
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3924
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17 01:00:39 +02:00
Gabe Black 4938a329ee ARM: Add some missing dependencies on config.h to ARM's Makefile.inc.
These dependencies came indirectly through kconfig.h which was included
automatically with a -include option which was either part of INCLUDES or
specified directly. With this change, I'm able to build for beaglebone with
make -j 48.

Change-Id: Ib57d0c6a755b747165b235c2328c3c30bd6dd67d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3922
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-17 01:00:12 +02:00
Gabe Black ccf4fdd1cd am335x: Update the config vars selected by CPU_TI_AM335X.
The way those variables work has changed twice since this file was last
changed, and console output was no longer working. Now that they're up to
date there's serial output from beaglebone again.

Change-Id: I5167fd8c0a8c33438d7f056fdf5951bd054010ed
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3923
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 00:41:01 +02:00
Kyösti Mälkki 0fbbff48bf CBMEM: Rename high_tables variables and make them static
Old name was too much x86.
All external references have been removed.

Change-Id: I982b9abfcee57a7ea421c245dadb84342949efae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3906
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:22:00 +02:00
Kyösti Mälkki 625f103ae8 CBMEM: Drop parameters from cbmem_init()
The parameters can be dropped as initialisation always happens for
the region resolved with cbmem_locate_table().

This is no longer referenced externally, make it static.

Change-Id: Ia40350a5232dcbf30aca7b5998e7995114c44551
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:20:52 +02:00
Kyösti Mälkki d50cdf108f CBMEM: Drop parameter from cbmem_reinit()
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE
which equals cbmem_base, thus no need to pass it as a parameter.

Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:20:25 +02:00
Kyösti Mälkki 95c39c28a3 CBMEM ARM: Prefer get_cbmem_table() over cbmem_late_set_table()
Implementing get_cbmem_table() allows initializing CBMEM earlier.

Change-Id: I973f3a84dd9aaa2839959df5dda22909fdb9edeb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3560
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:19:36 +02:00
Kyösti Mälkki f9f74afdd7 CBMEM x86: Unify get_cbmem_toc()
Remove any chipset-specific implementations and use arch-specific
implementation of get_cbmem_table() instead.

Change-Id: I338ee2c1bd51f5e517462115170dc926e040159e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3907
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:18:53 +02:00
Kyösti Mälkki bc90e15d3f CBMEM: Backup top_of_ram instead of cbmem_toc
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.

TODO: Redesign these get_top_of_ram() functions from scratch.

Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:18:02 +02:00
Kyösti Mälkki c04afd6433 CBMEM: Add cbmem_locate_table()
For both romstage and ramstage, this calls an arch-specific function
get_cbmem_table() to resolve the base and size of CBMEM region. In ramstage,
the result is cached as the query may be relatively slow involving multiple PCI
configuration reads.

For x86 CBMEM tables are located right below top of low ram and
have fixed size of HIGH_MEMORY_SIZE in EARLY_CBMEM_INIT implementation.

Change-Id: Ie8d16eb30cd5c3860fff243f36bd4e7d8827a782
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:17:14 +02:00
Kyösti Mälkki dcb688e5ec CBMEM: Unify get_top_of_ram()
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:16:00 +02:00
Kyösti Mälkki e1ea802ea6 CBMEM tables: Remove references to global high_tables_base
Unify checks and writing of CBMEM tables for x86 and ARMv7.

Change-Id: I89c012bce1b86d0710748719a8840ec532ce6939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3559
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:15:10 +02:00
Kyösti Mälkki 1ae305efe1 CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base
This helper function is for compatibility only for chipsets that do
not implement get_top_of_ram() to support early CBMEM.

Also remove references to globals high_tables_base and _size under
arch/ and from two ARMv7 boards.

Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3902
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:12:15 +02:00
Kyösti Mälkki 42f4651434 CBMEM northbridges: Remove references to global high_tables_base
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.

Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:09:47 +02:00
Kyösti Mälkki 2b790f6512 CBMEM AMD: Fix calls to set_top_of_ram_once()
We can postpone the call to set_top_of_ram_once() outside the
loops and make just one call instead.

As set_top_of_ram() is now only called once, it is no longer
necessary to check if high_tables_base was already set.

Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11 07:09:21 +02:00
Kyösti Mälkki e7e847cd5c CBMEM AMD: Remove references to global high_tables_base
Prepare for removal of globals high_tables_base and _size
by replacing the references with a helper function.

Added set_top_of_ram_once() may be called several times,
but only the first call (with non-zero argument) takes effect.

Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:06:15 +02:00
Kyösti Mälkki 9c7d73ca3f AMD sb800 sb900: Fix corruption of a global ramstage variable
A late for loop may reference over the current array allocation
and corrupt an unrelated global variable. As a quick fix bumb the
size of the array allocation uniformly to 6.

Change-Id: Ib067fdf077e091d13e32cc3a8e4a0b713d19bcc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-09-11 07:05:25 +02:00
Kyösti Mälkki c984f4f303 AMD AGESA: Place CAR_GLOBAL in BSP stack
Use BSP CPU's stack space to store CAR GLOBALS for the
duration of romstage before CAR migration.

NOTE: Such globals can only be accessed from BSP CPU due
the way AMD platform has memory architecture set up.

TODO: Add compile-time assertions to verify CAR configuration
matches with the programming in vendorcode.

Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3832
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-09-11 07:03:44 +02:00
Kyösti Mälkki 6f9fa8634a intel/i5000: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: Ibe2fea68854af465900e443959a745a7167fb753
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3813
Tested-by: build bot (Jenkins)
2013-09-10 20:23:37 +02:00
Kyösti Mälkki 8aa7e83994 intel/i945 intel/i82801gx: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10 18:22:04 +02:00
Kyösti Mälkki 9b143e1474 intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-10 18:20:34 +02:00
Kyösti Mälkki 35a7249183 intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO for all boards
with gm45 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.

Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3600
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-10 18:19:58 +02:00
Kyösti Mälkki 0306b50280 usbdebug: Fixes for LynxPoint LP
Keep the EHCI BAR unchanged to keep usbdebug working.

Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06 00:39:04 +02:00
Kyösti Mälkki 690bf2f333 usbdebug: Use CAR migration
If we already initialized EHCI controller and USB device in romstage,
locate active configuration from salvaged CAR_GLOBAL and avoid doing
the hardware initialisation again.

Change-Id: I7cb3a359488b25abc9de49c96c0197f6563a4a2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3476
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06 00:36:16 +02:00
Kyösti Mälkki e53cece07b usbdebug: Dump low-level protocol details
Dumping these EHCI host controller registers is useful to
solve problems with debug devices.

Change-Id: I0610cecca57b1b952d4f87211dd00c8c0bc398b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3866
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06 00:33:51 +02:00
Kyösti Mälkki 5c87d2f17e usbdebug: Adjust endpoint retry timeouts
Change Setup Stage of control messages to have no retries, while data
and status stages may retry until timing out after 1000 retries.

The correct amount of retries might vary by endpoint and device dongle
used, so make it a variable.

Change-Id: I63313f994d0bd3444a3aab527ca942da5de9e6fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3882
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06 00:32:41 +02:00
Kyösti Mälkki 2de841b355 usbdebug: Adjust transaction retries
Transaction consistently completes with 80 to 150 status reads on my
setups. Hardware should always be able to complete this within 125us
as the debug port is serviced at the beginning of each microframe.

Timeout is set to DBGP_MICROFRAME_TIMEOUT_LOOPS=1000 status reads. Do not
retry transactions if this timeout is reached as the host controller
probably needs full re-initialisation to recover.

If this timeout is not reached, but a transaction is corrupted
on the wire, or it is otherwise not properly delivered to the USB device,
transaction is retried upto DBGP_MICROFRAME_RETRIES=10 times.

Change-Id: I44bc0a1bd194cdb5a2c13d5b81fc39bc568ae054
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3881
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-06 00:32:26 +02:00
Patrick Georgi 16ae95c4bc Add Kconfig options for Linux as payload
These allow to define a kernel image, initrd and command line.

Change-Id: I40155b812728a176b6d15871e1e6c96e4ad693c8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3893
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:39 +02:00
Patrick Georgi 2f39eae41d Remove NRV2B compression support
It wasn't even hooked up to the build system anymore.

Change-Id: I4b962ffd945b39451e19da3ec2f7b8e0eecf2e53
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3892
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-31 08:58:37 +02:00
Kyösti Mälkki dcccbd1396 usbdebug: Fix control messages
Add support for control messages with a write of data stage.

Add status stage after a read of non-zero length data stage.

Do not retry control message if device responds with STALL.

Change-Id: I16fb9ae39630b975af5461b63d050b9adaccef0f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3867
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:39:54 +02:00
Kyösti Mälkki e29584c141 usbdebug: Use separate data toggle for each pipe
USB defines a mechanism to detect certain cases of lost handshakes
using an alternating data sequence number, referred to as data
toggling. This patch fixes each pipe to have its own tracking of
the data toggle state.

Change-Id: I62420bdaeadd0842da3189428a37eeb10c646900
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3865
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:39:33 +02:00
Kyösti Mälkki 75d006232a usbdebug: Reference endpoints by pipes in calls
Add allocation for endpoint0 as a pipe for control messages.

Endpoint number was already stored in the pipe object, place devnum
there too, although all pipes will use same devnum==127.

Change-Id: I299d139bdd8083af8b04a694e8e41435ec026a25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3864
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:39:11 +02:00
Kyösti Mälkki 545b30d151 intel usbdebug: Add choice of EHCI controller
Add option to choose one of the EHCI controllers in recent
intel chipsets for usbdebug use.

Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in
rcba_config() for some mainboards, check the PCI class code
for match.

Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:36:47 +02:00
Kyösti Mälkki 8101aa6bb0 usbdebug: Support choice of EHCI controller
Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.

Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:36:20 +02:00
Kyösti Mälkki 2410010018 usbdebug: Change debug port scanning
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
all physical ports one after other in incrementing order. To avoid
possible problems with other USB devices, one can select the port
number here and bypass the scan.

Intel platforms can communicate with usbdebug dongle on one
physical port only, and this option makes no difference there.

Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-29 18:35:47 +02:00
Patrick Georgi f7381f8cd1 kontron/ktqm77: Allow disabling onboard NICs
Two new nvram variables control disabling the two non-ME NICs
on the mainboard. This is implemented by disabling their PCIe bridge.

Change-Id: I086f0d79de3ad0b53fa0ec40648d63378070e3bd
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3870
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-29 10:06:26 +02:00
Paul Menzel ab6d27e8f8 lenovo/x60/romstage.c: Collect timestamps in romstage
Collect early timestamps in Lenovo X60’s romstage.

Selecting the option `COLLECT_TIMESTAMPS` in Kconfig and then
doing `cbmem --timestamps` should output the timestamps.

Change-Id: I7bd30f03a1b85c38e89c19cdf88b2d20b24abed8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3587
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-29 01:56:48 +02:00
Stefan Reinauer 3c46ca33a1 Sandybridge/Ivybridge: Unify and fix Kconfig defaults
Change-Id: Ia4a5530e6a1a1fd2dec6f348ff163b5c7a8cd4cd
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-29 00:52:41 +02:00
Patrick Georgi 12ba1978ba kontron/ktqm77: Drop MRC_FILE definition
The northbridge defines it already and to the same value.

Change-Id: Ia5d856258fac52ea0b249142f70a89123ca04f82
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3876
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 23:39:11 +02:00
Stefan Reinauer dedcc78ff4 Fix up Stumpy/Lumpy PEI data for system agent r6
Change-Id: I79937fd1671af23184ab830d5ba6242c8067d944
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-28 23:38:39 +02:00
Bruce Griffith 5bdcff5374 ASRock IMB-A180: Add CODEC initialization table
Change-Id: Ic4d191bd34179af707449a15026079da1412ed60
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3886
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2013-08-27 19:59:03 +02:00
WANG Siyuan f77f734d38 ASRock IMB-A180: Add new AMD Embedded G-Series SOC mainboard
Tested on Ubuntu 12.10. S3 is supported. No HD Audio.
Mainboard details: http://www.asrock.com/ipc/overview.asp?Model=IMB-A180

Change-Id: I75254194ab5da8e5c61383d8f85aa4e300815637
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3880
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-27 19:08:36 +02:00
WANG Siyuan a9b01d1347 AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in Yangtze
src/southbridge/amd/agesa/hudson/Kconfig config default value,
mainboard Kconfig config value for specific mainboard.
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3

Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3879
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-27 19:08:20 +02:00
Kyösti Mälkki 021fa78bca usbdebug: Change reference to EHCI BAR
Change the defines, as follow-up patch will replace use of
constant CONFIG_EHCI_BAR.

Change-Id: I44ff77cb7a2826f3b43d8d46440fd4482a29d18c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3875
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:38:52 +02:00
Kyösti Mälkki c73acdb69e Add test to match struct device with pci_devfn_t
Add a function to test if pci_devfn_t matches with a device
instance of struct device, by comparing bus:dev.fn.

Change-Id: Ic6c3148ac62c7183246d83302ee504b17064c794
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3474
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:38:23 +02:00
Kyösti Mälkki 842f0bab04 Add pnp_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PNP access
functions for ramstage using the inlined functions from romstage.

Change-Id: I2a0bd8194acaf9c4c7252a29376eec363397e3a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3871
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:38:03 +02:00
Kyösti Mälkki 3f9a62e5ad Add pci_devfn_t and use with __SIMPLE_DEVICE__
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.

Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 07:37:12 +02:00
Kyösti Mälkki a2adaeb68c usbdebug: Only test two possible USB device numbers
After an USB device sees USB bus reset on the bus, it will reset to
device number 0. Per the EHCI debug port specification, a debug
dongle device may reset to the fixed debug device number of 127 instead.
Thus there is no need to try device numbers from 1 to 126.

Do a sanity-check on a returned debug descriptor as I experienced
some USB flash memory to respond on this request with zero-fill data.

Change-Id: I78d58f3dc049cd8c20c6e2aa3a4207ad7e6a6d33
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3861
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-24 05:52:03 +02:00
Kyösti Mälkki 16c014578b usbdebug: Halt host controller before resetting it
Resetting an EHCI controller when it is not halted can have
undefined behaviour. This mostly fixes a case where calling
usbdebug_init() twice would fail to reset the USB dongle device
properly.

On amd/persimmon it still requires one extra retry, but at least it
is now possible to have usbdebug enabled for both romstage and
ramstage.

Change-Id: Ib0e6e5a0167404f68af2edf112306fdb8def0be9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3862
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-08-23 05:11:03 +02:00
Kyösti Mälkki 1cf85774da SPI: Support STMicro partial page write
Ported from spi/winbond.c.

Fixes this error:
   ICH SPI: Too much to write.
   Does your SPI chip driver use CONTROLLER_PAGE_LIMIT?

Change-Id: I50db8fd1104d3b7d319b278b14f97e3ff9cb6404
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3877
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-08-23 05:07:11 +02:00
Kyösti Mälkki 93b2bd70ff usbdebug: Do not support logging from SMM
Letting SMI handler touch EHCI controller is an excellent source
of USB problems. Remove usbdebug entirely from SMM.

It may be possible to make usbdebug console work from SMM
after hard work and coordination with payloads and even
OS drivers. But we are not there.

Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3858
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-08-23 05:05:34 +02:00
Kyösti Mälkki 6bfe61d5d1 usbdebug: Add compatibility quirk for FX2
This quirk is needed with a DIY debug dongle using obsolete
CY7C68013 (aka FX2) USB chips. Old revision of chip requires a
SET_CONFIGURATION to be sent, while this is not required in EHCI
debug port specs.

Change-Id: I4926eb19b7e991d6efeef782682756571ad006b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-08-23 05:04:30 +02:00
Kyösti Mälkki d79914008a usbdebug: Block recursive calls of printk
When we create low-level debugging of EHCI controller registers,
we call printk() within printk(). In ramstage this would leave us
with deadlock waiting on the console spinlock.

Change-Id: Idbe029af9af76de27094bb2964c60d9ccfdd96e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3860
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-23 05:02:54 +02:00
Kyösti Mälkki 8ff3d68e93 usbdebug: Add logging level to debugging
Increase existing level from DEBUG to INFO.

Change-Id: Ic5934aec449f921af96dd3a6524f7275f8de1304
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-23 05:02:10 +02:00
Andrew Wu eabfd3a7c1 Don't include LZMA in romstage if ramstage is not compressed.
If ramstage is not compressed, the CBFS module in romstage doesn't
need to support LZMA. Removing the LZMA module in this case can save
about 3000 bytes in romstage.

Change-Id: Id6f7869e32979080e2985c07029edcb39eee9106
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3878
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-19 21:05:44 +02:00
Paul Menzel 4159a8012e Correct spelling of shadow, setting and memory
Change-Id: Ic7d793754a8b59623b49b7a88c09b5c6b6ef2cf0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3768
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 22:25:56 +02:00
Christian Gmeiner 95b573a2db AMD Southbridge CS5536: make use of #include <device/smbus_def.h>
Change-Id: Ia2dff49d3e2b086546785d992f2d92bcf4d1ef1c
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 11:27:54 +02:00
Bruce Griffith 59c3a06154 AMD AGESA: Remove INVD instruction when transitioning from CAR
The AMD AGESA function to move the stack from cache-as-ram to
actual RAM doesn't need any help.  The current implementation has
an INVD instruction just before cache-as-RAM is torn down. It isn't
needed for Trinity processors and makes Kabini boot unreliable.

Change-Id: Ibe9e4105eee032471ccbb2d537471d5fa5847d22
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3852
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-16 11:20:05 +02:00
Patrick Georgi 540d8eaac9 kontron/ktqm77: Update MRC path
It still pointed to the old binary despite implementing the newer interface

Change-Id: Iebd5dae98168f5568f3ad6a18c5ebde9abc3ece0
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3869
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-16 10:52:18 +02:00
Patrick Georgi 3f34fc4bf3 emulation/qemu-i440fx: style cleanup
Drop unused and commented out variable, and fix a comment while at it.

Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3873
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-16 10:50:36 +02:00
Patrick Georgi 1e44c3ff5a Fix lint-stable target
SEABIOS_PS2_TIMEOUT needs a default, otherwise the "allyesconfig" target
hangs in an endless loop.
The given default is correctly overridden by the (currently sole) user,
the lenovo/x60 target.

Change-Id: I3f5e347c29ccbb4d711a489d067b6c909f030bd0
Reported-by: Kyösti Mälkki
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2013-08-16 10:32:43 +02:00
Kyösti Mälkki 361cd8153d console: Squelch console output from AP CPUs in romstage
Add Kconfig option SQUELCH_EARLY_SMP and have it enabled by
default.

Console drivers have unpredictable results if multiple threads
attempt to share same resources without spinlock. Serial UARTs
have not had huge problems, only distorted output, but those
relying on cache-as-ram (CBMEM and usbdebug) may require this.

Change-Id: I7f406fdea7b6dc6a341c4da2fab56f7b7ff568b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3854
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-16 05:39:47 +02:00
Christoph Grenz 7037840ece w83627hf/acpi: Move floppy drive enumeration from _INI into _FDE.
Move the floppy drive enumeration from _INI() and PROB(),
which stored the enumeration results into _FDE into _FDE().
_INI is called by any ACPI-capable OS on boot while _FDE
is rarely used. So it's better to run the enumeration when
requested rather than unconditionally.

Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 21:30:53 +02:00
Christoph Grenz bbf096911d w83627hf/acpi: Make `AddressMax` a multiple of `AddressAlignment`
The parallel port of the W83627HF can be configured on any port
between 0x100 and 0xFFC with 4 byte alignment for traditional modes
and 8 byte alignment for EPP mode. As the ACPI specification says
that the maximum acceptable starting address has to be a multiple
of the alignment granularity, correct the maximum starting address
from 0xFFC to 0xFF8.

Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/2942
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15 21:21:53 +02:00
Kyösti Mälkki c66f1cbdae Include boot_cpu.c for romstage builds
ROMCC boards were left unmodified.

Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:49:03 +02:00
Peter Stuge f040858ec3 payload/SeaBIOS: Add SEABIOS_PS2_TIMEOUT Kconfig variable
This allows mainboards to preconfigure a ps2-keyboard-spinup
timeout when SeaBIOS is chosen as the payload.

The Kconfig option can be changed manually if CONFIG_EXPERT is set.

Change-Id: I5732b18ef04f4bdef6236f35039656ad02011aec
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3734
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15 20:46:21 +02:00
Gerd Hoffmann a4e70578db qemu: fix ioapic reservation
The slightly hackish ioapic ressource reservation is needed for i440fx
emulation only, for q35 the ich9 southbridge driver handles this just
fine.

[ Side note: The i440fx chipset emulated by qemu is pimped up with alot
             of stuff which never existed on real hardware, which leads
             to tweaks like this one. ]

Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3850
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:37:48 +02:00
Rudolf Marek 1e1a1798fa ASUS F2A85-M: Provide HD Audio verb table for Realtek ALC887-VD
Use the same HD Audio [1] verb table for the Realtek ALC887-VD
audio chip as the one set up by the proprietary vendor BIOS.
Linux’ ALSA exposes this pin configuration under the virtual
filesystem sysfs.

    /sys/class/sound/hwC1D0/init_pin_configs

The script `alsa-info.sh` [2][3] is able to decode the table.

Only one channel audio playback (rear connectors) is tested [4],
which worked already before.

[1] http://en.wikipedia.org/wiki/Intel_High_Definition_Audio
[2] http://mailman.alsa-project.org/pipermail/alsa-devel/2013-March/060717.html
[3] http://alsa-project.org/main/index.php/Help_To_Debug
[4] http://review.coreboot.org/#/c/3170/2//COMMIT_MSG

Change-Id: I17fa2d4ab1e1a6bfd84de94e9e4a91bd67b6a0c0
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15 20:34:38 +02:00
Paul Menzel 1ae7d475a8 AMD Fam15tn boards: BiosCallOuts.c: Remove board name from `CodecTableList`
The board name in that variable name is not necessary, as it is not board
dependent, that means using the file as a template for making a new
coreboot port for another motherboard the variable does not need to be
changed, and just increases the code differences between AMD Parmer,
AMD Thather and ASUS F2A85-M. So use a generic name.

The same was done for AMD Persimmon (and inherited by the LiPPERT
FrontRunner/Toucan-AF) in the following commit.

    commit 5e70766f14
    Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Date:   Tue Feb 26 15:56:11 2013 +0100

        AMD Fam14 boards: reduce unnecessary differences, 2nd attempt

        Reviewed-on: http://review.coreboot.org/2529

The board name is *not* removed from the `CODEC_ENTRY` variable name as
the verb table not only depends on the codec but also on the board [1].
Having the board name in the variable name is a good indicator that the
pin configuration needs to be adapted when taking this file as a template
for a new port. If it was board independent, a default chip configuration
could be used and shared between all boards, which is unfortunately not
the case.

[1] Unfortunately I was not able to find Jens’ comment in my mail archive
    and in the Gerrit Web interface. Not sure where it is, but I am sure
    he made that comment.

Change-Id: I440a306cf4ff0a5b1b61d1983d70c66d129904d0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3199
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:34:27 +02:00
Christoph Grenz dc92d682ff w83627hf/acpi: Fix logical device power down in ACPI
As Nico noticed for the W83627DHG, the power management bits to power down
individual logical devices on Winbond superios are named counterintuitively
and need to be set when the logical device should be powered.

This corrects the power management methods for the W83627HF.

Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3605
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15 20:32:35 +02:00
Gabe Black ec3a462d03 CBFS: Change how the bss is zeroed when loading a stage.
For reasons explained in a previous CL, it might be necessary to "load" a file
from CBFS in place. The loading code in CBFS was, however, zeroing the area of
memory the stage was about to be loaded into. When the CBFS data is located
elsewhere this works fine, but when it isn't you end up clobbering the data
you're trying to load. Also, there's no reason to zero memory we're about to
load something into or have just loaded something into. This change makes it
so that we only zero out the portion of the memory between what was
loaded/decompressed and the final size of the stage in memory.

Change-Id: If34df16bd74b2969583e11ef6a26eb4065842f57
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3579
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:13:39 +02:00
Gabe Black 0c605a5a6c CBFS: Change the signature of cbfs_decompress.
Instead of returning 0 on success and -1 on error, return the decompressed
size of the data on success and 0 on error. The decompressed size is useful
information to have that was being thrown away in that function.

Change-Id: If787201aa61456b1e47feaf3a0071c753fa299a3
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3578
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:10:39 +02:00
Peter Stuge f31eacca62 lenovo/t60 lenovo/x60: Default SEABIOS_PS2_TIMEOUT to 3 seconds
The ThinkPad keyboard controller sometimes needs a while in order
to initialize, so let's ask SeaBIOS to wait for it.

This change ensures that the internal keyboard always functions
correctly on the ThinkPad when coreboot is built with SeaBIOS as
payload.

Change-Id: I562475ec98b0c1f5d0debf6e9b597748a420f068
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/3735
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-15 19:57:01 +02:00
Gerd Hoffmann 05d3f49fc6 qemu: reserve ports
QEMU has a bunch of non-standard virtual devices on various I/O ports.
Allocate resources for them so the coreboot resource management knows
those ports are used.

Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3851
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-15 19:48:17 +02:00
Bruce Griffith 42e11f5a03 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3857
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-15 18:41:44 +02:00
Mike Loptien 9e8690b43f AMD Fam16: Add OSC method to PCI0
The _OSC method is used to tell the OS what capabilities it can
take control over from the firmware.  This method is described
in chapter 6.2.9 of the ACPI spec v3.0.  The method takes 4
inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and
returns a Capabilites Buffer the same size as the input Buffer.
This Buffer is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control Dword.
The OS will request control of certain capabilities and the
firmware must grant or deny control of those features.  We do not
want to have control over anything so let the OS control as much
as it can.

The _OSC method is required for PCIe devices.  During Linux boot,
an error is logged to dmesg if _OSC is not found.

Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3823
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15 18:40:59 +02:00
Mike Loptien 6cf5c8ee65 AMD Fam16: Add secondary bus number to CRES method
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the AMD FCH ACPI code.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'

By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`.  PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge.  However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.

Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3822
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-08-15 18:40:29 +02:00
Mike Loptien ac90d8013a AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.

Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
2013-08-15 18:40:11 +02:00
Andrew Wu 81c70fb142 dmp/vortex86ex: Initialize Reatek ALC262 audio codec
Hook this up into the DMP Vortex86EX. Before under Windows XP
the microphone did not work. With the new logic it does. Now
line-in,line-out and microphone all work.

The verb data table is generated by Realtek.

Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3855
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-13 14:10:45 +02:00
Andrew Wu b7bb70d3de Add a generic Intel HD audio (Azalia) module azalia_device.c
This module uses cim_verb_data to detect and initialize HD audio
codecs.
The module source code is based on southbridge/intel/sch/audio.c and
southbridge/nvidia/mcp55/azalia.c.

Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3844
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-13 10:12:52 +02:00
Andrew Wu 9361daf7fd Fix some wait_for_valid functions return value from 1 to -1.
codec_init expects wait_for_valid returns -1 for timeout, not 1.

Change-Id: I0f2a3ebb1934d0adaf13765434526bbc9efca9a3
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3843
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-08-13 10:11:18 +02:00
Kyösti Mälkki 3be80cce29 usbdebug: Add option for verbose logging of connection
Add option to log changes in USB 2.0 EHCI debug port connection.
For romstage move usbdebug as the last initialised console so one
actually can see these messages.

Init order of consoles in ramstage is undetermined and unchanged.

Change-Id: I3aceec8a93064bd952886839569e9f5beb6c5720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3387
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-10 18:45:34 +02:00
Kyösti Mälkki a9bbdd39e4 usbdebug: Fix AMD cimx/sb700 cimx/sb800
These Kconfig entries were forgotten from the commit
that re-enabled usbdebug for these southbridges.

Change-Id: Ia17f1dd3340408da7c033c2c949404d2636bed44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-10 00:03:55 +02:00
Kyösti Mälkki fd98c65b9d intel/sandybridge intel/bd82x6x: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-09 23:20:52 +02:00
Kimarie Hoot 0cc33da553 ASUS F2A85-M: Split DSDT into common sections (as per Parmer)
Rearranged the F2A85-M DSDT file to match the functionality found
on Parmer.  As with the Parmer implementation, the F2A85-M dsdt.asl
file in the mainboard directory contains only #include references to
the appropriate files.

As with Parmer, some include files have no content but are left as a
template for other platforms and as placeholders for completing the
ACPI implementation for F2A85-M.

Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/3805
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08 05:58:29 +02:00
Kimarie Hoot 436a3753ec AMD Thatcher: Split DSDT into common sections (as per Parmer)
Rearranged the Thatcher DSDT file to match the functionality found
on Parmer.  As with the Parmer implementation, the Thatcher dsdt.asl
file in the mainboard directory contains only #include references to
the appropriate files.

As with Parmer, some include files have no content but are left as a
template for other platforms and as placeholders for completing the
ACPI implementation for Thatcher.

Change-Id: Ie44a32959cc547840914365e872416d4624d33df
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/3804
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08 05:58:15 +02:00
Kyösti Mälkki 0010bf60a6 usbdebug: Support AMD cimx/sb700 cimx/sb800 once again
Support code for sb700 and sb800 existed already, but Kconfig and
compile-time issues prevented from enabling USBDEBUG for boards
with the affected AMD southbridges.

Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-07 19:22:46 +02:00
Kyösti Mälkki 1fd7508121 usbdebug: Use __SIMPLE_DEVICE__ on early enable
With USBDEBUG selected, the file is built for both romstage and
ramstage. For the ramstage build, we need to explicitly use the
simple PCI config operations without devicetree.

Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-07 19:21:48 +02:00
Kyösti Mälkki da940c5835 Make EARLY_CONSOLE optional
This change brings back the possibility to disable console
output while in romstage, like before commit d2f45c65.

For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM
CONSOLE do not work correctly for romstage due the way
cache-as-ram is set up, but might already work for ramstage.

Change-Id: Id8d830e02a18129af419d3b5860866acf315d531
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3846
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-07 19:12:48 +02:00
Paul Menzel cec611a0ea AMD AGESA: Fix comment for `PCIE_DDI_DATA_INITIALIZER`
Copied from a similar commit for Family 10h AGESA [1]

Remove the fourth argument in the comments. Luckily the compiler,
at least gcc, warns about a wrong number of arguments, and therefore
no incorrect code resulted from the wrong documentation.

[1] 07e0f1b AMD AGESA: Fix argument list for `PCIE_DDI_DATA_INITIALIZER` in comments
[2] fc47bfa Revert "AMD f14 vendorcode: Fix warning"

Change-Id: I3806e368a823e4a40d22e99b91bf3598d9ed2f15
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06 19:40:38 +02:00
Bruce Griffith 5697df2a84 AMD AGESA: Add missing breaks to switch statement in one file
This is the same patch as an earlier one applied to family 15 [1].

Static analysis often flags case statements that do not include
a terminating "break;" statement. Eclipse's CODAN is an example
of this.  This changelist modifies amdlib.c to terminate
case statements with "break;".

[1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ...

Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3839
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06 19:21:11 +02:00
Bruce Griffith ee7cd8d85d AMD Olive Hill: Enable WARNINGS_ARE_ERRORS (remove override)
Change-Id: Idf26eb3fb541355bd9553c1897f647738c347eb5
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-06 19:07:27 +02:00
Bruce Griffith 4e08a95d26 AMD Olive Hill: Change SB800 references to Yangtze
Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3815
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06 19:06:48 +02:00
Bruce Griffith effc8d087d AMD Olive Hill: Add HUDSON_LEGACY_FREE flag
Olive Hill does not have a Super I/O or keyboard controller.

Change-Id: I8c1e5d8c20c4a964fe8d98df920b416382a26d9d
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-06 19:06:21 +02:00
Bruce Griffith 2b56e85a50 AMD Olive Hill: Remove default VBIOS vendor/device ID
The VBIOS device ID is set by processor family using the
map_oprom_vendev() function in the northbridge code.  There
is rarely a reason why this should be overridden by the mainboard.
Since Kabini includes a default VBIOS vendor/device ID in the
northbridge Kconfig code, remove the setting from the Olive Hill
mainboard settings.

Change-Id: Icd69155f5b51105d564dd82c89e4bb54a6118a82
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3816
Tested-by: build bot (Jenkins)
2013-08-06 13:53:33 +02:00
Bruce Griffith aea318f35d AMD Kabini: Add "const" modifier to AGESA function parameters
Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA.  This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.

This same change was made for AMD Trinity APUs (Family15tn) [1].

[1] 283ba78 AGESA: Add "const" modifier to function parameters

Change-Id: I2bdd9fc5e027e938de9df0f923b95da934bb48dc
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3837
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-06 07:33:39 +02:00
Paul Menzel abebe80161 AMD SATA: Correct "them implement" to "then implement" in comments
This changelist was cherry-picked from merged community code
for Parmer [1] and the paths modified so that the Parmer
modification is applied against Olive Hill.

[1] 0086162 AMD SATA: Correct _them implement_ ... in comments

Change-Id: I9849e9a75dacfde15331c4200d72343a59036f14
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3841
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-08-05 22:15:49 +02:00
Bruce Griffith 76db07e8c2 AMD Kabini: Add map_oprom() function for Vendor/Device IDs
Change-Id: I14285f0677003fbf8b9b112207af202658807894
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:13:20 +02:00
Bruce Griffith 17933e8bc1 AMD Olive Hill: Enable HDMI audio setting in build options
Change-Id: Ifc180e6fcd594dbedc2512ea5bef283a3ad689d3
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3814
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:09:17 +02:00
Bruce Griffith 5912125dff AMD Olive Hill: Eliminate unnecessary memory copy
Eliminate an unnecessary copy of the DDI descriptor list and
the PCIe port descriptor list.  As descriptor tables, these
tables do not need dynamic updating and should be used from
ROM without runtime copying.

There will be a corresponding patch for AGESA that adds CONST
modifiers to function parameters that are pass-by-reference
"IN" values (read-only pointers).

Change-Id: I7ab78e58041e9247db22d0f97a6f76d45f338db0
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3818
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:09:06 +02:00
Siyuan Wang 80cf7d5956 AMD Olive Hill: Add new AMD mainboard using Kabini processor
Change-Id: I1f252b67c039d28df96e8dfd458a1ca6a7dbc816
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:09:00 +02:00
Bruce Griffith 37a1d6c955 AMD Hudson/Yangtze: Enable support for SATA port multipliers
This patch sets a bit in the Yangtze southbridge to enable
the extra protocol necessary to handle port multiplier chips.
This has been turned on during most of Kabini development
without any notable impact. Olive Hill has an optional daughter
board that incorporates Silicon Image Steel Vines chips.  This
change has been tested with and without the daughter board.  This
change can be regression tested using any Hudson-based motherboard,
although it has no impact on boards with discreet Hudson/Bolton
southbridges.

This was tested for impact on SATA performance in the absence of
a port multiplier using the IOZone benchmarks within the Phoronix
Test Suite.  A SATA 3 hard drive (6.0 Gbps) and an SSD were
connected to the ports on Olive Hill without using the port
multiplier card.  The test results contained more run-to-run
variation within the same configuration than was seen in the
aggregate results comparing the interface with and without the
port multiplier protocol additions.  In other words, the test
had less accuracy than the impact caused by turning on port
multiplier support.

Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3808
Tested-by: build bot (Jenkins)
2013-08-05 22:08:25 +02:00
Siyuan Wang 915714501b AMD Kabini: Modify Hudson southbridge to support new AMD processor
Yangtze uses Hudson AGESA wrapper code but has some changes.
The changes are necessary and have no effects on Hudson.

Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:24:10 +02:00
Siyuan Wang 3e32cc00d1 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also
changed because these two files depend on F16kb northbridge macros

Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:23:34 +02:00
Siyuan Wang 5d7d09c4ab AMD Kabini: Add CPU AGESA wrapper for new AMD processor family
Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:21:29 +02:00
Siyuan Wang affe85fbc8 AMD Kabini: Add AGESA/PI code for new processor family
Change-Id: Icb6f64e2e3cfd678fb4fb4f13f0e4b678d5acc4a
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Nick Dill <nick.dill@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-04 05:40:37 +02:00
Andrew Wu ae8d06969b Remove unnecessary space characters.
Change-Id: I4ed9329126b216eb4ae58355672603ce79a6d4ef
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3847
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-02 14:46:06 +02:00
Kyösti Mälkki 386b3e631f intel/lynxpoint: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3812
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01 16:28:46 +02:00
Kyösti Mälkki ef84401149 Add directive __SIMPLE_DEVICE__
The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.

If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.

Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-01 15:57:11 +02:00
Stefan Reinauer 0aede1185b Drop unused EXTERNAL_MRC_BLOB
The Kconfig variable EXTERNAL_MRC_BLOB is not used.
Drop it.

Change-Id: I3caa5c2b6bcf5d2c13b6987da8ab3987bad0e506
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3829
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-07-31 22:02:41 +02:00
Kyösti Mälkki 71216c9bcd Makefile: Fix adding intel/common
Directory intel/common must be conditionally added in the list
of source directories, as the parent directory southbridge/intel
is unconditionally added even for boards without such device.

Change-Id: I7088bc6db9f56909ffa996aa7eff76cd72e177eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3827
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-30 22:09:21 +02:00
Kyösti Mälkki e23c22dd88 usbdebug: Fix missing include
Change-Id: I74d28c13e6597c56e3b85ccd2b83386b86c200f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3828
Tested-by: build bot (Jenkins)
2013-07-30 08:25:19 +02:00
Kyösti Mälkki 8eaf1e765d cpu/intel/model_67x: Add missing include
The added device.h file was indirectly picked from cpu.h, which will
have this include removed in a follow-up patch.

Change-Id: Ifc0a4800de3b1ef220ab1034934f583be8c527b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3826
Tested-by: build bot (Jenkins)
2013-07-30 08:23:01 +02:00
Nico Huber 696561c2a4 kontron/ktqm77: Update cmos checksum range
Change-Id: I08e56b4a1c56128c6d4beb751979c5b99cdae829
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3790
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:22:41 +02:00
Nico Huber ca4f073f8e ec/kontron/it8516e: Add sanity checks for values from nvram
Change-Id: Ie52d80fc8657064efdcec51c31dc9309fcc28121
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3787
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:22:12 +02:00
Nico Huber 1f9f67864a ec/kontron/it8516e: Comment low-level EC functions
Change-Id: I5f75998356554e08f8c9920e7612494e4710ab15
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3786
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-29 23:21:55 +02:00
Nico Huber 260c33ba56 ec/kontron/it8516e: Remove some unsafe bit shifting
The EC expects the temperature in 64ths degree C. Alter
it8516e_set_fan_temperature() to just export this interface and
make the calculation more obvious.

Change-Id: Ibe241b7909f4c02b30b1e1200a1850d47695a765
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3785
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-29 23:21:11 +02:00