To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
TEST=execute `echo b > /proc/sysrq-trigger` to reboot system
Change-Id: I1a55216c0d5a00bbdb373d931bd50ebe7ca5694f
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure DDI-0 connector type to DP.
BUG=b:187856682
TEST=Build and boot into OS
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ic8af14509b0d246c5c2da6e1a48991384471e69f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
TCSS OC pins have not been correctly configured for volteer.
This patch fills the value from devicetree to correct the OC pins
mapping.
BUG=b:184660529
BRANCH=None
TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and
verify CpuUsb3OverCurrentPin UPDs get set correctly.
Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Initialize and calibrate DRAM in romstage.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.com>
Change-Id: Ib7677baef126ee60bf35da3a4eaf720eaa118a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
I suspect there is additional initialization required to enable the
8042 keyboard controller on the EC. By removing the range we no longer
encounter long 20 second delays when reading the IO ports. Since
depthcharge polls the IO ports it makes it seem like depthcharge locked
up.
BUG=b:182100027
TEST=Boot majolica with depthcharge to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I56a7eb4200e4615e1b4d9f14594d64f93e031a54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Switch to device alias names in devicetree. Remove unnecessary comments
since the names are self-explanatory.
Change-Id: Id486d9bd44bd7ba6a93a5f757af487b211e58efa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
volta will use different wifi SAR from voxel.
Using clamshell mode of fw config to decide to load volta wifi sar.
BUG=b:184820057
TEST=build and verify wifi power as expect.
Cq-Depend: chrome-internal:3824093
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I000aefca63346c70556688f232ca54360b3badef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54051
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIE6 only needed when use the PCIE LTE.
BUG=b:180166408
BRANCH=none
TEST=FM350 can/can't be detected when enable/disable this config.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9dce05fdb6eb956a054d3815ff706b94f0d3fc37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Configure USB HUB_RESET_L gpio to high.
BUG=b:187485847
TEST=Build and boot from USB to OS, check the USB function.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I94e4806c7463030df31f8d819510f9533a622f2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The CBFS mcache size default was eyeballed to what should be "hopefully
enough" for most users, but some recent Chrome OS devices have already
hit the limit. Since most current (and probably all future) x86 chipsets
likely have the CAR space to spare, let's just double the size default
for all supporting chipsets right now so that we hopefully won't run
into these issues again any time soon.
The CBFS_MCACHE_RW_PERCENTAGE default for CHROMEOS was set to 25 under
the assumption that Chrome OS images have historically always had a lot
more files in their RO CBFS than the RW (because l10n assets were only
in RO). Unfortunately, this has recently changed with the introduction
of updateable assets. While hopefully not that many boards will need
these, the whole idea is that you won't know whether you need them yet
at the time the RO image is frozen, and mcache layout parameters cannot
be changed in an RW update. So better to use the normal 50/50 split on
Chrome OS devices going forward so we are prepared for the eventuality
of needing RW assets again.
The RW percentage should really also be menuconfig-controllable, because
this is something the user may want to change on the fly depending on
their payload requirements. Move the option to the vboot Kconfigs
because it also kinda belongs there anyway and this makes it fit in
better in menuconfig. (I haven't made the mcache size
menuconfig-controllable because if anyone needs to increase this, they
can just override the default in the chipset Kconfig for everyone using
that chipset, under the assumption that all boards of that chipset have
the same amount of available CAR space and there's no reason not to use
up the available space. This seems more in line with how this would work
on non-x86 platforms that define this directly in their memlayout.ld.)
Also add explicit warnings to both options that they mustn't be changed
in an RW update to an older RO image.
BUG=b:187561710
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I046ae18c9db9a5d682384edde303c07e0be9d790
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable DPTF functionality for Alder Lake based brya
BRANCH=None
BUG=b:188028732
TEST=Built and tested on brya board
Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
gcc 11.1 complains when we're passing a type* into a function that was
declared to get a type[], even if the ABI has identical parameter
passing for both.
To prepare for newer compilers, adapt to this added constraint.
Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Select touchscreen(s) based on touchscreen source provisioned in SSFC of CBI (higher 32 bits of FW_CONFIG in coreboot).
The reason is to avoid to enable multiple touchscreen ICs with the same slave address.
BUG=b:186609348
TEST=build and boot to OS.
Change-Id: I087ea677a8865fc8c5b3f7c9773bd7f97924dbb3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Hermes can be used with either CSME or SPS firmware. However, the SPS
(Server Platform Services) firmware does not support ACPI S3 and S4
sleep states, and coreboot should not report S3 and S4 as supported.
Add a Kconfig option to be selected when building coreboot to use with
SPS firmware, which allows disabling ACPI S3 and S4 sleep state support.
Change-Id: I9d0fa8530e198e86415f92da6719d2fb0d2401ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Remove TSR2 and use DPTF parameters from internal thermal team.
BUG=b:175938681
TEST=build and boot to OS.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If0ec1ec48b8971efe87f1f8d10332a9c16352122
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
In order to support wake on WLAN events, configure the wake resource.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that WiFi power resource
is added to SSDT.
Device (\_SB.PCI0.GP20.WF00)
{
Name (_UID, 0x38B82CBC) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x0000000000000000) // _ADR: Address
}
Scope (\_SB.PCI0.GP20.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x08,
0x03
})
}
Change-Id: Ic238d9606aea20c058e9b47093693f10b14e6288
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The 448KB size of the GBB is larger than is needed, so adjust it down
to the minimum size needed.
BUG=b:186761897
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7a24945cd9ecc8872871f57b09ca71fc40e92473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add audio codec module RT5682 in project and define GPIO_137 in the
override_table for SSFC framework to adjust IRQ configuration.
BUG=b:182221327
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682I or DA7219 then check whether device tree is updated correspondingly by disabling unselected one.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I202f71f57ad2db84fb90b52f9ffd7a1fd05494a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Create the chronicler variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:187318819
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_CHRONICLER
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iebfea87b7c4cfc2a83e88a6c479a0842774ae018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.
BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board
Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Probe the fw_config for RT1015 speaker amplifier operation mode and
enable it accordingly in the device tree.
BUG=b:180570923
BRANCH=dedede
TEST=ALC1015Q-VB drive speaker OK
Change-Id: I756bfa6f604ed320de9a515821979aa95c869ebf
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add support for GPIO and SPD driver for pirika
BUG=b:184157747
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: Id367a83b04aad62b7deabae99b3f91905a2fc46c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update LTE USB port configuration at run-time after probing the firmware
config. By default the concerned USB port takes the Type-A port
configuration.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight
Change-Id: I5ad5a1670adef54075923cf912fb41a1ce776155
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
This callback is required to update the devicetree config at run-time
after probing the firmware config.
BUG=b:186380807
BRANCH=dedede
TEST=Build and boot to OS in metaknight.
Change-Id: I857211bfc4beb36ab225f3786c1707336a34aae9
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Remove a blank line and correct the indentation of another line.
Change-Id: Id66f0a847720713c1d3445ac70a9e075228dfe88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54017
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No board defines this macro. In preparation to drop OptionsIds.h files
from mainboards, remove commented-out references to `IDS_DEBUG_PORT`.
Change-Id: I67a10d863aeea9e1b91c38aa02d19106b7b97659
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Ibc2876a5a8419ec4fa5a793bb996f5c14d989bac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: I9cd9fa0dc25b1143f8b4c1f20beffba638437398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This macro is not used anywhere in AGESA. Remove all references.
Change-Id: Icae0ecae77a20e1568440e3191a29db33b5581d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The values were copied from Foxconn D41S, which uses a different codec.
Adjust the codec config as per the settings dumped from vendor firmware.
Change-Id: If6a4c41b5d424adb23ebef402d2d2ad21269fe25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable Display Controller Engine Audio endpoint to enable HDMI audio.
BUG=b:186479763
TEST=Build and boot to OS in guybrush.
Change-Id: I5e35440e8e70ee125d37c7ac30c9219ec69c7c6e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Everybody wants a stylish stylus. Enable the power system to it.
BUG=b:186267293
TEST=connect multimeter to PP5000_PEN and see it go from 0 to 1. MAGIC!
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: I11d05c118ec9451d26136c320f3650c489e02c59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common
folder and rename to rtc_mt6359p.c.
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I73ea90512228a659657f2019249e7142c673e68e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PIC IRQs are required so we can correctly set up the PCI_INT
registers. This only matters when booting in PIC mode. We don't need to
set the IO-APIC registers since the linux kernel will auto-assign those
to reduce conflicts.
BUG=b:184766519
TEST=Boot guybrush with `pci=nomsi,noacpi amd_iommu=off noapic` and
verify xhci and graphics continue to work.
$ cat /proc/interrupts
12: 285064 XT-PIC nvme0q0, nvme0q1, rtw88_pci
13: 100000 XT-PIC xhci-hcd:usb1
14: 4032 XT-PIC amdgpu, xhci-hcd:usb3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1d66ccd08a86a64242dbc909c57ff9685828f61f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52915
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mcache is overflowed in the latest build. In order
to fix the mcache overflow, we increase the mcache size
to 0x4000 and adjust the percentage to 50% for the ro/rw
mcache. This change is for all of the volteer variants
as we see many of the volteer variants which use the
latest bios having the mcache overflow issue.
BUG=b:187095474, b:187095765, b:187234881, b:162052593
TEST=no mcache overflow in the bios log
Change-Id: If9552bc9fa5d36b1ca662c9da030ae7b137b60a8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add backlight support in sn65dsi86bridge through the AUX channel using
eDP DPCD registers, which is needed on the GOOGLE_HOMESTAR board.
Change-Id: Ie700080f1feabe2d3397c38088a64cff27bfbe55
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52663
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace `3` with `SaGv_Enabled`, which has the same value.
Change-Id: I05cfddfefc45ba5bfb0e684445a6d8e02d7865e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Create the volet variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:186334008
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOLET
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ic6ca9a78494e3819b0fb39c0bcc70fed95c2c589
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Bank interleaving does not work on this platform, disable it.
AmdInitPost returns success thanks to this setting.
TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD support to elemi for K4AAG165WB-BCWE
BUG=b:187379245
TEST=FW_NAME=elemi emerge-volteer coreboot chromeos-wqbootimage
Change-Id: I839447a9e7c7b6558b2d0877c67dc9cf89ee792a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Mancomb uses DDR4 SODIMMs, but the default cezanne configuration is for
the LPDDR4 version. This changes to use SODIMMS.
Further changes may be needed for platform customization, so I put the
config file in variants/baseboard instead of the root mancomb directory.
BUG=b:187094481
TEST=Build only
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icc4dc8aec2053cb177765f57e57cac7a099508fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DISABLE_KEYBOARD_RESET_PIN - This pin goes to a test point and is not
used for the reset.
DRIVERS_UART_ACPI - Add the UART ACPI code
FW_CONFIG - Mancomb uses the firmware config interface
PSP_DISABLE_POSTCODES - The PSP is not yet initializing eSPI correctly
to send post codes to the EC, so disable them for now.
BUG=None
Test=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I39efcc8d1e0fb1e7ac0b0541a49db0ac0ee56481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
This same patch was added for Guybrush at CB:52673
BUG=b:186045622, b:181139095
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac86d2ef5bdd21fbb0a0d4e235efe4fe621023b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52948
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using the push-pull alert was causing leakages when in S0i3. This is
because the EC drives ALERT#, so when the AP enters S0i3, the extra
current leaks into the SoC and ends up turning on the power regulators.
By using in-band ALERT#, the EC no longer drives this pin high, thus
fixing the leak. We could also have used an open drain alert, but the
rise time is less than ideal.
BUG=b:187122344, b:186135022
TEST=Measure S0i3 power on guybrush and validate it's no longer high.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6de771aeda8feca062652f0ea9eb57d31cb68562
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SPI flash is not emulated on these boards.
Change-Id: If29a87441cb26e53c9814ed10ddcfe14752c3965
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52791
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CMOS option system does not support negative integers. Thus, retype
and rename the option API functions to reflect this.
Change-Id: Id3480e5cfc0ec90674def7ef0919e0b7ac5b19b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
BUG=b:186380809
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I0975a8b64452c3f636e6c5937c6918518ec5b4e9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
TGL boards using the Type-C subsystem for USB Type-C ports without a
retimer attached may require a DC bias on the aux lines for certain
modes to work. This patch adds native coreboot support for programming
the IOM to handle this DC bias via a simple devicetree
setting. Previously a UPD was required to tell the FSP which GPIOs were
used for the pullup and pulldown biases, but the API for this UPD was
effectively undocumented.
BUG=b:174116646
TEST=Verified on volteer2 that a Type-C flash drive is enumerated
succesfully on all ports. Verified all major power flows (boot, reboot,
powerdown and S0ix/suspend) still work as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I70e36a41e760f4a435511c147cc5744a77dbccc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the pirika variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:184157747
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_PIRIKA
Signed-off-by: kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
Change-Id: I57bf33deeadacc88800f9ce1d3d54385ba56c798
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52626
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pen Detect GPIO is exported through GPIO keys driver to the kernel so
that stylus tools is popped on pen eject event. Hence enable the GPIO
keys driver and configure the devicetree.
BUG=b:186011392
TEST=Build and boot to OS in guybrush. Ensure that PRP0001 device is
added to the ACPI SSDT table. Ensure that the Pen Eject events are
detected.
Event: time 1620159356.243180, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1620159356.243180, -------------- SYN_REPORT ------------
Event: time 1620159356.735316, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Ensure that when the device is suspended, it wake on Pen Eject event and
does not wake on Pen Insert event.
Change-Id: I4d2aa29c0f1839c563b40734527a687a5618ba5c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=Wake system from S0i3 with EC and see GPE 3 increment.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If7f9d2c13503c01fb9d834c436dac723f2c3b24c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS on shadowmountain. Ensure that the
EC Software Sync is complete.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Configure GPP_A20 as PAD_CFG_GPI_IRQ_WAKE to enable interrupt and wake routes for touchscreen device.
BUG=b:186070097
BRANCH=puff
TEST=Build and make sure TS works to wakeup suspend/resume.
Change-Id: I2bbaab56924849a22a4d05ce53bf5bdcf00265dd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only 4 mainboards selected to use the option table.
Use the same default on all boards.
Change-Id: Ia9ef88d5158a2b43f843c26b5b366a899dad8788
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz
BUG=b:179170193
BRANCH=firmware-zork-13434.B
TEST=verified that the resolution of the display is 4K 30Hz
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Using PAD_WAKE is actually wrong. The wake bits are only supposed to be
set when using the GPIO controller to wake the system. coreboot's
current architecture relies on using GPEs to wake the system.
BUG=b:186011392
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib956fc299fe21cd7ea0b465cbdc5c8da830a668d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.
BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform
Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All the boards in the patch have a constraint for the I2C bus to operate
on 100 kHz. Provide dedicated values for rise time, fall time and data
hold time on mainboard level to get a proper timing which takes the bus
load into account. Giving these values the driver computes the needed
timings correctly.
TEST=Measure I2C frequency on all boards while coreboot accesses
external RTC and make sure it is 100 kHz.
Change-Id: Iab634190bda5fa2a4fdf2ebaa1e45ac897d84deb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52721
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Default VBT supports only integrated Display port. Magister supports a
HDMI port and hence support a separate VBT for Magister.
BUG=b:180666608
BRANCH=dedede
TEST=Build and boot to OS.
Cq-Depend: chrome-internal:3661227
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I52c10452887312959f68cfc4e25d5897dae388f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51279
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mancomb will have the boot flash on a daughterboard, so the SPI speeds
need to be low for now.
BUG=b:182211161
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Icacb68d65fb414197d7b8d45799527d8d2568dc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Guybrush is pretty definitely alive, so this can be removed, as the
TODO line said.
BUG=180721202
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f89f3e6f780c2da2136a838950ef2bcebc4c3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There is no lid switch in mancomb so remove it.
Will replace the lid switch with a fake gpio in depthcharge.
BUG=b:182211161
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ifd0fcec9557bf7ebad64ce9342d3b50eb511522b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The usage of external oscillator has got nothing to do with Audio
Co-processor (ACP). Hence move it out of common config and put it into
the SoC config where it is being used.
BUG=None
TEST=Build Dalboz and Vilboz mainboards.
Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Follow the FP6 IRM(#56328) to set the stapm parameter
and allow other mancomb variants boards can customize those parameters.
BUG=b:1181157669
TEST=build.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ib3ed76e5212a5a8b5fb4fcc3d6884ceff82377b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The boolean is stored in ChromeOS NVS, not GNVS.
Change-Id: I5c424a052d484228a456f8f0ad4fb0bed3165e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Brya uses CBI to store dram part number. So enable the config.
BUG=b:186571840
BRANCH=none
TEST=dmidecode -t 17 can show the dram part number.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1b4fc4da31d8964763c3e671d84be71996fa5e2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.
BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to SED team provided ELAN touch screen SPEC. IRQ trigger
method need set with level trigger, that modify IRQ trigger to level
from edge.
BUG=b:174972088
TEST=Build FW and boot to OS and check with test result.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9237d9aad6166a5754afe464ce8453129a58d283
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
guybrush and mancomb don't configure any GPIO as PAD_SMI. Since
mainboard_smi_gpi will only get called for a GEVENT that will cause a
non-SCI SMI, this isn't expected to be called. For the unexpected and
very unlikely case that it still does get called, put a printk into
mainboard_smi_gpi to see what is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6e3348ecc078932bf6cf5b0830b4b034d274bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52360
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will
only get called for a GEVENT that will cause a non-SCI SMI, this isn't
expected to be called. For the unexpected and very unlikely case that it
still does get called, put a printk into mainboard_smi_gpi to see what
is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure Audio Co-processor(ACP) to operate in I2S TDM mode. Also fix
the scope in which ACP is defined in the devicetree.
BUG=b:182960979
TEST=Build and boot to OS in Guybrush. Ensure that the ACPD device is
enabled in the appropriate scope in SSDT.
Change-Id: Ic90fd82e5c34a9feb9a80c4538a45e7c2fb91add
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
All guybrush boards should have system_configuration set to 2, so
put this in the main devicetree.
BUG=b:185209734
TEST=Build & Boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce2acb3b4ed51aa9a0aa379ed125f0b04f04d31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
From ANX7625 spec, the delay between powering on power supplies and GPIO
should be larger than 10ms. Since it takes about 4ms for the previous
GPIO EN_PP3300_EDP_DX to be pulled up, increase the delay from 2ms to
14ms.
BUG=b:157716104
TEST=emerge-asurada coreboot
BRANCH=asurada
Change-Id: If73747bdaec5ac069b048920d27e27178bc3cedc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Follow L850GL spec to adjust power sequence. RST need to drive low
before power on then drive to high.
SPEC:FIBOCOM_L850-GL Hardware User Manual_V1.0.8
BUG=b:186374631
TEST=WWAN is detected by lsusb.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I13357677bb1ab185abf1d4c915a762a9d6894312
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This changes adds the EC_HOST_EVENT_USB_MUX to be dark resume source.
BUG=b:183140386
TEST=In S0ix, remove DP dongle, system does dark resume. AP and EC
synchronized. AP got port partner disconnection.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I53bd4fee21e2e2d1f16f558ab0341a50ef9a0e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52716
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always print the chosen fan mode, not only when get_int_option() returns
the fallback value. Callers of get_int_option() should not try to handle
option-related errors, and simply proceed using the fallback value.
This change is needed to update the option API to use unsigned integers.
The CMOS option system does not support negative numbers.
Change-Id: Ic8adbe557b48a46f785d82fddb16383678705e87
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen
and control TOUCH_RPT_EN pin to keep low.
BUG=b:176253069
TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Brya uses CNVi WiFi module, PCIE setting is not required.
TEST=WiFi is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
AMD GPIO driver will not load if IRQ is not set. As a consequence,
it does not clear the interrupt when waking from S0i3.
BUG=178728116
TEST=Perform 2 S0i3 cycles, confirming second cycle does not return
instantly due to first interrupt not being cleared.
Change-Id: I3072263e8e68f939a47ed4125444c60133087824
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Drop Vref verbs from the baseboard table as it's not required for
Rev. 3 and earlier.
Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This change fixes two problems:
1) We had the enum values for .direction and .level swapped. The naming
is very confusing...
2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low
event that is only cleared by reading the eSPI status register 0x9C.
Cezanne has added a new event source that directly exposes the SCI bit.
This is the correct event source to use for EC SCI.
BUG=b:186045622, b:181139095
TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I764b9ec202376d5124331a320767cbf79371dc07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2"
Because baseboard modify slow slew rate setting to "SLEW_FASE_8"
for all project, but Lindar and Lillipup is using "SLEW_FAST_2",
so this setting need to roll back.
BUG=b:186140230
TEST=Build FW and boot to OS checking with CPU log.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
https://tech-docs.system76.com/models/oryp6/README.html
Tested with TianoCore (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe
- M.2 SATA
- MicroSD card slot
- All USB ports
- Integrated graphics using Intel GOP driver
- Webcam
- Ethernet
- Internal microphone
- Combined headphone + mic 3.5mm jack
- Combined microphone + S/PDIF 3.5mm jack
- Booting to Ubuntu Linux 20.10 and Windows 10
- Flashing with flashrom
Not working:
- S3 suspend/resume: System hangs on wake from S3
- Discrete/Hybrid graphics: Requires a new driver
- Internal speakers: Enabled in separate patch
Not tested:
- Thunderbolt functionality
- S/PDIF output
Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux kernel now uses S5 for reboot, which makes reboot fail if EC
SLPT bit is set.
Tested on HP EliteBook 2560p, reboot and S3 resume work after this
change.
Change-Id: I9b3ea737f85cc4045714263657bcdaac08f3a20d
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
No code in coreboot uses this option, so it might as well be dropped.
Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove CMOS options that are not read anywhere in the code. They may
have been used in the native AMD platform code, or got copied around
from board to board and never did anything to begin with.
Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To train PCIe devices, the devices need to be enabled and taken out of
reset. This patch does the bare minimum needed to train PCIe. It is
not intended to handle timings, which will be addressed later.
Copy the enables for WLAN into early GPIO Init so that they're
enabled before FSP-M runs and trains the PCIe busses.
Again, this patch is the minimum to let the FSP train the PCIe busses.
BUG=b:182202136
TEST=Boot guybrush from NVME.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add dynamic fan table mechanism for Lindar and Lillipup.
Create different fan tables that provided from thermal team.
BUG=b:185308432
TEST=Build FW and boot to OS modify CBI test with DPTF tool.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
BUG=b:185939089
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Enable GL9755 SD card reader.
BUG=b:185397257
TEST=SD card is functional in the OS.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The `ethernet1` and `ethernet2` options are not used in this board.
Change-Id: I24c8f662d094fb77ed1425ec13486ffa9c3dff07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52631
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace spaces with tabs for consistency with other mainboards.
Change-Id: Ia4042ecf7c62490b0a50bc42d5ddddd5872bf036
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52633
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace spaces with tabs for consistency with other mainboards.
Change-Id: Ib0d5bf566148cc4890d5ba010314d11b7a4f8c2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52634
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, it fails to dump the nvme data by test command.
It reports the following error:
cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out
So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem.
BUG=b:177393430
TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin
2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log
3. cat ov8856_eeprom_dump.log
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: ShawnX Tu <shawnx.tu@intel.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The next guybrush build uses 2 new LPDDR4X memory chips:
- Micro MT53E1G32D2NP-046 WT:B
- Hynix H9HCNNNBKMMLXR-NEE
The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X
list since the last time guybrush was updated, so that's brought into
the guybrush SPD directory as lp4x-spd-10.hex, but it's not used.
BUG=b:186027256
TEST=Build only
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add cs42l42 codec support in fleex.
BUG=b:184103445
TEST=boot to check cs42l42 is functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Remove the unneeded pull up, as leaving them unterminated disconnects
them from internal logic.
Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO where no
termination is used.
Change-Id: Ia85ea39d46d7d9584b94726a7d601ca06826b1d1
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and specify the srcclk pin and reset GPIO.
TEST=Tested on shadowmountain platform to ensure the system can enter the
S0ix state and suspend/resume is stable
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DPTF functionality for Alder Lake based adlrvp board
BRANCH=None
BUG=None
TEST=Built and tested on adlrvp board
Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry
since it is not used anymore.
BUG=none
TEST=Check lsusb to see if BT enumerated.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the unneeded pull up, as leaving them unterminated disconnects
them from internal logic.
Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO, as none configure
termination.
Change-Id: I28549a89a885598ba2d5111a9974356562a03cde
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With this change, the type-unsafe {get,set}_option() API functions are
no longer used directly. The old API gets dropped in a follow-up.
Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes changes to enable display and DSP audio UPD.
BUG=b:181219097,b:183482000
TEST=Audio sound card is detected and listed by the linux kernel.
Audio playback and capture is working on the Brya.
Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.
TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.
Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.
This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.
BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.
Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch has changes to support multiple cameras modules, based on
the value set in the SSFC_CONFIG.
BUG=b:176065425
TEST=Tested the changes with magolor 5MP and 8MP camera.
Change-Id: I764abf70bacbe61452e7b0fd59c1b375227b5748
Signed-off-by: Shawn Tu <shawnx.tu@intel.com>
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for
cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect
PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus
errors on guybrush.
BUG=b:185514903, b:184356693
TEST=Boot guybrush, observe no port80 codes from PSP
Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The slot ID can be passed in from the function caller but
parsing slot ID from devicetree is not yet supported and
would still be 0.
Add Slot ID in SMBIOS type 9 for Delta Lake.
Tested=Execute "dmidecode -t 9" to verify.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore,
default to 512 in the SoC Kconfig and drop it from related mainboard
Kconfigs.
Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on asus/p8z77-m_pro's, with NMI set to disabled by default, and
all available gfx_uma_size values.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I9582747b3d4782f4b02ddecaab636bdbb1b6f530
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52344
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting.
BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.
Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.
Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).
This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.
Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U.
BUG=b:184126265
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.
Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add control charging current from TSR0 and correct charger_perf table value.
BUG=b:179067801
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Edward Doan <edoan@google.com>
Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather
than CONFIG_CHROMEOS.
Test: build/boot google/{beltino,jecht} with RO_VPD propagated from
stock firmware, verify MAC address set correctly.
Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and
DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to
probe daughter-board to avoid USB device cannot recognize correctly.
BUG=b:184809456
TEST=build and verify USB device can recognize correctly
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`devicetree.cb` is the default value for the Kconfig DEVICETREE
setting. Drop redundant configurations.
Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `chipset_lockdown` option defaults to `CHIPSET_LOCKDOWN_FSP` if
omitted. As most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`,
choose it here as well for consistency.
Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Fix board ID (HSI) read from BMC:
* R02 and R03 have an HSI of 2.
* R04 has an HSI of 3.
Change-Id: I987b2dd848c48e3562bcc07270c958cde3c5a962
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51920
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option is not mainboard-specific, and should be user-visible.
Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
To make the L140CU able to be selected by other OEMs, use
BOARD_CLEVO_L140CU_BASE for OEM independent options.
BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any
OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the
baseboard.
Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to
make clear that this option represents the baseboard.
Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Memory init config is board specific. Thus, move it to variant level and
hook up variant romstage.c.
Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Hook up FSP-M configuration on mainboard level instead of variant level
being able to do common configuration there.
Also, hook up variant romstage.c on mainboard level for variant
specific configurations.
Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to
set it here.
Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 1e36dc078e. With EFS2
already enabled in EC, enabling early EC sync is not required. Also a
workaround has been added in payload to address any boot issues.
BUG=b:185277224
TEST=Build and boot to OS in Guybrush in both normal and recovery mode.
Cq-Depend: chromium:2832032
Change-Id: I921dc5c814e5187dce283eeff43075b59885723a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS
is selected, so non-ChromeOS targets use the default x86 FMAP.
Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The
concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has
a voltage rating of 3.3 V. The schematics has been updated to bridge the
gap. So enable the speaker amplifier by default and add a gpio override
table to disable the speakers before board version 2.
Also update the codec ACPI HID name for the kernel machine driver to
probe the codec successfully.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state
is high.
Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable AMD I2S machine driver and configure the devicetree with HID
information so that the machine driver ACPI objects can be passed to the
kernel.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for
machine driver is populated.
Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.
This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.
This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update GPIO config based on review of latest schematics:
- LAN/WLAN reset lines are NC
- SDIO lines configured via GPP_G0-G7
- DMIC lines are wired directly to codec, not PCH, so GPP_D17-20
are set to NC
- Pads GPP_H0-H3 are configured for I2S2
- Pads GPP_H7-H9 are straps for board revision, so treated as GPI
- CPU_C10_GATE# is NC
- PWRBTN# does not need an internal pull-up
- GPP_C20-23 are configured for M.2 UART
- SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups
- GPP_C6/C7 set to I2C1 for future use
- GPP_E15 changed from SCI to SMI, edge triggered
Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When a pad is configured as NC, it is set as a GPI with both
TX and RX disabled, and as the pad is internally disconnected,
no pull up or pull down is needed.
Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the SATA device to the device tree so it may be found
when trying to write SATA registers. Otherwise, it fails
on "requests hidden 00:17.0 PCI: dev is NULL!"
Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
MPTS is currently not executed by the AML interpreter.
Use Method (\\_SB.MPTS) instead of
Scope (\\_SB)
Method (MPTS)
ScopeEnd
Tested on Prodrive Hermes. MPTS is now executed at S5.
Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Add ACPI code to enable the backlight when we enter the OS.
BUG=b:184198808
TEST=Backlight enabled in the OS
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
This pad is connected to INTP_OUT of the Type-C PD controller. Correct
the comment. Also remove the unneeded pull-up.
Checked with schematics.
Change-Id: I33a5f177affc3f13d091a85073499b7283f54ada
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CBFS size equals flash size, leaving no space for descriptor and ME.
Reduce CBFS_SIZE.
BUG = N/A
TEST = Build and boot Portwell M107
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: Ida5a248edf4f602c4a106ae29d706e732ef8454f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
