The name GENERIC_SPD_BIN doesn't reflect anymore what that config is
used for, so rename it to HAVE_SPD_BIN_IN_CBFS.
Change-Id: I4004c48da205949e05101039abd4cf32666787df
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.
Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.
All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.
Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.
Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.
Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.
I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.
Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.
I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.
Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.
Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.
I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.
Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE
so their FADT preffered_pm_profile would change from PM_MOBILE without
the added overrides here.
Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the use of C_ENV_BOOTBLOCK_SIZE. Verify the bootblock by reading
the CBFS file instead of directly accessing the datablock.
BUG=None
BRANCH=None
TEST=tested on facebook fbg1701
Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41694
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't directly include <soc/gpio.h>. All code using GPIO features
should always and only include <gpio.h>, which should indirectly
include the SoC-specific <soc/gpio.h>.
Change-Id: Id2663398b9f069ab1f60d63016ea7aa080f66d20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Update monolith root port settings to match those of the original BIOS.
MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced
Error reporting are enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The current flash layout requires changes to the descriptor area to
create the 9MB BIOS region.
Add fmd files that allow switching to coreboot by only replacing the
BIOS region.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I2b003018e245693934202505d7e3891c2f545e6c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I311c62e8321afa43fdb442e10158973ecdcca793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update the icc_max for the GT-Sliced VR domain according to the
hardware design.
BUG=N/A
TEST=build
Change-Id: Ib9f7d77d144a282214e6bda8a4e836873c395487
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39804
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 2nd COM port's base address defaults to 0x2f8. Current software
for this system expects the port at 0x3e8.
Configure COMB to use 0x3e8 instead of 0x2f8.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ibb462bad5f0594e0b5c8dea6e02cd42d58d999ab
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The serial number and UUID returned by DMI are retrieved from VPD.
The solution supports a 16 character "serial_number" and a 36 character
"UUID" string.
BUG=N/A
TEST=tested on monolith
Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable use of VPD for monolith. This will be used to store the UUID and
Serial number.
BUG=N/A
TEST=build
Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The monolith board doesn't support the S3 and S4 states because of the
watchdog and failover mechanisms.
Remove S3 and S4 from the available sleepstates.
BUG=N/A
TEST=build
Change-Id: I01f67d8bb3f9e45caef748caca91eeb6859d7393
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=tested using fwts on a facebook monolith.
Found-by: fwts 19.12.00
Change-Id: I25a842539ee2e8febc8a1ae88843a71ccb4ee68e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38133
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mainboard ASL code contained a power button definition. This is not
required as the system uses the standard ACPI power button.
Remove the PWRB device from ASL.
BUG=N/A
TEST=build
Found-by: fwts 19.12.00
Change-Id: I4fac1411fd99475551bc970818759649f80b3f0e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38134
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Read the CPU temperature from the EC.
For this board the EC support is limited to reading the CPU temperature
sensor at this moment. Events are not supported.
BUG=N/A
TEST=tested on facebook monolith using acpidbg
The TSR0._TMP method is returning the correct values.
Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies
according to the information in the schematic. The IccMax for these
supplies is lower than the standard supported by the SoC.
BUG=N/A
TEST=build
Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Due to build rules, dummy acpi_tables source files were added in many
mainboards. With commit 1e83e5c61a
("src/arch/x86: Build mainboard acpi_tables source if present"),
the build system will build mainboard acpi_tables only if present. Remove
the dummy/empty/blank acpi_tables source files.
BUG=None
TEST=Build test with some google mainboards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The SDIO device is disabled so remove it from the devicetree.
BUG=N/A
TEST=build
Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HDA controller was disabled because no codec exists on the board.
However, this also disabled audio over HDMI.
To correct this, enable Azalia and the HDA controller in the devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is
expected by some parts of the code.
Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Even if they were corrected, they just rephrase the code.
Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The MIC1 NID is configured incorrectly because of a typo. The value is 7
digits instead of 8. This is corrected by this patch.
No issues are known because of this (the MIC is not connected).
BUG=N/A
TEST=build
Change-Id: Ia12f3be7d7262829cce3400a8535a33ea1c54b78
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now RCOMP_TARGET_PARAMS is defined and used once in the definition of
the RcompTarget structure. All other structures in these functions use a
fixed value.
Replace RCOMP_TARGET_PARAMS with fixed value.
BUG=N/A
TEST=build
Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an fmd file with a layout that allows configuring the system for
measured boot without enabling verified boot.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cbfstool doesn't support % tag yet while this was in the fmd.
Revert the fmd changes that use the % tag.
BUG=N/A
TEST=build
Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Defines in onboard.h are moved to other files.
Remove this empty and unused file.
BUG=N/A
TEST=build
Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Items in onboard.h are related to verified or measured boot.
Move the items to board_verified_boot.h and remove onboard.h.
BUG=N/A
TEST=build
Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37614
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SDCARD_CD is defined in onboard.h but required in ASL only, move this
define to dsdt.asl.
Removed the onboard.h file from the ASL files that don use it.
BUG=N/A
TEST=build
Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ITE8258_CMD_PORT is used in com_init.c only.
Replace ITE8258_CMD_PORT by fixed value in the c file.
ITE8258_DATA_PORT is removed as this isn't used.
BUG=N/A
TEST=build
Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The board is booting Linux and has been briefly tested.
SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.
BUG=N/A
TEST=tested on Facebook Monolith
Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Some guarding is not needed because the linker drops the code,
other guarding is not needed because all platforms using the code now
have C_ENVIRONMENT_BOOTBLOCK.
Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.
Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add IFD and ME binary to generate complete SPI image.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: I9370bf9f2bba8887988bc6484524f6cf53bed8db
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34448
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the logo.bmp file from the verify list when FSP1_1_DISPLAY_LOGO
is not set.
BUG=N/A
TEST=build
Change-Id: I87eac0b3cbe9450d5623b5331d8de096f140b595
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36853
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changed the order of the verify lists and updated the comments to
reflect the order of execution. This makes the list easier to understand
and maintain.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Ia656fbf07e5d42bafd328eaba69b660e5a1e4f1a
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36817
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change from hardcoded "fallback/*" to using CONFIG_CBFS_PREFIX.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Ie728d01ebb93edd88516e91528ecaaa3f139b7a9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The public key should only be validated if the manifest is signed.
BUG=N/A
TEST=testedd on fbg1701
Change-Id: I703ed442e0b1926859f593ce9ca84133013224ea
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The postcar_verify_list should contain the items that should be verified
before the postcar stage is started.
BUG=N/A
TEST=build
Change-Id: I328858e4803873fed6d47313def5e7b9a434e8ad
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The bootblock measurement was handled using the romstage_verify_list()
and the public_key in the mb_log_list. This is confusing as these are
both read-only items that should be handled in the same way.
Both will be handled in the romstage_verify_list().
BUG=N/A
TEST=tested on fbg1701
Change-Id: If05198deec85188f39a221a8b755798755afa5bb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Support to display a logo using FSP 1.1 currently resides in facebook fbg1701
mainboard.
The related support is moved to drivers/intel/fsp1_1 and used by the
Facebook fbg1701 mainboard. The storage for the uncompressed logo
is changed. We don't use .bss any longer as the logo doesn't need to be
available at runtime.
BUG=N/A
TEST=booting Facebook fbg1701
Change-Id: I276e6e14fc87d0b95fe5fdf7b617afd26769de79
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The FSP loops through microcode updates and at the end checks if
the microcode revision is not zero. Since we update the microcode
before loading FSP, this is the case and a fake microcode can be
passed to the FSP.
The advantage is that the Kconfig symbols to specify the location and
the size of the microcode blob can be dropped.
Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Align the eltan mboot support with coreboot tpm support to limit the amount of custom code.
We now only support SHA256 pcrs, only single a single digest will be handled in a call.
The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is
selected.
BUG=N/A
TEST=tested on fbg1701
Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Allow the user to enable and disable the logo from
make menuconfig. The file can be selected as well.
BUG=N/A
TEST=build
Change-Id: I630a9d14308131c180adaaa9e1fa5e6e11c3c61c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The public key was not verified during the verified boot operation.
This is now added. The items in the manifest are now fixed at 12 as
we always have the postcar stage.
BUG=N/A
TEST=tested on facebook fbg1701
Change-Id: I85fd391294db0ea796001720c2509f797be5aedf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36504
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig contained some items that were only intended to
set a default and that now were displayed in two locations
in the menuconfig.
BUG=N/A
TEST=build
Change-Id: If5d9c993c03a0e901fd6c2a2107a6be6b94d063b
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36481
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The facebook fbg1701 never contains Intel wifi functionality
so this can be disabled.
BUG=N/A
TEST=tested on facebook fbg1701
Change-Id: Iab7dd760020cb7a9f7fea24812afb19bf5e62183
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Renamed mainboard.h to logo.h as it only contains
logo related items.
BUG=N/A
TEST=tested on fbg1701
Change-Id: I921ae914c13d93057d5498d8262db2c455b97eaf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
FBG-1701 revision 1.3 will use Kingston onboard memory.
Add Kingston SPD file.
When Samsung memory configuration is disabled use
cpld_read_pcb_version() for using correct SPD data.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701 revision 1.3
Change-Id: I2e1d1b933d5a49a7005685ed530c882429019027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35792
Reviewed-by: Wim Vervoorn
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all code involving the cpld to a single file.
Rename mainboard_read_pcb_version() to cpld_read_pcb_version().
BUG=N/A
TEST=tested on fbg1701 board
Change-Id: I9ee9a2c605e8b63baa7d64af92f45aa07e0d9d9e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36095
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The vendorcode/eltan mboot and verified boot options only build if a
few other Kconfig options are defined.
Change-Id: Ie333d2fbf294e23ec01df06ee551e2d09541c744
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35954
Reviewed-by: Wim Vervoorn
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ONBOARD_MICRON_MEM and ONBOARD_SAMSUNG_MEM are available.
These are used to determine if Samsung or Micron onboard memory is
assembled. This can not detected run-time.
Choice is replaced by one config.
Only oldest HW revision contains Samsung module, so set
CONFIG_ONBOARD_SAMSUNG memory to default No.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701
Change-Id: Id65e92bd4b8d4fe3a6b87dec9bf77e3a62e1be96
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
No support is available in mainboard.
Add support to mainboard:
- Add mb_log_list[]
- Add routine mb_crtm()
BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701
Change-Id: I5120ffb6af0b41520056e1773f63b7b2f34a2460
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The vendorcode for verified boot is uploaded, but not used by a mainboard.
Add support to the mainboard for verified boot.
The items to be verifed are placed in board_verified_boot.c
BUG=N/A
TEST=Boot Embedded Linux 4.20 and verify logging on Facebook FBG-1701 rev 0-2
Change-Id: I3ea0a95287977df0dea13e05acedd5406538a6ee
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33463
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Connected 4K monitor is not configured at max resolution. The
framebuffer size is too small.
Increase the framebuffer size to 64MB. This is sufficient for max
configuration of 1 HDMI monitor combined with internal LCD panel.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: I25d2cd696830fc5bda84ea2b87538f526373998e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
PCB version is determined using inb() in actual code.
Create function mainboard_read_pcb_version to read pcb version.
BUG=N/A
TEST=Boot and verified on Facebook FBG-1701
Change-Id: I7c16627f468d84ca4ad2aab8bf9fb555f50dc23c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Select NO_UART_ON_SUPERIO as the SoC internal UART is used.
The current code is working, so this is just a cosmetic fix to remove
some unused options from Kconfig.
Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35151
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EFP1 is configured as 'DisplayPort with HDMI/DVI
compatibility'. Using this setting 4K monitor is configured
into lower resolution.
Change EFP1 setting to 'HDMI/DVI'
The next addtional small changes are made in VBT:
UEFI GOP Driver
Child Device 2 = LFP
Child Device 3 = EFP1/LFP
LFP Panel configuration Y-Res of Panel #10 = 1920
BUG=N/A
TEST=LCD and HDMI on Facebook FBG1701
Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
