Skylake moves back to having SerialIO devices be enumerated
as PCI devices instead of putting them all in ACPI mode.
There is currently no code that populates the device_nvs
fields so all the ACPI code to support that is dead.
Additionally because it contains _PS0/_PS3 methods that
causes the kernel to not use the standard PCIe PME handlers
and results in confusing messages at boot about not being
able to transition to a non-D0 state from D3.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados and ensure I2C devices work
Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b
Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295909
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the storage controller devices out of serialio.asl
and into a new scs.asl file and implement the power
gating workarounds for D0 and D3 transitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I43081e661b7220bfa635c2d166c3675a0ff910d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0c67b386974dedf7ad475c174c0bc75dc27e529
Original-Change-Id: Iadb395f152905f210ab0361121bbd69c9731c084
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295908
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11535
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the itss.asl code that was exporting PIRQ routing
control registers into irqlinks.asl and use the PCR access
methods to find the appropriate address. At the same time
clean up the code in irqlinks.asl to follow formatting rules.
Also now that the GPIO code in itss.asl is unused the file
can be removed.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I1af7d730542fd0e79b9f3db9f0796e7c701c59e6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39a96063d01d00ab768db1c723f78b5af9ed6513
Original-Change-Id: Iafa03c276cb276ec8c00c24ed2dba48d0dc9612b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295907
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11534
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the now unused RCBA base and size from iomap.h
and fix a trivial typo that doesn't seem to get used
anywhere.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emege-glados coreboot
Change-Id: If95dd2ee3f4a8dd0a6a7cf996aef8f19f27ddc48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee7b1a8a75a9e9dc191c16ddc32b6a38acec398c
Original-Change-Id: I0c49803d47105c3c55121caedaffaa249c4f0189
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11533
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the PCR Port ID for the storage controllers and
reformat to put the PCR PIDs in increasing order.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f0144ef79d3691fa120dafc9a31d2a681bf2a28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 208242f58759899f17e52593ed6e1dd631334ac9
Original-Change-Id: I942bcf01b0576136c0039aa62f38fe7f3454ba8a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295905
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11532
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are a few places in ACPI that touch PCR registers,
either to read a value or to set some magic bits.
Expose some functions for this that will keep all the PCR
access in one location instead of spread throughout the code.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Iafeb3e2cd8f38af10d29eaaf18f2380c5651fe6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78b2801fbc5c00ba452ae5e4ecb07c3e23bf6c1
Original-Change-Id: I2e4d491157f7ac6d2ebc231b11661c059b4a7fa0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11531
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the code in pch.asl:
- move all the C header includes into here instead of duplicated
in various ASL files included from here
- move the trap field definition into platform.asl with the method
- alphebetize the includes
- move gpio.asl include into pch.asl
- remove duplicate irqlinks.asl include from lpc.asl
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I51b1c5286fc344df6942a24c1dea71abf10ab561
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3ee9c4afa031191d275f0d3d40b2b15b85369b2f
Original-Change-Id: I3bae434ad227273885d8436db23e17e593739f77
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11530
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the code for PCIE _PRT entries to use an actual root
port number from the device instead of NVS that was never
initialized from zero.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados with pci=nomsi to ensure interrupts work
Change-Id: I76ff07d2bf7001aed504558d55cca9e19c692d7e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d43392199ec5f37150f2b13732924c47b8dc830c
Original-Change-Id: I1132f1dc47122db08d1b798a259ee9b52a488f5e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11529
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that cbfstool supports file alignment, we can use the conveniently
available <filename>-align handler, and remove the need to have a
separate rule in src/Makefile.inc just for adding the microcode.
We can also get rid of the layering violation of having the
CONFIG_PLATFORM_USES_FSP1_0 symbol in a generic src/cpu/ makefile.
Note that we still have a layering violation by the use of the
CONFIG_CPU_MICROCODE_CBFS_LOC symbol, but this one is acceptable
for the time being.
Change-Id: Id2f8c15d250a0c75300d0a870284cac0c68a311b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11526
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot has no CREDITS file.
Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This depends on RELOCATABLE_RAMSTAGE, and shouldn't be selected if
its dependency is not activated.
Change-Id: I8e7efc3f87e105715fe3377ed306891f0d209979
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11473
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether
or not the payload will actually be SeaBIOS:
1. PAYLOAD_SEABIOS, but payload changed with cbfstool
2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS
et. cetera.
Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11293
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
This patch adds the ASL files with the DPTF related settings and the
thermal devices enabled in the SOC. It also enables the DPTF setting
at the global NVS level.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7
Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293391
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11430
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The previously driven TX state of the buffer was not
being cleared before or'ing in the new value. Fix this
oversight.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Also dumped assembly and saw the
masking happen.
Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda
Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294541
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11416
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Aaron Durbin found that soc/common is already included as a subdir via
the wildcard in Makefile.inc:
subdirs-y += $(wildcard src/soc/*/*)
Since the entire file is protected by CONFIG_SOC_INTEL_COMMON, there
is no problem with including it for every platform. On the other hand,
when it is included by the skylake and braswell makefiles, any rule is
duplicated. As a result fix the braswell and skylake makefiles.
Change-Id: If5bad903c78dbce418852935ee55cdc7162b3b2d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11439
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The acpi_fill_ssdt_generator function pointer is evaluated for
each device. As there are multiple cpus in the system the
acpi_fill_ssdt_generator was being called more than once creating
duplicate ACPI entries because there was more than 1 cpu device.
Fix this by only generating them once by removing the
acpi_fill_ssdt_generator for the cpu devices, but add the
generator to the cpu cluster device.
BUG=chrome-os-partner:44084
BRANCH=None
TEST=Built and booted on glados. Noted ACPI entries only generated once.
Original-Change-Id: I695c30e6150f6d3a79d13744c532f1b658b10402
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294240
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: I7c85f44ba65398bda668e13db8be531535a983c5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The prior implementation of PAD_CFG_GPI kept the pad
ownership as ACPI. The gpio driver in the kernel then
wouldn't allow one to export those GPIOs through sysfs
in /sys/class/gpio. Fix this by setting the ownership
to GPIO.
BUG=chrome-os-partner:44147
BRANCH=None
TEST=Built and boot glados. PCH_WP gpio is properly exported
by crossystem.
Original-Change-Id: I9fc7ab141a3fd74e0ff8b3ff5009b007b8a0d69b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294081
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ifbb61c5d64bb6a04f140685c70f4681e2babecef
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11283
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory
regions reserved by fsp for chipset use. With that being removed, the
function needs to properly walk though the memory map resulted from fsp
memory init to find out the usable address for cbmem root.
Refer the FSP 1.3.0 Integartion guide for more details on the Memory
Map.
systemagent should also use the same mechanism to create the reserved
RAM resource.
BRANCH=None
BUG=None
TEST=Build and Boot kunimitsu (FAB3)
CQ-DEPEND=CL:*226035,CL:*226045,CL:291573
Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291611
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: http://review.coreboot.org/11239
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The skylake IO-APIC supports up to 120 redirection entries.
In practice it seems FSP has already written to this write-once
register. However, it doesn't hurt to actually be correct within
the source.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293251
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
One thing that is brittle is lining up GPE0 bits in ASL
and with a board's design proper. This results in open
calculated magic numbers. To help alleviate this provide
just #defines that C preprocessor can use before handing
the source off to the ASL compiler.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. Everything's intact.
Original-Change-Id: I359616ebe4bfc83c05bafe0ca36b766efd16dcca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293410
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I32513c324b923fa0adbd6a0ee920c27e9b97dd1b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11233
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Broadwell and Skylake chipsets, along with a few mainboards were
selecting ALWAYS_LOAD_OPROM without making sure that the dependency
for that symbol was met as well.
Looking at the dependencies for VGA_RUN_ROM, we see:
PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT
Since ARCH_X86 selects PCI, that's always met here.
Since Broadwell and Skylake don't have native VGA init yet, that's
not needed.
- Make sure that VGA_RUN_ROM is selected as well.
- Add dependency on !PAYLOAD_SEABIOS for both ALWAYS_LOAD_OPROM and
VGA_RUN_ROM symbols where they're selected.
Fixes Kconfig warning for these boards and chipsets:
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS)
selects ALWAYS_LOAD_OPROM which has unmet direct dependencies
(VGA_ROM_RUN)
Change-Id: I787a87e9467e1fc7afe8b04864b2a89b54824b9f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the dependency on CONSOLE_SERIAL to select CONSOLE_SERIAL based
on this question.
The dependency was causing multiple warnings on every platform tested.
src/console/Kconfig:21:error: recursive dependency detected!
src/console/Kconfig:21: symbol CONSOLE_SERIAL depends on
DRIVERS_UART_8250MEM
src/drivers/uart/Kconfig:16: symbol DRIVERS_UART_8250MEM is selected by
UART_DEBUG
src/soc/intel/skylake/Kconfig:198: symbol UART_DEBUG depends on
CONSOLE_SERIAL
Change-Id: Ia0426cd150561694081b5ea7c6797d36022c1f57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11243
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The current construction for processing SMI GPI events
didn't allow for the mainboard to query the state of a
particular GPI for the snapshotted SMI event. The
skylake part can route GPIs from any (there are design
limitations) GPIO group. Those status and enable registers
are within the GPIO community so one needs to gather
all the possibilities in order to query the state.
The call chain did this:
southbridge_smi_gpi(
clear_alt_smi_status() -> reset_alt_smi_status() ->
print_all_smi_status() -> return 0)
As a replacement the following functions and types are
introduced:
struct gpi_status - represent gpi status.
gpi_status_get() - per gpi query on struct gpi_status
gpi_clear_get_smi_status() - clear and retrieve SMI GPI status
mainboard_smi_gpi_handler() - mainboard handler using gpi_status
Also remove gpio_enable_all_smi() as that construct was never
used, but it also is quite heavy handed in that it would
enable SMI generation for all GPIs.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built.
Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291933
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The first pass of the GPIO configuration patch didn't
enable the SMI# generation for GPIs marked as SMI
routed. Now when a pad is configured as SMI routed
the bit for the SMI enablement is set accordingly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados. Confirmed SMI_EN being set
for SMI routed GPIOs.
Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/292010
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The gpio pad configuration currently defaults to ACPI
owned GPIs. A '0' was used which wasn't so clear. Add
a comment and explicitly set it to ACPI. Also,
PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS
macro which causes compliation errors if attempted
to be instantiated. No piece of code tried to use
it so the error was overlooked.
Lastly, allow for soc/gpio.h to be included during
ASL compilation. That allows for gpio_defs.h to be
included and those macros utilized without needing
to know the file name and where it lives; just use
the generic gpio.h.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291935
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of using a hard-coded value leverage the existing
definitions to perform GPE0 block length calculations. There
are 4 pairs of 32-bit status/enable registers.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I14d08298b5750c91ce0ac3fa33569813396f7089
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291932
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I127f026f15180fa79625d4cad96d5e35f85e5090
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ec_smi_gpio and alt_gp_smi_en devicetree options are
goign to be removed. The plan for skylake is to set the
settings by the mainboard through either gpio pad
configuration or through helper functions.
Moreover, these values only allow *1* SMI GPIO configuration
in that the following has to be true:
alt_gp_smi_en = 1 << (ec_smi_gpio % 24)
If not, then another gpio(s) from the same group has the
SMI_EN bit set for it.
Lastly, remove all the subsequent dependencies as they are
no longer used: enable_alt_smi() and gpio_enable_group().
BUG=chrome-os-partner:43778
BRANCH=None
TEST=None
Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291931
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On skylake the GPE0 routing can be dynamically changed to
a particular GPIO group. Provide the ability for the mainboard
to set the route accordingly. If any of the values in the
devicetree are the same the current setting in the PMC register
is used. The GPIO communities need to have matching configuration
for the plumbing to work properly.
BUG=chrome-os-partner:43778
BRANCH=None
TEST=Built and booted glados w/ and w/o devicetree changes. Fields
are set accordingly.
Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291930
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
IedSize is not used in replace of IED_REGION_SIZE.
Drop it from chip.h.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290933
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11201
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The stage_cache_external_region() calculation is actually
dependennt on the properties of the chipset. The reason
is that certain regions within the SMRAM are used for
chipset-specific features. Therefore, provide an API
for abstracting the querying of subregions within
the SMRAM.
The 3 subregions introduced are:
SMM_SUBREGION_HANDLER - SMM handler area
SMM_SUBREGION_CACHE - SMM cache region
SMM_SUBREGION_CHIPSET - Chipset specific area.
The subregions can be queried using the newly
added smm_subregion() function.
Now stage_cache_external_region() uses smm_subregion()
to query the external stage cache in SMRAM, and this
patch also eliminates 2 separate implementations of
stage_cache_external_region() between romstage and
ramstage.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290833
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11197
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The smm_subregion() support allows the SMM relocation
to not use duplicated math by calling out the specific
regions it wants. IED base is now correct and not
pointing outside from SMRAM.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290930
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11198
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The TSEG is defined to be from TSEG->BGSM in the
host bridge registers. Use those registers at
runtime to calculate the correct TSEG size.
Lastly, use a few helper macros to make constants
more readable.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290832
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11195
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch enables GPIO controller for skylake. It adds
community base addresses and offset for Community0, Community1,
and Community3. Community2 is not exposed in BIOS or enabled
in the kernel driver.
Also, clean up the carry over GWAK implementation from BDW.
BRANCH=None
BUG=chrome-os-partner:42393
TEST=cat /sys/kernel/debug/gpio should list of GPIOs
TEST=export a GPIO pin using /sys/class/gpio/export
Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: http://review.coreboot.org/11191
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Explicitly clear all write-1-to-clear fields in the
appropriate power state registers. That way stale
state isn't left around from boot to boot. The
MMIO PMC registers are always added such that the
resource can be accessed from reg_script. It doesn't
hurt to add the resource, and it's actually more
informative by attaching the actual resources
owned by the device.
BUG=chrome-os-partner:43625
BRANCH=None
TEST=Built and boot glados. Did global reset. Noticed bits
set. Did normal reset and saw those same bits no longer set.
Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290339
Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11186
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Leaving a sentinel 0xC0DEBABE and fixing it up is
is the old way of setting the correct base address
for GNVS. One just needs to reference NVSA which is
already filled in by the skylake ACPI code.
BUG=chrome-os-partner:43611
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados. /sys/firmware/log shows
up as well as ramoops using the correct address.
Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290338
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I25efea73a383215f9365ce91230f79516b0201a6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11185
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide #defines for the bit fields in the SMI status register.
This allows for one to set the callback accordingly without
hard coding the index.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289802
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11184
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM
training is complete. However, as a 8-bit write was
being performed the bit was never being set.
BUG=chrome-os-partner:43516
BRANCH=None
TEST=Built and booted to kernel. Rebooted. Noted full memory
training was not being peformed.
Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290337
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11183
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Open coding bitfields is really annoying as no one knows
what they are unless you have a doc in front of you.
Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B
registers.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290336
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11182
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
FSP was setting up the TCO registers to be mapped at 0x400.
However, the SMBus initialization in romstage was mapping
its I/O BAR to 0x400 as well. The result seemed to cause the
TCO register to be hidden. However, the board was rebooting in
depthcharge when the SMBus device was enabled from a TCO timeout.
As the TCO timer was halted before the double resource assignment
it's not clear how the TCO was getting re-enabled. In either case,
the current behavior is wrong.
BUG=chrome-os-partner:42407
BRANCH=None
TEST=Built and booted glados w/ SMBus enabled.
Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290363
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It's important to be able to configure the gpio pads at
various stages instead of a single place using FSP. Without
this support there is a lot of duplicated open-coded pad
configuration taking place both within the SoC code and
mainboards.
Current limitation is that all GPIOs are in ACPI mode. i.e.
The HostSW ownership register sets the pad configuration to
only update GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS. The
GPI_STS update is masked within the GPIO community registers.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Id8a00e99c7a4c3912de2feaff9cea12b402f2c68
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289789
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I4c86b47ac5ab004f2bfd7cb07dd23c458f7dbb7c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11174
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default. Remove from the soc Kconfig and add a
default Kconfig for SOC_INTEL_SKYLAKE.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=built glados
Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289833
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11168
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In the review process for http://review.coreboot.org/#/c/11052/
the code was mangled and the result was unbuildable code. Fix this.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Can actually build bootblock.
Original-Change-Id: I5bc63b8c435dbf025f1c334e9a1bc4a9da2b4902
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289788
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: Id0f67d8b74fa9146bf01990f599d538222f7e0e2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11167
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For Skylake, Microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If This is supported the FIT microcode
load will set the msr (0x08b) with the Patch id one less than the
id in the microcode binary. This results in Microcode getting
reloaded again in bootclock and ramstage (MP init).
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None TEST=Built for glados and tested on RVP3
CQ-DEPEND=CL:287513
Change-Id: Ic5dbf4d14dc1441e5b5acead589a418687df7dca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c599714b2aef476297eeaad5da8975731b12785a
Original-Change-Id: Id3a387aa2d8fd2fd69052bfc7b4e88a7ec277a72
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11056
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
If Skylake microcode is being loaded from FIT, Skylake supports
the PRMRR/SGX feature. If this is supported the FIT microcode
load will set the msr (0x08b) with the patch ID one less than the
ID in the microcode binary. This results in microcode getting
reloaded again in the bootblock cpu init.
Avoid the microcode reload by checking for PRMRR support.
BUG=chrome-os-partner:42046
BRANCH=None
TEST=Built for glados and tested on RVP3
Change-Id: I06e59f5cad549098c7ba2dfa608cd94a0b3f0ae1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6242b9dea283149bd0c968af1ba186647d37162d
Original-Change-Id: Iea5a223aa625be3fc451e8ee5d3510f548b07f8b
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/286054
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11052
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Remove the items that are obviously broadwell left or become no-need
with fsp.
BUG=chrome-os-partner:43186
BRANCH=None
TEST=build and boot on sklrvp3.
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I5dfd62363eecc514e45a7b7ba0961ec7fe0499ee
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 570920cdc9e9c08ee85dcb08998069f1cae2d3cd
Original-Change-Id: I63176584042516c4d28f1bb6403e7bbe5de61010
Original-Reviewed-on: https://chromium-review.googlesource.com/288833
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11072
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some of the field and register names in the power management
code were not reflecting current chipset documentation. While
in there fix 0-sized array in the power_state structure. Lastly,
log the entire STD GPE register for visibility in elog. It reports
as an extension of other GPIO wake events.
BUG=None
BRANCH=None
TEST=Built and booted.
Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e
Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288296
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11070
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to aid users of the PCR register space provide
pcr_port_regs().
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built glados.
Change-Id: Ibfcffbfd4304a59dd80a88dc18404d3a5dfa2f5d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5f796319ba1d00557e32bf18309fc3cc772ccae0
Original-Change-Id: I21243d18c1bbd19468f8f279b2daa4e40a8f0699
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288193
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11068
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to provide more clarity on what some of the gpio
functions are doing add a 'gpio_' prefix to the globally
visible functions.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built glados.
Change-Id: I4cf48558c1eb9986ed52b160b6564ceaa3cb94b4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: f79ef113797884063621fe6cd5cc374c53390ebd
Original-Change-Id: I0d8003efff77b92802e0caf8125046203f315ae4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288192
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These types and definitions were carried over from a previous
platform. However, they are not used. Remove them.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built on glados
Change-Id: Ib3d20222df34a32865aac6b6cf13517c208e17c6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: be2d0d273a6c02483a944edac95ab48c433b29cd
Original-Change-Id: I56a0d549f5733eec8f405f2024ced8c153fa545c
Original-Signed-off-by: Aaron Durbin <adurbin@chormium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288191
Original-Trybot-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The fspNotify(EnumInitPhaseAfterPciEnumeration) is already
registered in fsp_util.c as a generic callback, this is some code
left from early development.
Also I don't see a need for the chip_final function, although we
could keep it as a placeholder but i decided to remove it.
BUG=chrome-os-partner:42979
BRANCH=None
TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3.
Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7
Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287991
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11054
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In order to build without CONFIG_CONSOLE_SERIAL the Skylake
SOC Kconfig should not be enabling serial console by default.
Also fix other compile issues when serial console is disabled.
BUG=chrome-os-partner:40857
BRANCH=none
TEST=build glados without serial console enabled
Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55
Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/287438
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11043
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove the C types and functions from PCR so that pcr.h
can be included from assembly and ACPI. While in there
make the PCR reg caclulation using a C function and
place the P2SB (PCH_PCR_BASE_ADDRESS) address in iomap.h.
BUG=None
BRANCH=None
TEST=Built and booted glados.
Change-Id: I9cde178bcdbf49327ef7892393fc277f6c74f34b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fdf5c77ecfa0ca8d3c45604d15b9dec9a6e85193
Original-Change-Id: I5996efaa9869f8f412e4d45c13f30233384a38b2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286901
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11030
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current primary to sideband (P2SB) code for private configuration
register (PCR) access weren't very clear with the naming or
reasoning for some of the code. Provide more verbiage surrounding
this interface.
BUG=None
BRANCH=None
TEST=Built and booted glados.
Change-Id: I5b2e84444a29b2fc2f527502e8c9f26eb60e687a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06345ba1abd893059a6584856851f92f43289247
Original-Change-Id: If57a4bbc90365c1135b4986dce328b5dbabe483b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286900
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11029
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Log the global reset causes in the power state structure.
While working in there pack the struct and use width-specific
types as this struct crosses the romstate <-> ramstage boundary.
Lastly, remove hsio version as it wasn't being written or read.
After global reset induced:
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
GEN_PMCON: d8010200 00003808
GBLRST_CAUSE: 00000000 00040004
Previous Sleep State: S0
BUG=None
BRANCH=None
TEST=Induced global reset on glados using ETR3 register and write
to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47
Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286640
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11011
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If a resume from S3 is occuring one needs to take into account
deep S3 in order to check the proper power failure bits.
When deep S3 is enabled the suspend well will be turned off.
Therefore don't look for that bit when determining a power
failure.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Suspend and resumed with deep s3 enabled and disabled.
Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2
Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286271
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and
save the full 32 bits for completeness.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Built and booted. Noted output on terminal.
Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0
Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286270
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch updates the Serial IO modes for UART2 to PCI mode
in devicetree for glados board.
Also we switch over to CONSOLE_SERIAL8250MEM_32 here. 8-bit
legacy UART will stop working after devicetree change.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for glados and tested LPSS logs on glados.
CQ-DEPEND=CL:284881 CL:284882 CL:284883
Change-Id: I433979c852c80848c006ef089b43d75a17e761c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c37519e0762801cbb9b547b538b385c84299189
Original-Change-Id: I2faec08d089e407c5ab9838bea980553f49821c4
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284826
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11002
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
FSP will initialize GPIOs during TempRamInit.
So configure LPSS UART2 GPIOs in native mode
after TempRamInit.
BRANCH=none
BUG=chrome-os-partner:41374
EST=Build and boot on RVP3. Check LPSS logs on UART2
Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c
Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9
Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
FSP 1.1 platforms should be conforming to the spec. In order
to ensure following specification remove the crutch that allows
FSP to no conform.
BUG=chrome-os-partner:41961
BRANCH=None
TEST=Built.
Change-Id: I28b876773a3b6f07223d60a5133129d8f2c75bf6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c3fe08c5af41867782e422f27b0aed1b762ff34a
Original-Change-Id: Ib97027a35cdb914aca1eec0eeb225a55f51a4b4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285187
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All boards should have their L1 sub states working now so
re-enable the defaults.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built and booted glados into OS. PCIe devices show up still.
Change-Id: Ic040fa108a662e15bb97cf8b0961f0f56683e146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 380491f8267e60c3c6bc62486aaf21e201fcfd36
Original-Change-Id: Idc6923b1fdd1c20d463eb7782be112f90b9adbfd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285170
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10989
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For some unkonwn reason the pcie root port settings weren't
being honored in the device tree. Fix that omission.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
settings were being honored.
Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285027
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10987
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Unhide the SPI controller PCI device if it is enabled in
devicetree.cb so flashrom can do its job.
BUG=chrome-os-partner:37711
BRANCH=none
TEST=run flashrom -r on glados
Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245
Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284948
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
They have been removed in the rest of the code already.
http://review.coreboot.org/#/c/4506/
Change-Id: I232cc2ccd4dd90359de4ab710486db65667500f4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10964
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Found by the commit hooks.
Change-Id: I9baa90ca0111ddc9cb69cbb7dd17f63e8a98a04f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10965
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
