Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is abuild-tested by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
lib/debug.c and use that one.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works good enough to boot to a Linux console.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3650 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as the global src/arch/i386/lib/failover.c file).
Also, drop a number of dummy failover.c files which are not even used at all.
This is abuild-tested by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3649 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to v3 sooner or later we cleanup _now_, so we don't have to do it twice.
- Whitespace, coding style improvements.
- Fix a few typos.
- Add a missing #endif in raminit.h.
- Drop an unused variable.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Marc Jones <marcj.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We shouldn't assume the presence of a working HDA codec, so put in
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is
present in Simnow, it is non functional.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to clean it up a bit and find justifications for every difference from
x86 and AMD CAR code. I believe this is mostly merge-ready. Although I'd
have preferred to do this for v3 first, we can fix v2 boards with this
change and then move them to v3.
Thanks to Bari Ari for getting the code to me for rewrite/review.
CONFIG_CARTEST shall not be enabled (breaks the build).
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Jason Zhao <jasonzhao@viatech.com.cn>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
certainly won't build -- that comes later. I am hoping to get some
eyeballs on it for simple errors.
rs690 is next.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change a few PCI bus/dev/fn to use hexadecimal numbers.
Kill unused variables.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This fixes that build error. (trivial)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The only non-cosmetic change is s/A8NE/A8N-E/ for the board name.
This is build-tested by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
A trivial fix to correct the address of the high byte in SDRAMC.
Thus the leadoff timing IPDLT will be correctly referenced.
Signed-off-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
option.
This patch converts the following patches to use PRTINK_IN_CAR
amd/serngeti_cheetah
msi/ms9185
msi/ms9828
supermicro/h8dmr
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ChannelB slot. Previously a DIMM could only be populated in ChannelB
if there was a DIMM already in ChannelA. This patch doesn't allow unmatched
DIMMs to be populate in ChannelA and ChannelB. In an A & B configuration
the DIMM must still be matched.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fix the a8n_e and any other it8712f SIO keyboard issues. The it8712f
requires an archaic PS/2 mode setting to the keyboard controller before
accessing the keyboard. Beyond that, I made the keyboard controller and
keyboard init more robust and added more informative debug output.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3610 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
default 48MHz clock input. The Asus a8n_e uses the it8712f
with a 24MHz clock input. The it8712f early init code was
setting a 24MHz input clock(to support the a8n_e).
Since 48Mhz is the default I added a function to set 24MHz
input clock to the a8n_e.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VT8237R (random keyboard/mouse lockups).
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
problem left is with CPU scaling setup. No VGA - may work with the Xorg drivers
recently released, maybe with OpenChrome too.
It wont work with the little patch which will hop in soon
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Most of the functions in SB600 are enabled except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All the PCIe slots are enabled in this patch except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.
U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.
Second small change just changes a bit which controls the PSTATECTL logic.
Third change deals with the integrated VGA, which needs to be enabled early,
so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
correctly. Finally the CPU accessible framebuffer is now disabled as it is not
needed.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Michael Xie Michael.Xie@amd.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* change the comment for device f.0 from "IDE" to "SATA"
* turn on firewire device a.0
* turn on pata device f.1
* don't turn on the unusable device 10.5 (built-in vt8237 ethernet?)
Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use dev_path() to have nice debug output
patch is run-time tested
Trivial, thus:
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
changes the superio to a Fintek F71805F as described at
http://www.coreboot.org/Jetway_J7F2_Build_Tutorial
It also creates the mainboard tree for this series of motherboards
(Jetway J7F2 and J7F4). I've tested it with one motherboard
(J7F2WE1G3), and I believe it works with the others, as the differences
among them are mostly trivial (processor speed, chipset and quantity of
LAN cards, audio chipset, etc.). A list of the relevant motherboards
with specs can be found at
http://www.jetway.com.tw/jw/ipcboard_socket.asp?platid=16
The irq_tables.c is copied directly from the epia-cn, because the one
generated by getpir with the factory BIOS did not work properly while
the EPIA-CN one did.
Minor changes on checkin to cope with moved romcc in latest revision.
NOTE: This board is broken until the issue introduced in r3567 is resolved.
Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3571 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
on mine desktop) except of reverting the small change introduced by Bari
(gpio/inta setup reg 0x5b). This should go for some board specific file. The
change would broke at least mine board. But seems to be needed for jakllsch.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Bari Ari <bari@onelabs.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All devices work, no irq storms. Enjoy.
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
LinuxNetworx own the copyright for the Intel e7520, e7525 and 3100
raminit code.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3546 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
option CONFIG_PRECOMPRESSED_PAYLOAD=1
set in Config.lb but accidentally use an uncompressed payload, coreboot (v2)
bombs out like this:
elfboot: Attempting to load payload.
rom_stream: 0xfffc0000 - 0xfffdefff
Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
Decoding error = 1
Unexpected Exception: 6 @ 10:04000408 - Halting
Code: 0 eflags: 00010057
eax: 00000101 ebx: 04000400 ecx: 000003d4 edx: fffc0000
edi: 04000400 esi: 04000401 ebp: 04000400 esp: 0013dfb4
The attached patch modifies v2's lzma code so that it assumes an uncompressed
payload if it fails to find a properly compressed payload.
Compare with the fatal error above:
elfboot: Attempting to load payload.
rom_stream: 0xfffc0000 - 0xfffdefff
Uncompressing to RAM 0x01000000 Decoder scratchpad too small!
olen = 0x00000000 done.
Decompression failed. Assuming payload is uncompressed...
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
If you don't have CONFIG_COMPRESSED_PAYLOAD_LZMA and
CONFIG_PRECOMPRESSED_PAYLOAD set and use an uncompressed payload, things are as
before:
elfboot: Attempting to load payload.
rom_stream: 0xfffc0000 - 0xfffdefff
Found ELF candidate at offset 0
header_offset is 0
Try to load at offset 0x0
One can argue that this is a case of 'builder beware', but my counter argument
is that anything that causes unexpected runtime breakage is really, really,
really bad, and should be avoided where possible.
This patch also fixes one erroneous comment.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3542 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and renames some existing macros for clarity.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
integrated LPC, SMBus, USB and SATA devices of the Intel EP80579
Integrated Processor.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Thanks Arne. Good job.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in a couple of occurences)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3509 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This works fine in Linux if you use the 'irqpoll' kernel command
line option.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3469 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
own welcome message.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3468 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in a number of places.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CONFIG_AP_IN_SIPI_WAIT flag. Newer Intel CPUs need this to operate with
multiple cores.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fixes a warning
* puts some debug messages to spew because they're only useful to debug CAR
* print an explicit message "Uncompressing..." instad of "Copying..." when
coreboot_ram.rom is compressed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
drove me crazy during debugging. Fix Typos. Add a warning because the
on-chipset devices are hardcoded. For newer machines, a lot more memory space
will have special meanings, and we can't hardcode them all in an ifdef desert.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
supposed to be. rename LXBIOS to CORE in ACPI table identifiers. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3442 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The change in tables.c protects the legacy x86 BIOS data segment
(0x400-0x4ff) from being used for storing coreboot tables. Some
bytes from the segment are used by the kernel and should not be
garbled.
The change in coreboot_table.c is not strictly necessary. It removes
some redundancy and confusion.
Signed-off-by: Roman Kononov <kononov@dls.net>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3437 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
went missing....
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3436 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Includes setting for most recent errata.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3432 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Sean Nelson <snelson@nmt.edu>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3424 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested by me on actual hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-Off-By: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on v1 and v2 of the board.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the range of 0xf0000-0x100000, where the Coreboot tables live in v2.
As long as the payload doesn't need the tables, it seems harmless, so
why not just print a warning?
This allows v2 to load "legacybios" without having to have a separate loader.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
It'll be fine for testing and doesn't really break anything that did
work before...
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This also contains various improvements of the CN700 code in svn.
Signed-off-by: Aaron Lwe <aaron.lwe@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the possible IRQs generated by the SIO. This included IRQ 7 as the default
parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's
own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards
that were setting it to prevent the conflict and crash when the MFGPT driver
loads.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3328 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There isn't really any good reason to have the second serial port
enabled on Norwich, and this makes the X DDC code stop working.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3294 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pci_write_config8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- W83627THF is strapped to 0x4e, not 0x2e
- there's no device 9 on PCI-E x1 bus, it should be device 0
- add mptable entries for AGR slot, based on info in user manual
- enable floppy drive controller so that some legacy VGA ROMs will work
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3279 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for both serial ports, making it challenging to use COM2 for the early
console.
Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This doesn't save any space for me but it is the right thing to allow GCC to
optimize.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Peter did a nice job cleaning up my initial patch. Thanks!
Signed-off-by: Marc Jones <marc.jones@amd.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Disabling it should help performance.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is based on amd-lx800/cs5536.
Tutorial: http://www.coreboot.org/IEI_LX_800_Build_Tutorial
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3261 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
white space in the s2892 and s2891 mptable.c files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.
Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.
While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Pstate intialization has moved to early init because it requires a warm reset.
Add CPUID setup and disable SMM access to late initialization.
Much of this code is leftover from porting from K8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In addition, AP microcode is now updated in early initialization to support errata settings that require it.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add early MSR and PCI register initialization.
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code
to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This fixes many default setting as well as erratas.
Some CPU core functions were moved from the HT init and platform specific code to the generic Fam10 CPU code.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generic SMSC support, and corrects a small typo.
With this patch, coreboot v2 on a mainboard with SCH3112 has been
demonstrated to correctly use the serial port. No other chip
functions were tested.
Signed-off-by: Christopher Kilgour <techie@whiterocker.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3244 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
recomendations.
Changes include the following:
fix > 4GB dqs tests
fix channel interleaving
ecc memory scrub updates
MC tristating updates
debug print changes
fix memory hoisting across nodes -
The DRAM Hole Address Register is set via devx in each node, but the Node
number <-> DRAM Base mapping and the Node number <-> DstNode mapping is
set in Node 0. The memmap is setup on node0 and copied to the other nodes
later. so dev, not devx. The bug was the hole was always being set on the
first node.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
patch.
Signed-off-by: Marc Jones (marc.jones@amd.com)
Acked-by: Marc Jones (marc.jones@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3220 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This field is rarely used (and not used in the LX tables).
There is not a good reason to mask off non-exclusive IRQs.
Signed-off-by: Marc Jones(marc.jones@amd.com)
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It also keeps the boot processes from rebooting through out the coreboot process.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
interpret whitespace as macro argument delimiter. Since the code is
preprocessed by gcc and the tokenizer may insert whitespace, that can
fail. http://sourceware.org/bugzilla/show_bug.cgi?id=669
The same change was committed in r3044 to the AMD CAR code.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
"off" in Config.lb should cause the PCI device not to respond to
configuration requests.
Replace the existing code that I naively copied from esb6300 with
something that actually works on the 3100.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There are no boards that use the i82801DB (ICH4). The code does NOT work.
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Ed Swierk <eswierk@arastra.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3206 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.
The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.
It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Ed Swierk