IT8716F decodes any address to the attached SPI ROM.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashchips.c, but the IDs in flash.h will make lookups easier if anybody
wants to add support for them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3321 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Powerdown) SPI command to flashrom to identify older SPI chips which
can't handle JEDEC RDID. Since RES gives a one-byte identifier which is
shared among many different vendors and even different sizes, we want to
match RES as a last resort if RDID returns 0xff 0xff 0xff.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
This is a heavily reworked version of a patch by Fredrik Tolf, which was
Signed-off-by: Fredrik Tolf <fredrik@dolda2000.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
detected by JEDEC probe routines all have vendor IDs with correct
parity. Use a parity check as additional hint whether a vendor ID makes
sense.
Note: Device IDs have no parity requirements whatsoever.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3308 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
have different register meanings, so they get their own lookup tables.
This is a trivial patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3307 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch has no code changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ICH9 SPI support. In theory, this patch has no behaviour changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
by Harald Gutmann.
SST39VF040 has been confirmed to probe OK by misi e.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
series has the same IDs.
Add short AMIC vendor ID to flashrom.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This paves the way to have a fully generic generic_spi_command without
knowledge about any SPI controller.
The third step would be calling SPI controller functions via a function
pointer.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3296 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is a very early step toward cleaning up SPI code in flashrom.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
will be printed twice in the output (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3292 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Currently there is an ongoing technology migration from LPC/FWH to SPI chips.
For this reason some boards have multiple chips of different technologies
onboard. This patch makes flashrom probe for up to 3 chips and if more than
one chip is found flashrom exits, asking the user to specify -c.
[root@localhost src]# ./flashrom
...
Multiple flash chips were detected: SST49LF008A M25P16@ICH9
Please specify which chip to use with the -c <chipname> option.
[root@localhost src]#
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Claus Gindhart <claus.gindhart@kontron.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3291 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Two bits indicate OK and BAD for each operation PROBE READ ERASE WRITE.
8 bits out of 32 are in use now. No bits set means nothing has been tested.
For chips with at least one operation that is not tested or not working, the
user is asked to email a report to a special email adress so that the table
can be updated.
All chips are TEST_UNTESTED for now.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
devices, because they need an unlock command first.
For this reason, ST M50FLW support is moved to a
new HW support module, because any change in jedec.c
would bear the risk to cause problems with the already
supported devices.
It's already tested with ST M50FLW080A; the other
chips of this family i dont have available, so i couldnt
test it.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
flashchips table. The read pointer was already checked properly.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
layout option, as well as areas, whose flash contents already contain the
desired data, will be skipped.
These ensures absolute data security of critical areas (BIOS boot block),
e.g. against a sudden power off or a CPU hangup during flashing. As a
nice side effect, it speeds up the flash process, if the BIOS to be flashed
is very similar to the version in flash.
Signed-off-by: Claus Gindhart <claus.gindhart@kontron.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This chip seems to be very similar to the SMSC DME1737, for coreboot
purposes it might even work without any code changes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This decreases the size of the superiotool binary from ca. 1.1 MB to 600 KB.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Support for the Winbond W39V080FA series of chips.
Support for flashing on the Kontron 986LCD-M board.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Support for flashing on the Kontron 986LCD-M board.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Also dump the extra registers (e.g. EC regs) in --list-supported.
- Small fix in the code to allow for building with -pedantic (yes,
the fix is a bit silly, but it's simple and allows us to use the
-pedantic flag to keep the code even cleaner and nicer).
- Install the binary in /usr/sbin, as it's meant to be run as root.
- Small typo in README.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3163 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ICH* chipsets. Functionality (except printing) should be unchanged.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Ward says:
This code detects the ICH8 chipset on my laptop, and it appears to use
SPI.
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3144 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Cosmetic changes in some files, partly bending the 80-characters-per-line
rule in this special case, as the 80-character-limited version looks
equally crappy even in an 80x25 console/xterm, so let's make it at least
look good in a high-resolution xterm.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3139 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
been used in the last few years, and the contents are available in
the README already anyway.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3134 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
'superiotool --help' already provide the same information (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer for coresystems GmbH in 2005, as confirmed on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pnp-style configuration registers, using the new option -e/--extra-dump.
This patch only adds dumping of the Environmental Controller
configuration registers for the IT8716f chip.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
I (Carl-Daniel) checked the data sheets of the whole IT87[012] series
and although the environment controller is sometimes called fan
controller, the location of the register is the same for all models.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also add a comment about NULL subsystem IDs leaving the board entry out
of auto-detection logic.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch introduces virtual LDNs changes for W83627EHF driver. Not only LDN 7 and 9 are
changed, but also a SPI flash interface which has enable on bit1 and not bit0.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
specifying custom CFLAGS/LDFLAGS from the make command line like:
make CFLAGS="..." LDFLAGS="..."
I need to do this when building flashrom in a cross compiler environment
like buildroot for a foreign target.
Signed-off-by: Clark Rawlins <clark@bit63.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3102 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Remove the "enable write to flash" message, as the caller appears to
already report that.
- Move the 'modprobe msr' suggestions to the first lseek64 error handling, as
we get an error there already.
- Rename a perror string from "read" to "read msr", as we use the latter
already in this function for another read.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3101 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, move a big code comment to the top of enable_flash_cs5536().
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CS5536 that have the Boot ROM on NOR flash that is directly connected to
FLASH_CS3 (Boot Flash Chip Select).
We need to write enable it in the NORF_CTL MSR register for flashrom to
be able to write to it, including JEDEC probe commands.
This patch allows us to stop using AMD gx_utils.ko for BIOS flashing on
the DBE61.
Signed-off-by: Mart Raudsepp <mart.raudsepp@artecdesign.ee>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Programmable Micro Corp (PMC) need this.
Both the serial and parallel flash JEDEC detection routines would
benefit from a parity/sanity check of the vendor ID. Will do this later.
Add support for the PMC Pm25LV family of SPI flash chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Chris Lingard <chris@stockwith.co.uk>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
one board name that matches. The full syntax still works, and is required
when two vendors have boards with the same names.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
Tested on the pcengines alix1c and works fine.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Update website URL to http://coreboot.org/Lxbios.
- Use svn:keywords property to actually expand the $Id$ entries.
- Update COPYING to the latest version from
http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I've tested and verified the chip myself, and it seems to work
everything like supposted, since Carl-Daniel has patched flashrom to
use the read funktion on verifying.
"benchvice flashrom # ./flashrom -m gigabyte:m57sli -v test.4mb
Calibrating delay loop... OK.
No coreboot table found.
Found chipset "NVIDIA MCP55", enabling flash write... OK.
Found board "GIGABYTE GA-M57SLI-S4": enabling flash write...
Serial flash segment 0xfffe0000-0xffffffff enabled
Serial flash segment 0x000e0000-0x000fffff enabled
Serial flash segment 0xffee0000-0xffefffff disabled
Serial flash segment 0xfff80000-0xfffeffff enabled
LPC write to serial flash enabled
serial flash pin 29
OK.
MX25L3205 found at physical address 0xffc00000.
Flash part is MX25L3205 (4096 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED.
benchvice flashrom # ls -l test.4mb
-rw-r--r-- 1 root root 4194304 22. Jan 16:27 test.4mb
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
access instead. That fails if the flash chip is not mapped completely.
If the read function is set in struct flashchip, use it for verification
as well.
This fixes verification of all SPI flash chips >512 kByte behind an
IT8716F flash translation chip.
"MX25L8005 found at physical address 0xfff00000.
Flash part is MX25L8005 (1024 KB).
Flash image seems to be a legacy BIOS. Disabling checks.
Verifying flash... VERIFIED."
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Harald Gutmann <harald.gutmann@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3070 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
readcnt==0 saves 10 seconds with the unconditional 10us delay, reducing
programming time for SST25VF016B to 40-45 secs.
Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3068 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
are already in use, the patch uses 'R' (for release) and, of course,
'--version'.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
patch is tested on actual hardware.
As per datasheet the ID should be 0x886? for those chips.
Not mentioned in the datasheet, but sensors-detect says
0x8853 is also possible. Also, the ASUS A8V-E Deluxe
(W83627EHF) has an ID of 0x8854 (verified on actual hardware).
So assume all 0x88?? IDs to mean W83627EHF/EF/EHG/EG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I have test that on my board, it works ;)
Signed-off-by: Bingxun Shi <bingxunshi@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After the patch [...] The line length is still below 80 characters.
Signed-off-by: Bernhard Walle <bernhard.walle@gmx.de>
Acked-by: Torsten Duwe <duwe@lst.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Straight from the data sheet, not tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
exactly the same ID. Improve model number printing.
Add EN29F002(A)(N)B support while I'm at it.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Markus Boas <bios@ryven.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The continuation ID code does not go further than checking for IDs of
the type 0x7fXX, but does this for vendor and product ID. The current
published JEDEC spec has a list where the largest vendor ID is 7 bytes
long, but all leading bytes are 0x7f. The list will grow in the future,
and using a 64bit variable will not be enough anymore.
Besides that, it seems that the location of the ID byte after the first
continuation ID byte is very vendor specific, so we may have to revisit
that code some time in the future.
(Suggestion for a new encoding:
Use a two-byte data type for the ID, the lower byte contains the only
non-0x7f byte, the upper byte contains the number of 0x7f bytes used as
prefix, which is the bank number minus 1 the vendor ID appears in.)
Add support for EON EN29F002AT.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(JEP106W), adds some device IDs and provides information about
non-conforming IDs.
The EON change is left to the patch adding EON chips.
This patch should have no effect on code generation.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3029 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
page size. Fix that. Page size is uniform 256 bytes for SPI.
A sector/block size field in struct flashchip would be nice, though.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3027 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
output is specified.
Pretty-print the chip status register (including block lock information)
for ST M25P family and Macronix MX25L family chips.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M25P64, M25P128 to flashrom. ST M25P80 support is already there.
Not tested, but conforming to data sheets and double checked.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with multiple possible opcodes from linear numbering at the end (_1, _2)
to include the opcode at the end (_60, _c7). That way, you only have to
take a short look at the data sheet and choose the right function by
appending the opcode listed in the data sheet.
No functional changes.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
PC97317 has SID = 0xdf. PC87371/PC97371 do not seem to exist.
Signed-off-by: Ulf Jordan <jordan@chalmers.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, s/0xFF80/0xFFC0/ in the Acorp 6A815EPD board-enable, as per
http://www.linuxbios.org/pipermail/linuxbios/2007-December/027750.html
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2995 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add missing contributors to the README.
- Drop obsolete -D option from manpage.
- Only list contributors who added non-trivial amounts of code as copyright
holders (and do not list those who merely provided register dump support
for Super I/Os). Those contributors are still listed in the README,
of course. See discussion in the thread starting at
http://www.linuxbios.org/pipermail/linuxbios/2007-October/025516.html
- Make a function static.
- Fix incorrect URL in code comment. Drop obsolete comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Attached is a patch that enables AMD Geode CS5536 chipset support. I
have tested it successfully on a MSM800 board from digital logic.
Signed-off-by: Lane Brooks <lbrooks@mit.edu>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a delay of 10 us after entering ID mode and this was insufficient for
the 29C020. The data sheet claims we have to wait 10 ms, but tests have
shown that 20 us suffice. Allow for variations in chip delays with a
factor of 2 safety margin.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Small cosmetic fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2956 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is the common style in both Linux as well as in LinuxBIOS.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add support for the Fujitsu MBM29F400TC flash part.
Detection and reading works, writing is not tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2903 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Looking through the sources of Uniflash utility I found that this chip
is no more no less than low-voltage variant of Am29F040B but with
different ID.
So I created a very quick patch (attached).
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2897 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
making the output of "make -s" finally usable.. (still trivial, doesn't
change any logic or remove any code)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
status register instead.
This has been tested by Harald Gutmann <harald.gutmann@gmx.net> with a
MX25L4005 chip.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
chip the code was tested and verified with is the Macronix MX25L4005,
but other chips should work as well.
Timeouts are still hardcoded to data sheet maxima, but the status
register checking code is already there.
Thanks to Harald Gutmann for the initial code on which this is loosely
based.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the --dump option, it just means lots of additional work for no gain, IMO.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2872 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We often want to know the exact version number of superiotool which
was used to gather a certain output/dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Install binary in /usr/sbin (not /usr/bin), as it's a root-only tool.
- Rename manpage from flashrom.1 to flashrom.8, as section 8 contains
"System administration commands (usually only for root)".
- Actually install the manpage upon 'make install'.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Michael van der Kolff <mvanderkolff@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
has a slightly different format than that of the W83697UF/UG so we have
to hack around it a bit.
This patch has been verified to work on real hardware by
Idwer Vollering <idwer_v@hotmail.com> on IRC (thanks!).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Move SPI code out of board_enable.c where it started its life. The SPI
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
chip finding and SPI chip accessor code is moved as well. This can be
split later if we feel like it.
The non-use of svn cp is intentional because the only history we'd have
to preserve are a few commits which were early prototypes of chip
identification code. For those who intend to look at that history, they
can look at board_enable.c revision 2853.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2857 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of the Winbond chips from being detected (trivial fix).
This is verified on real hardware and works fine now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2855 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
went wrong in one of the recent commits.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, dump support for the NSC PC87351.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
about where to send additional register dumps.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
be detected, as it needs a non-standard init sequence.
Minor other fix: Drop incorrect 0x2b from LDN 5 of the ITE IT8705F.
Signed-off-by: Robinson P. Tryon <bishop.robinson@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add notes which IDs were taken from sensors-detect (as where we lack
datasheets, thus cannot verify them) and which we support but sensors-detect
does not (yet). I'll post patches on the lm-sensors list to sync up
the detected chips between superiotool and sensors-detect.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Improve the --verbose output a bit more. Print the "Probing..." text for
all Super I/Os and if a Super I/O is not known, show the data we were
able to read from the chip (what data this is is very vendor/chip specific).
* Thus the common no_superio_found() is dropped, it's not useful.
The "read from 0x20" part was wrong for all Super I/Os other than the
NSC ones anyway.
* Winbond: For the 'olddevid' only use bits 3..0, mask away the others.
* SMSC: Print which ID registers we try to read (in --verbose mode).
* Minor cosmetic fixes.
* Rename PC8374 to PC8374L (as per datasheet).
* Rename probe_idregs_simple() to probe_idregs_nsc().
* Rename dump_readable_ns8374() to dump_readable_pc8374l().
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The help implied that writes happen by default, which they don't. Fix
the text, and say something when we dont specify any commands.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
way. It introduces a generic SPI host driver for the IT8716F Super I/O
which will enable easy SPI programming without having to care for the
peculiarities of the SPI host.
To activate probing for the IT8716F, you have to use the gigabyte:m57sli
mainboard override. SPI support will then use the gathered SPI host data
to access the SPI flash.
This has been tested sucessfully by Ward Vandewege <ward@gnu.org> on the
GA-M57SLI v2.0, which has a MX25L4005 SPI flash part.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Make the -V output more informative.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Super I/Os from SMSC. Otherwise not all of them are detected (and there
could theoretically be _two_ of them in a system, so we should probe
for both types anyway).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to ITE IT8716F Super I/O. Right now this is hardcoded to the Gigabyte
M57SLI board. It works only with rev 2.0 of the board, but it will bail
out on earlier versions, so no damage can occur.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
dump support for the SMSC DME1737 and the ASUS A8000. Random minor fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
contents in human-readable form (e.g. "COM1 enabled" etc.) instead
of the hex-table format from -d / --dump.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add common 'enter configuration mode' function for most Winbond/Fintek/ITE
chips which use the 0x87 0x87 sequence for that reason.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pure luck (and broken code elsewhere). Needs some more fixing.
Add more LDN descriptions to various Super I/Os.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Minor coding style changes and code simplifications.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Various minor fixes and improvements (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
them. Reduce code duplication a bit by improved 'no dump available' handling.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
use different config ports.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Here's what a register dump looks like on my test system:
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
No Super I/O chip found at 0x002e
No Super I/O chip found at 0x004e
Super I/O found at 0x03f0: id=0x28, rev=0x01
SMSC FDC37N769
idx 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
val 20 90 80 f4 00 00 ff 00 00 00 40 00 0e 28 01 00 00 00 00 00 02 00 01 03 00 00 00 00 00 00 80 00 00 00 00 00 00 ba 00 00 03 00 00 23 03 03 00 00
def 28 9c 88 70 00 00 ff 00 00 00 00 00 02 28 NA 00 00 80 RR RR NA NA NA 03 RR RR RR RR RR RR 80 00 3c RR RR 00 00 00 00 00 00 00 RR 00 00 03 00 00
Probing 0x0370, failed (0xff), data returns 0xff
I'm self-acking this as it's pretty simple stuff, but please let me
know if anything could be improved here, or if you think this
is not trivial enough to warrant self-acking.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generic, so that we can use it for other Super I/Os, too.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
all Super I/Os can (and should!) use this (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As there will be lots more supported Super I/Os soon, the file is
really getting way too big...
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I'm self-ack'ing this, as the origin of the code in udelay.c (and thus
the license and copyright owner) is pretty clear.
The code which is now in udelay.c was split out from flash_rom.c in r1428,
and flash_rom.c, in turn, has been around since the beginning and had a
'Copyright 2000 Silicon Integrated System Corporation' line as well as the
usual GPLv2-or-later license header.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2767 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
project (being packaged by distros, among other things).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Flesh out Makefile with all the usual stuff, e.g. install targets etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Rename it to superiotool while we're at it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The default for LDN 5 (keyboard), index 0xF0 is not 0x00
but rather 0x08 as per datasheet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No changes in content of the files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fixes minor coding style issues and prepares the table for supporting
more chips of the ITE IT87xx Super I/O family.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Common code sequences have been factored out, the code has been made
more generic, has better handling of corner cases and is actually much
shorter.
It also adds probing for almost all recent (since 1999) ITE Super I/O
chips to probe_superio. I did verify against all ITE datasheets
(including those not available any more) that the probing was
non-destructive.
For the ITE IT8712F, the complete configuration is dumped and as
comparison the default value from the data sheet is printed.
More information can be extracted easily, however this needs loads of
datasheet surfing.
This code has been tested extensively, dumping for other ITE chips will
follow as a separate patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The first byte of the flash chip was read at the start of the function
and later written back to address 0 if the flash chip was not identified
as SST28SF040, which means most of the time. This write caused corruption
of flash contents when verifying a SST49LF160C part.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M50FLW080B, M50FW080, M50FW016, M50LPW116, M29W010B flash chips made
by ST to flashrom.
The patch is based on the data sheets of the chips and has not been
tested at all.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only reading from the chips was tested; writing support is untested.
Thanks to Gürkan Sengün <gurkan@linuks.mine.nu> for testing!
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Same board enable as Asus A7V8-MX. Tested by Reinhard Max.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The previous code was pretty unreadable, undocumented and did some totally
unrelated things (such as mucking with the game port or port 0x92).
This version is tested with a 256 KB chip and should work for the
CS5530 and CS5530A.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Carl-Daniel Hailfinger