DP link rates are reported in an array of LE16 values. The current code
tries to parse them as 8-bit which doesn't get very far, causing us to
always drop into the fallback path. This patch should fix the issue
(+minor whitespace cleanup).
BUG=b:170630766
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1e03088ee2d3517bdb5dcc4dcc4ac04f8b14a391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
CBFS SAR and SAR tables in ACPI are currently supported only by Intel
WiFi devices. This change adds a check in `emit_sar_acpi_structures()`
to ensure that the PCI vendor for the device is Intel before
generating the SAR tables.
BUG=b:169802515
BRANCH=zork
Change-Id: Ibff437893a61ac9557cff243a70230f101089834
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46040
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change limits the scope of `wifi_generic_fill_ssdt()` and
`wifi_generic_acpi_name()` to generic.c since they are not used
outside of this file anymore. Also, since there is no need to split
SSDT generator into two separate functions,
`wifi_generic_fill_ssdt_generator()` is dropped and `.acpi_fill_ssdt`
directly points to `wifi_generic_fill_ssdt()`.
BUG=b:169802515
BRANCH=zork
Change-Id: I2cbb97f43d2d9f9ed6d3cf8f0a9b13a7f30e922e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46038
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, drivers/intel/wifi is a PCI driver (provides `struct
pci_driver`) as well as a chip driver (provides `struct
chip_operations`). However, there is no need for a separate chip
driver for the WiFi device since drivers/wifi/generic already provides
one.
Having two separate chip drivers makes it difficult to multi-source
WiFi devices and share the same firmware target without having to add
a probe property for each of these devices. This is unnecessary since
the WiFi driver in coreboot is primarily responsible for:
1. PCI resource allocation
2. ACPI SSDT node generation to expose wake property and SAR tables
3. SMBIOS table generation
For the most part, coreboot can perform the above operations without
really caring about the specifics of which WiFi device is being used
by the mainboard. Thus, this change drops the driver for intel/wifi
and moves the PCI driver support required for Intel WiFi chips into
drivers/wifi/generic. The PCI driver is retained for backward
compatibility with boards that never utilized the chip driver to
support Intel WiFi device. For these devices, the PCI driver helps
perform the same operations as above (except exposing the wake
property) by utilizing the same `wifi_generic_ops`.
This change also moves DRIVERS_INTEL_WIFI config to
wifi/generic/Kconfig.
BUG=b:169802515
BRANCH=zork
Change-Id: I780a7d1a87f387d5e01e6b35aac7cca31a2033ac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46036
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the addition of CBFS SAR file from
intel/wifi/Makefile.inc to wifi/generic/Makefile.inc to keep it in the
same sub-directory as the Kconfig definition.
BUG=b:169802515
BRANCH=zork
Change-Id: I7ee33232b6a07bbf929f3a79fabe89130fb6fa6f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change drops the dependency of DRIVERS_WIFI_GENERIC on
HAVE_ACPI_TABLES as the driver provides operations other than the ACPI
support for WiFi devices. Since the dependency is now dropped, ACPI
operations in generic.c are guarded by CONFIG(HAVE_ACPI_TABLES).
BUG=b:169802515
BRANCH=zork
Change-Id: I16444a9d842a6742e3c97ef04c4f18e93e6cdaa9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46037
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support in generic WiFi driver in coreboot to
generate SMBIOS data for the WiFi device. Currently, this is used only
for Intel WiFi devices and the function is copied over from Intel WiFi
driver in coreboot. This change is done in preparation for getting rid
of the separate chip driver for Intel WiFi in coreboot.
BUG=b:169802515
BRANCH=zork
Change-Id: If3c056718bdc57f6976ce8e3f8acc7665ec3ccd7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
To avoid confusion with `flashconsole` (CONSOLE_SPI_FLASH), prefix this
option with `EM100Pro`. Looks like it is not build-tested, however.
Change-Id: I4868fa52250fbbf43e328dfd12e0e48fc58c4234
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The patch allows to configure sensors with a remote diode connected
and a on-chip local temperature sensor from the devicetree for the
board that uses this HWM. According to the documentation [1], this is
done by setting the corresponding bits in the Mode Selection Register
(22h). It is necessary for some Intel processors (Apollo Lake SoC)
that do not support PECI and the CPU temperature is taken from the
thermistor.
TEST = After loading the nct7802 module on the Kontron mAL-10 [2] with
Linux OS, we can see configuration of the HWM with one sensor in
the thermistor mode:
user@user-apl:~$ sensors
coretemp-isa-0000
Adapter: ISA adapter
Package id 0: +41.0°C (high = +110.0°C, crit = +110.0°C)
Core 0: +40.0°C (high = +110.0°C, crit = +110.0°C)
Core 1: +40.0°C (high = +110.0°C, crit = +110.0°C)
Core 2: +41.0°C (high = +110.0°C, crit = +110.0°C)
Core 3: +41.0°C (high = +110.0°C, crit = +110.0°C)
nct7802-i2c-0-2e
Adapter: SMBus CMI adapter cmi
in0: +3.35 V (min = +0.00 V, max = +4.09 V)
in1: +1.92 V
in3: +1.21 V (min = +0.00 V, max = +2.05 V)
in4: +1.68 V (min = +0.00 V, max = +2.05 V)
fan1: 0 RPM (min = 0 RPM)
fan2: 868 RPM (min = 0 RPM)
fan3: 0 RPM (min = 0 RPM)
temp1: +42.5°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C) sensor = thermistor
temp4: +44.0°C (low = +0.0°C, high = +85.0°C)
(crit = +100.0°C)
temp6: +0.0°C
[1] page 30, section 7.2.32, Nuvoton Hardware Monitoring IC NCT7802Y
with PECI 3.0 interface, datasheet, revision 1.2, february 2012
[2] https://review.coreboot.org/c/coreboot/+/39133
Change-Id: I28cc4e5cae76cf0bcdad26a50ee6cd43a201d31e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39766
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops maxsleep parameter from chip config and instead
hardcodes the deepest sleep state from which the WiFi device can wake
the system up from to SLP_TYP_S3. This is similar to how other device
drivers in coreboot report _PRW property in ACPI. It relieves the
users from adding another register attribute to devicetree since all
mainboards configure the same value. If this changes in the future, it
should be easy to bring the maxsleep config parameter back.
BUG=b:169802515
BRANCH=zork
Change-Id: I42131fced008da0d51f0f777b7f2d99deaf68827
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds a call to `pci_dev_is_wake_source()` to determine and
log WiFi wake source to event log just like the Intel WiFi driver
does. This is done in preparation to merge the generic and Intel WiFi
drivers in follow-up changes.
BUG=b:169802515
BRANCH=zork
Change-Id: I20528ae1f72ca633da31e01d777c46fd5f4a337f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change uses the newly added `pci_dev_is_wake_source()` helper function
to determine and log WiFi wake source instead of assuming a hard-coded
register value to check. This is done in preparation to merge the
generic WiFi and Intel WiFi drivers in coreboot in follow-up changes.
BUG=b:169802515
BRANCH=zork
Change-Id: I9bdb453092b4ce7bdab2969f13e0c0aa8166dc0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
HPD on this bridge chip is a bit useless. This is an eDP bridge so the HPD is
an internal signal that's only there to signal that the panel is done powering up.
But the bridge chip debounces this signal by between 100 ms and 400 ms (depending on process,
voltage, and temperate). One particular panel asserted HPD 84 ms after it was powered on
meaning that we saw HPD 284 ms after power on. Assume that the panel driver will have the
hardcoded delay in its prepare and always disable HPD.
Change-Id: Iea7dd75b57fa55ec182c0bee09b0f35208357892
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Modify mrc_cache_load current to return the size of the mrc_cache
entry so that caller will know what the actual size of the data
returned is. This is needed for ARM devices like trogdor, which need
to know the size of the training data when populating the QcLib
interface table.
BUG=b:150502246
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
Change-Id: Ia314717ad2a7d5232b37a19951c1aecd7f843c27
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
`pci_dev_init()` is used to load and run option ROM on VGA class
devices (PCI_CLASS_DISPLAY_VGA). WiFi device is not a VGA class device
and hence the call to `pci_dev_init()` is not required. This change
drops the call to `pci_dev_init()` from `wifi_pci_dev_init()` in Intel
WiFi driver.
BUG=b:169802515
BRANCH=zork
Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
WiFi devices supported by the generic WiFi driver are PCIe devices
which need to be managed using the standard pci_dev_* operations to
read, set and enable resources. This change updates the
device_operations structure `wifi_generic_ops` to use the standard
pci_dev_* operations for these devices.
BUG=b:169802515
BRANCH=zork
Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Remove #include "chip.h", which is not needed and causes a build
problem in a later change. Alphabetise the #includes. Add <types.h>.
Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45968
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were writing to cbmem after memory training and then
writing the training data from cbmem to mrc_cache in ramstage. We
were doing this because we were unable to read/write to SPI
simultaneously on older x86 chips. Now that newer chips allow for
simultaneously reads and writes, we can move the mrc_cache update into
romstage. This is beneficial if there is a reboot for some reason
after memory training but before the previous mrc_cache_stash_data
call originally in ramstage. If this happens, we would lose all the
mrc_cache training data in the next boot even though we've already
performed the memory training.
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't do mmapping but still want to use the
cbmem to store the mrc_cache data in order to write the mrc_cache data
back at a later time. We are maintaining the use of cbmem for these
older platforms because we have no way of validating the earlier write
back to mrc_cache at this time.
BUG=b:150502246
BRANCH=None
TEST=reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I3430bda45484cb8c2b01ab9614508039dfaac9a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44196
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
APEI (ACPI Platform Error Interface) defines BERT (Boot Error Record
Table) memory region:
* Bootloader (firmware) generates UEFI CPER (Common Platform Error
Record) records, and populates BERT region.
* OS parses ACPI BERT table, finds the BERT region address, inteprets
the data and processes it accordingly.
When CONFIG_ACPI_BERT is defined, update FSP UPD BootLoaderTolumSize,
so FSP allocates memory region for it. The APEI BERT region is placed
on top of CBMEM, for the size of CONFIG_ACPI_BERT_SIZE.
Apart from APEI BERT region, we also have plan to add APEI HEST region
which holds OS runtime hardware error record, based on firmware
first hardware error handling model. HEST region will be reserved
same way as BERT region.
Note that CBMEM region can not be used for such purpose, the OS
(bert/hest) drivers are not able to access data held in CBMEM region,
as CBMEM is set as type 16 (configuration table).
An option considered was to reserve the BERT region under CBMEM.
However, we do not know the size of CBMEM till acpi tables are set up.
On the other hand, BERT region needs to be filled up before ACPI BERT
table is finalized.
Change-Id: Ie72240e4c5fa01fcf937d33678c40f9ca826487a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The kernel guys have found that automatic link training from this bridge
can occasionally fail and needs to be retried. They have added up to 10
retries just to be sure, so let's do the same in coreboot.
BUG=b:169535092
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I713b6851bd51d3527ed4c6e6407dee6b42d09955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45882
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`option.c` was already linked into verstage but needs `mc146818rtc.c`
to work. While we are at it, also make use of the `all` target.
Change-Id: I8f545e036962ed0716bcd3b9a5b5d06e18a367f6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45802
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coverity detects calling function spi_sdcard_do_command without checking
return value. Fix this issue by checking return value for error
handling.
Found-by: Coverity CID 1407737
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie0d28806b5c0b4c6d509e583d115358864eeff80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add CONFIG_FSP_STATUS_GLOBAL_RESET Kconfig to get correct FSP global
reset type from respective SoC Kconfig.
Supported value: 0x40000003-0x40000008, These are defined in FSP EAS
v2.0 section 11.2.2 - OEM Status Code
Unsupported value: 0xFFFFFFFF
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Idc04eb3a931d2d353808d02e62bd436b363600d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Coverity detects variable dsd going out of scope leaks the storage it
points to. Move dsd resource allocation after sanity check for
config->nvm_compact to avoid leak.
Found-by: Coverity CID 1432727
TEST=Built and boot up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I86af322dc78845b8b312b6815135336c2c56b4dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The device is a PCIe Gen2 to SD 4.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9755S and the revision
is 05.
The patch sets LTR value.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I16048dde348be248c748d50ca4a8a62c8a781430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add compatible field for NVM
Make PRP0001 as default HID if device type is INTEL_ACPI_CAMERA_NVM
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: Iad7afa7b3170982eb5d6215e766f3e98f7a89213
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This adds error checking in paths that previously ignored TPM
communication errors. We hit this case occasionally during "Checking
cr50 for pending updates"; previously we would go down this path and
eventually time out using MAX_STATUS_TIMEOUT, which is 2 minutes.
Now, we detect the failure and return with an error indication instead
of timing out after a long time. The root cause of the communication
error is an open issue.
BUG=b:168090038
TEST=booted on volteer, observed error handling when
"Checking cr50 for pending updates" fails.
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ia8a1202000abce1857ee694b06b1478e6b045069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Servers often run headless, so a missing EDID isn't a problem. However,
we still need to initialize a framebuffer for the BMC's KVM function.
Reduce the log level to BIOS_INFO to avoid confusion.
Change-Id: Ice17bf6fdda0ce34e686dbf8f3a1fa92ba869d7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change is being done for the following reasons:
1. The CONFIG_ELOG_PRERAM is unused.
2. We need to pull in elog.c into romstage because we are pulling the
mrc_cache_stash_data function into romstage.
3. Furquan says that we can rely on the linker to optimize out the
unused 4KiB buffer in the early stages of boot, which allows us to
get rid of the ELOG_PRERAM config.
BUG=b:117884485, b:150502246
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a -v
Change-Id: Id76cabc38e41e9bf79e1580a530c871a4ecef4ec
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45303
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add sn65dsi86 bridge driver to enable the eDP bridge.
Datasheet used : https://www.ti.com/lit/ds/sllseh2b/sllseh2b.pdf
Changes in V1:
- fix the dp lanes using mask
- separate out the refclk and hpd config to init function
Change-Id: I36a68f3241f0ba316c261a73c2f6d30fe6c3ccdc
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With the current timeout of 1000 cycles of 100 microsecond would see
timeout occurs on OCP Delta Lake if the log level is set to values
smaller than 8. Because the prink(BIOS_SPEW, ..) in ipmi_kcs_status()
creates delay and avoid the problem, but after setting the log level
to 4 we see some timeout occurs.
The unit is millisecond and the default value is set to 5000 according
to IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or greater
is recommended.
Tested=On OCP Delta Lake, with log level 4 cannot observe timeout
occurs.
Change-Id: I42ede1d9200bb5d0dbb455d2ff66e2816f10e86b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This ports Linux commit 71f677a91046599ece96ebab21df956ce909c456
"Handle configuration without P2A bridge".
Quote:
The ast driver configures a window to enable access into BMC
memory space in order to read some configuration registers.
If this window is disabled, which it can be from the BMC side,
the ast driver can't function.
Closing this window is a necessity for security if a machine's
host side and BMC side are controlled by different parties;
i.e. a cloud provider offering machines "bare metal".
P2A stands for primary to AHB.
Tested on Prodrive Hermes, which uses an AST2500. The machine still
boots, has a high resolution framebuffer working in EDK2, and its
boot time has been reduced by 2.5 seconds as it no longer runs into
a timeout due to disabled P2A bridge.
Change-Id: I3293dc35ae89c010154e02eff904ec3a68c96683
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On autogenerated FMAPs, there's no `UNIFIED_MRC_CACHE` region. The
current code will print a spurious error message about it, though.
Reduce the log level to BIOS_INFO to avoid confusion.
Change-Id: I0961bb2a7d2d81dc5c0d28f6e6c29b320421fc3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45076
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to pull update_mrc_cache into mrc_cache_stash_data, so moving
to end of the file to make sure update_mrc_cache is defined before.
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I9e14fec96e9dabceafc2f6f5663fc6f1023f0395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a helper to get the cached cr50 firmware version. This
information is in turn used to identify the strap configuration
supported by Cr50.
BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that the version
cached cr50 firmware version is returned.
Change-Id: Id84b152993f253878a6c133cc433a0da2c990cf2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44653
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided that
Cr50 firmware is new enough to support the register.
BUG=b:154333137
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Value stored to 'size' is never read.
Also drop unused parameter.
Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects that value assigned to variable "ret" is overwritten
before it is used. Fix the issue by returning right value.
Found-by: Coverity CID 1255942, 1241836
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0
based, so it doesn't reuse coreboot's stack, but sets up its own stack.
In contrast to all other FSP 2.0 based platforms, this stack isn't in
the CAR region, since AMD Picasso doesn't support CAR and the DRAM is
already available when the x86 cores are released from reset. Selecting
FSP_USES_CB_STACK ended up doing the right thing, but is semantically
wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso
we take the corresponding code path if ENV_CACHE_AS_RAM is false which
is only the case for non-CAR platforms.
BUG=b:155501050
TEST=Timeless build results in an identical binary for amd/mandolin,
asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases
here.
Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Latest EDK2 code inside
"UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c"
is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence
coreboot need to fill required information (package, core and thread
count).
TEST=Able to see package, core and thread information as part of FSP
debug log.
Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This patch ensures that coreboot is able to take control of APs back
by doing a full AP re-initialization after FSP-S is done.
TEST=Able to see all cores available after booting to OS using below command
when coreboot is built with USE_INTEL_FSP_MP_INIT enable.
> cat /proc/cpuinfo
Without this CL :
shows only 1 core (only BSP)
With this CL :
shows all possible cores available (BSP + APs)
Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Includes changes in mipi_camera driver to fix following issues related
to SSDT generation for IPU devices.
1. acpigen_write_device was not getting called for IPU devices
2. acpigen_pop_len was called for a generic devices without calling
acpigen_write_device
Change-Id: I309edd065719cb8250f1241898bb5854004d2a9f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device is a PCIe to eMMC bridge controller to be used in the
Chromebook as the boot disk. The datasheet name is GL9763E and
the revision is 02.
The patch sets single request AXI, disables ASPM L0s and enables SSC.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates the mipi_camera driver to handle shared power
resource between multiple cameras. This is achieved by adding a guard
variable and methods to manipulate the guard variable before calling
the actual platform method which enables or disables the resource.
PowerResource will call these guarded methods to enable or disable the
resource. This protects the shared resource from being enabled or
disabled multiple times while the other camera is using the resource.
Example:
Consider a platform where two cameras are sharing a GPIO resource 0xXX
and both the cameras calls enable and disable guarded methods for this
GPIO. Actual platform disable method for the GPIO is called only after
the last camera using the GPIO calls DSBx method and RESx becomes 0.
Scope (\_SB.PCI0)
{
Name (RESx, Zero)
Method (ENBx, 0, Serialized)
{
If ((RESx == Zero))
{
\_SB.PCI0.STXS (0xXX)
}
RESx++
}
Method (DSBx, 0, Serialized)
{
If ((RESx > Zero))
{
RESx--
}
If ((RESx == Zero))
{
\_SB.PCI0.CTXS (0xXX)
}
}
}
Change-Id: I1468459d5bbb2fb07bef4e0590c96dd4dbab0d9c
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add driver for OCP specific ipmi commands. With this driver, OCP
specific ipmi command can be used after implementing functions here.
TEST=Build with CB:42242 on Delta Lake, select Kconfig option:
IPMI_OCP and add device in devicetree to open this function.
Use ipmi-util in OpenBMC to dump raw data and check if this
function work.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I2efa85978ec4ad3d75f2bd93b4139ef8059127ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43996
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a missing newline to a printk in the max98373 driver.
BUG=none
TEST=verified BIOS boot log is properly formatted on volteer.
Change-Id: I1c989729bdc71736975901566023e0057a6d0556
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Re-organize the existing generic wifi driver into a generic wifi chip
driver. This allows generic wifi chip information to be added to the
devicetree.
BUG=None
TEST=./util/abuild/abuild
Change-Id: I63f957a008ecf4a6a810c2a135ed62ea81a79fe0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The prompts for the DPTF Kconfig options were not necessary, they should
be selected based on what DPTF implementation is being used, ASL files
or generated at runtime. It's not really meant to be fiddled with at
build-time. Also rewrite the help text for the _HID selection, to try
and make it more clear when to use y or n.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6edcabd28426916d9586d501b95b510dfc163fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43830
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the scan-build warning below:
CC romstage/drivers/mrc_cache/mrc_cache.o
src/drivers/mrc_cache/mrc_cache.c:450:26: warning: Value stored to 'flash' during its initialization is never read
const struct spi_flash *flash = boot_device_spi_flash();
^~~~~ ~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
The function can return early before the value is read. Fix this, by
getting rid of the variable, as the value is only read once.
Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09
Found-by: scan-build (clang-tools-9 1:9.0.1-12)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects dereferencing pointers that might be "NULL" when
calling acpigen_write_scope and acpigen_write_device. Add sanity
check for both of scope and name to prevent NULL pointer dereference.
Found-by: Coverity CID 1430454
TEST=Built and boot up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8ece3831bbd2641ceafbd71b9dc3db7e04a8eae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43449
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Missed one other scope operator in the DPTF cleanup. This one is for the
fan device, and without this fix, the kernel isn't able to properly
control the fan (it gets confused about whether it's ACPI 4+ compatible
or not).
BUG=b:149722146
TEST=verify /sys/class/thermal/cooling_zone0/max_state returns > 1,
and /sys/class/thermal/cooling_zone0/cur_state is writable, and writing
the value of `max_state` causes the fan to spin faster.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7bd83967ace761ddd17eaeae9c25abb0b2cbe413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Unconditionally selecting `GFX_GMA_IGNORE_PRESENCE_STRAPS` creates a
hard dependency on `MAINBOARD_USE_LIBGFXINIT`, which is undesired. Move
it out of the `if GFX_GMA` block to break this unwanted dependency.
TEST=Build for Librem 13v4 with no graphics init successfully.
Change-Id: I53e132c209c065068f20959fa1a6f5195f5fe766
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The previous DPTF patch train missed the proper scope operator around
all of the TSR options. Without this, the optional GTSH and/or _STR
Methods end up in the wrong scope.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the initial DPTF refactor, the scope of the TCPU device was
incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the
way that the acpi_inject_dsdt() callback currently works (it injects
contents before the dsdt.aml file), the Scope where the TCPU
device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing
games with *when* things are defined in the DSDT, switch to defining all
of the DPTF devices in the SSDT.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new driver for AMD I2S machine device. Currently,
this device is added as part of `acp_fill_ssdt()` in Picasso, but with
addition of this driver, this device can be added just like any other
device in the devicetree.
BUG=b:157708581
Change-Id: I49d1a867d7941397acca1054632b6ad855a021de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We only want to return an ACPI name for a USB port if the controller
physically has the port. This has the desired side effect of making the
usb_acpi driver skip generating an ACPI node for a device which has
no port. This prevents writing an invalid SSDT table which the OS then
complains about.
BUG=b:154756391, b:158096224
TEST=Boot picasso trembyle and verify HS05, HS06 and SS05 are no longer
generated. Also checked the logs and saw the devices being ignored.
\_SB.PCI0.LPCB.EC0.CREC.TUN0: Cros EC I2C Tunnel at GENERIC: 0.0
\_SB.PCI0.LPCB.EC0.CREC.MSTH: Cros EC I2C Tunnel at GENERIC: 1.0
\_SB.PCI0.LPCB.EC0.CREC.ECA0: Cros EC audio codec at GENERIC: 0.0
\_SB.PCI0.PBRA.XHC0.RHUB.HS01: Left Type-C Port at USB2 port 0
\_SB.PCI0.PBRA.XHC0.RHUB.HS02: Left Type-A Port at USB2 port 1
\_SB.PCI0.PBRA.XHC0.RHUB.HS03: Right Type-A Port at USB2 port 2
\_SB.PCI0.PBRA.XHC0.RHUB.HS04: Right Type-C Port at USB2 port 3
xhci_acpi_name: USB2 port 4 does not exist on xHC PCI: 03:00.3
xhci_acpi_name: USB2 port 5 does not exist on xHC PCI: 03:00.3
\_SB.PCI0.PBRA.XHC0.RHUB.SS01: Left Type-C Port at USB3 port 0
\_SB.PCI0.PBRA.XHC0.RHUB.SS02: Left Type-A Port at USB3 port 1
\_SB.PCI0.PBRA.XHC0.RHUB.SS03: Right Type-A Port at USB3 port 2
\_SB.PCI0.PBRA.XHC0.RHUB.SS04: Right Type-C Port at USB3 port 3
xhci_acpi_name: USB3 port 4 does not exist on xHC PCI: 03:00.3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia645380bea74f39fd94e2f9cbca3fcd4d18a878e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to use ugly preprocessor here when regular C conditional
statements will work just fine.
Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43268
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can use xhci_for_each_ext_cap to inspect the xHC so we generate the
correct number of device nodes.
Scope (\_SB.PCI0.PBRA)
{
Device (XHC1)
{
Name (_ADR, 0x0000000000000004) // _ADR: Address
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x1F,
0x03
})
Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Device (HS01)
{
Name (_ADR, 0x01) // _ADR: Address
}
Device (HS02)
{
Name (_ADR, 0x02) // _ADR: Address
}
Device (SS01)
{
Name (_ADR, 0x03) // _ADR: Address
}
}
Name (_S0W, Zero) // _S0W: S0 Device Wake State
Name (_S3W, 0x04) // _S3W: S3 Device Wake State
Name (_S4W, 0x04) // _S4W: S4 Device Wake State
}
}
BUG=b:154756391
TEST=Boot trembyle and look at ACPI table. See all xHCI nodes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I9311dd07b8259384badec65da649fa0cf2da1e01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43267
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I7f06ea45f90d502053c52ea0b7cd7aa6d52295c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43266
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
Nothing is selecting this driver. Drop it before it grows moss.
Change-Id: I9e2ba205154a9b37455c522721f5eb2ef9d76b40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Iebd9080cd0e859dce5e6c5398429c38d1aa075dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Iff5007256fedebd98082a575773d7de181b321ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
\_SB.DPTF.IDSP adverties to the DPTF daemon which policies the
implementation supports. Added a new acpigen function to figure out
which policies are used, and fills out IDSP appropriately.
Change-Id: Idf67a23bf38de4481c02f98ffb27afb8ca2d1b7b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
DPTF has several options on how to control the fan (fine-grained speed
control, minimum speed change in percentage points, and whether or not
the DPTF device should notify the Fan if it detects low speed).
Individual TSRs can also set GTSH, which is the amount of hysteresis
inherent in the measurement, either from circuitry (if analog), or in
firmware (if digital).
BUG=b:143539650
TEST=compiles
Change-Id: I42d789d877da28c163e394d7de5fb1ff339264eb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds support for emitting the PPCC table, which describes
the ranges available as knobs for DPTF to tune. It can support min/max
power, min/max time window for averaging, and the minimum adjustment size
(granularity or step size) of each power limit. The current implementation
only supports PL1 and PL2.
BUG=b:143539650
TEST=compiles
Change-Id: I67e80d661ea5bb79980ef285eca40c9a4b0f1849
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds support for generating the _FPS table for the DPTF Fan
object. The table describes different levels of fan activity that may be
applied to the system in order to actively cool it. The information
includes fan speed at a (rough) percentage level, fan speed in RPM,
potential noise level in centibels, and power in mA.
BUG=b:143539650
TEST=compiles
Change-Id: I5591eb527f496d0c4c613352d2a87625d47d9273
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change generates the DPTF TCHG.PPSS table in the SSDT. This table
describes different charging rates which are available to use. DPTF
can pick different rates in order to passively cool (or not) the
system.
BUG=b:143539650
TEST=compiles
Change-Id: I6df6bfbac628fa4e4d313e38b8e6c53fce70a7f2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds support for DPTF Critical Policies, which are consist
of Method definitions only. They are `_CRT` and `_HOT`, which are
defined as temperature thresholds that, when exceeded, will execute a
graceful suspend or a graceful shutdown, respectively.
BUG=b:143539650
TEST=compiles
Change-Id: I711ecdcf17ae8f6e653f33069201da4515ace85e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds support for emitting the Thermal Relationship Table, as
well as _PSV Methods, which together form the basis for DPTF Passive
Policies.
BUG=b:143539650
TEST=compiles
Change-Id: I82e1c9022999b0a2a733aa6cd9c98a850e6f5408
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds support for generating the different pieces of DPTF
Active Policies. This includes the Active Relationship Table, in
addition to _ACx methods.
BUG=b:143539650
TEST=compiles
Change-Id: Iea0ccbd96f88d0f3a8f2c77a7d0f3a284e5ee463
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In this DPTF implementation, the participant device objects are written
into the DSDT with only minimal Names attached (_HID/_ADR, _STA, _UID,
PTYP, and _STR). All other Methods & Names will be written into the
SSDT. If a device is not used in any policy, then its _STA is set to
return 0 ("off").
BUG=b:143539650
TEST=Compiles.
Change-Id: Ief69a57adce9ee0b19056ce6a11ed8a5b51b3f87
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change adds support function to parse entries in the devicetree to
generate PowerResource entries for the MIPI camera.
Change-Id: I31e198b50acf2c64035aff9cb054fbe3602dd83e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41624
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the mipi_camera driver to handle acpi_name based on
device_type, if acpi_name is not set in the devicetree and moves some of
the common code to separate methods.
Change-Id: I15979f345fb823df2560db269e902a1ea650b69e
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As the booting the system can be delayed for a noticeable amount of
time, often 60 seconds is the default, this is not a debug message.
Chose log level BIOS_INFO.
Change-Id: I941792148820c0e1d3fbc80197125fee8cedf09f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Fix integer with different size to pointer conversion on x86_64.
Change-Id: Ic06a32d549b694310f4c724246f28fed15acf83f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42983
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For historical reasons, Windows has issues with certain names being
used for files and directories, 'con' or 'CON' being one of
them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in
order to work around this issue.
TEST=built volteer (only user of this driver as of now)
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
It implements the SMBIOS IPMI FRU mapping table defined in
https://www.opencompute.org/documents/facebook-xeon-motherboard-v31
22.3 SMBIOS FRU mapping table.
Mainboard needs to configure the correct values for FRU_DEVICE_ID and BMC_KCS_BASE.
For type 11 string 1 to 6 are common and implemented in this driver, the
rest are project dependent and can be added in the mainboard code.
Tested on OCP Tioga Pass.
Change-Id: I08c958dfad83216cd12545760a19d205efc2515b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40308
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would
add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION
when PLATFORM_USES_FSP2_0 is selected.
Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility
can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120"
Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Replace uses with MAINBOARD_HAS_LPC_TPM, if drivers/pc80/tpm
is present in devicetree.cb it is necessary to always include
the driver in the build.
Change-Id: I9ab921ab70f7b527a52fbf5f775aa063d9a706ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
It's necessary to run IPMI commands in romstage for writing error SEL
such as memory initialization error SEL, and also for other usages
such as starting FRB2 timer, OEM commands, etc.
Add CONFIG_BMC_KCS_BASE for BMC KCS port address that can be used
across romstage and ramstage.
Change-Id: Ie3198965670454b123e570f9056673fdf515f52b
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40234
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per ACPI spec, GpioIo does not have any polarity associated with
it. Linux kernel uses `active_low` argument within GPIO _DSD property
to allow BIOS to indicate if the corresponding GPIO should be treated
as active low. Thus, if GPIO has active high polarity or if it does
not have any polarity associated with it, then the `active_low`
argument is supposed to be set to 0.
Having a `polarity` field in acpi_gpio seems confusing because GPIOs
might not always have polarity associated with them. Example, in case
of DMIC-select GPIO where 0 means select DMIC0 and 1 means select
DMIC1, there is no polarity associated with the GPIO. Thus, it would
be clearer for mainboard to use macros without having to specify a
particular polarity. In order to enable mainboards to provide GPIO
information without polarity for GpioIo usage, this change also adds
`ACPI_GPIO_OUTPUT` and `ACPI_GPIO_INPUT` macros.
BUG=b:157603026
Change-Id: I39d2a6ac8f149a74afeb915812fece86c9b9ad93
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proposal for gpio_regulator usage in ACPI never got accepted upstream
for Linux kernel. So, the gpio_regulator driver in coreboot remains
unused. This change drops this unused driver.
Change-Id: Ia1e0ae4f955b9ffc8346d957f755499419d8cbc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coverity detects dereferencing pointers that might be "NULL" when
calling acpigen_write_scope and acpigen_write_device. Add sanity
check for both of scope and name to prevent NULL pointer dereference.
Found-by: Coverity CID 1429979, 1429982
TEST=Built and boot up to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If17d12861f562dc0d6c98a5c91a9d3c0360ca2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42835
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not all FSPs based on FSP 2.1 supports the feature of external PPI
interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE.
Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is
selected.
Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake).
Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Implemented according to IPMI "Platform Management FRU Information
Storage Definition" specification v1.0 for reading FRU data Chassis
Info Area.
Tested on OCP Tioga Pass.
Change-Id: Ieb53c20f8eb4b7720bf1fe349e6aaebaa4c37247
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40306
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
This change will add these files to verstage only if the verstage
architecture is X86 - either 32 or 64 bit.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I797b67394825172bd44ad1ee693a0c509289486b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42062
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Having speparate types for the status register with three and four block
protection bits respectively doesn't really make sense, it's the same
size either way just a different representation, so one union type will
do.
This allows us to de-duplicate the status register read in
winbond_get_write_protection as well as removing another layer of union
in 'struct status_regs'.
Change-Id: Ie99b98fb6762c8d84d685b110cfc2fd5458b702e
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42111
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPI_WRITE_PROTECTION_REBOOT seems to be a Winbond thing, other vendors
such as Macronix only support permanent protection but conditional on
the WP# pin state.
Change-Id: Iba7c1229c82c86e1303d74c7bc8f89662b5bb58c
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41747
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The former is not standard C, and we primarily use the latter form.
Change-Id: Ia7091b494ff72588fb6910710fd72165693c1ac5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the introduced functions and verify pointers in the SMMSTORE.
Make sure to not overwrite or leak data from SMM and update the
documentation as well.
Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor. With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.
As a generalization, remove all-y for CONFIG_ARCH_xx guarded
makefiles.
BUG=b:158124527
TEST=Build and boot on Trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Add multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Add FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Add FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, configuring and reviewing DPTF parameters is difficult
because DPTF tables and methods are defined in static ASL files, and are
littered with #ifdefs which both define parameters and influence
behavior (e.g., whether a method is included or not). This patch train
is an effort to bring DPTF support to our ACPI DSDT/SSDT generation
framework.
This first patch is very minimal, and includes only creation of the
DPTF device (in the DSDT).
BUG=b:143539650
TEST=compiles (later tests get more comprehensive).
Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the check for NvsBufferPtr in S3 resume case to
happen just before FSP-M is called. This allows SoC/mainboard code to
set NvsBufferPtr if it doesn't use the default MRC cache driver.
BUG=b:155990176
Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
Not strictly required for binaryPI boards, but do this for
consistency.
Change-Id: Id0bbbfb6f695c4bb920bc57a1e9362a23884efb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Only Winbond parts seem to support making status register writes
volatile. So this flag should not be exposed in the generic interface.
Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When MRC cached data update is performed, messages are written to
event log, which is flash based. For system that does not have flash
based event log, the messages are lost.
Added corresponding BIOS_DEBUG messages.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1ef4794151fea7213c8317ddc898b0e37da280b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41981
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
