This is a geode LX board. There are timing settings that are not right
yet, we are still trying to get our board to boot Linux :-)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
A trivial one-liner for the CPU I happen to have. The sales docs said it's
a "G1 revision", but the Rev F code works just fine.
Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Generic driver for pretty much all known Standard Microsystems Corporation
(SMSC) Super I/O chips.
Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.
So far only the ASUS A8000 has been tested on real hardware!
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(SMSC) Super I/O chips.
Most of the SMSC Super I/O chips seem to be similar enough (for our
purposes) so that we can handle them with a unified driver.
So far only the ASUS A8000 has been tested on real hardware!
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Now uses CAR.
New code for SPD-less memory implementation.
Updated IRQ routing.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the system boot to a command line.
This patch comments out the code to set up the vga framebuffer to allow
the system to boot, without this fix the system hangs during elfboot.
The only line that is absolutely necessary to change is the SMRAM setup,
however I've commented out all vga setup to make it very obvious to both
the kernel/payload and anyone looking at the code that vga isn't
currently working. This setup might also be better handled in
northbridge.c, if it doesn't need to be done before ram init, yet
another reason to comment it all. In the future, LinuxBIOS needs to be
told that the graphics memory area, 1mb or 512kb (at the user or
developer's option), is reserved for the onchip vga, but I'm not sure if
it's taken at the top or bottom of the memory, yet. LB may also need to
set a base address for the AGP aperture and/or be told that range is
reserved as well, whether this was originally the job of the system bios
or vga bios is still a mystery. It also corrects the number of entries
in irq_tables.c, without this fix the kernel would probably complain and
hang due to unmapped IRQs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
more than just one way. This version should be (more) correct.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
southbridges, along with the Asus MEW-VM. With this, my machine attempts to
boot linux, but does so very slowly and fails during the boot process, probably
because of the irq tables.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The DB800 is the AMD LX Reference Design Kit platform.
For details see: http://www.amd.com/geodelxdb800
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Still hardcoded for Tyan S1846.
This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both are very similar, thus both use the JUKI-511P target.
Linux with patches from Juergen Beisert
(http://www.linuxbios.org/pipermail/linuxbios/2007-May/020932.html)
boots and work fine (ide, usb, ethernet, serial, keyboard and sound
work normally).
Problems:
- Filo loads a bzImage only from ide0 (ide1 doesn't work yet).
- Video doesn't work, yet.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Linux booted with the proprietary BIOS reports 2e.f as PS/2 mouse
in the output of 'lspnp -v'.
- The floppy on 2e.f was a typo, should have been 2e.e from the beginning.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Super I/O part was incorrect.
Also, add ide0_enable/ide1_enable variables, and enable both the
primary and secondary IDE interface per default.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
return that skipped the disable code. This patch removes the return and
fixes the UART disable code.
The problem was that the disable code was ORing bits into the Legacy_IO
MSR causing issues with the LPC SIOs init code that would manifest as a
hang because the IO would not be decoded correctly. ANDing to clear the
bits fixes the issue.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In a mainboard's Config.lb file you can configure whether the primary
and/or secondary IDE interfaces shall be enabled.
Also, various fixups in the rest of the southbridge code, most notably
the early SMBus code, plus some documentation improvements.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
All other delays are so low that we get away with just waiting 1us.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
available on all boards, regardless of what DIMMs you use.
Tested on the Tyan S1846, works fine.
- Properly set the PAM registers to allow the region from 768 KB - 1 MB
to be used as normal RAM (required for the above).
- Document all of this properly. Add/improve other documentation, too.
- Simplify and document code in northbridge.c.
- Cosmetics and coding style.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
accessible (but not writable), so that reading/loading a payload
from that area can work (for instance).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It moves the complete naming functionality to
src/cpu/amd/model_fxx/processor_name.c.
The current code sets the processor name string twice for Rev. F CPUs.
In src/cpu/amd/model_fxx/model_fxx_init.c the function
amd_set_name_string_f is called first. Several lines later
init_processor_name is called which doesn't recognize newer CPUs and
actually programs incorrect values, thus overwriting the previously set
CPU name. For example, this resulted in identifying an Opteron 2218 as a
Turion processor.
This patch removes the amd_set_name_string_f function from
src/cpu/amd/model_fxx/model_fxx_init.c and adds support for Rev. F CPUs
to src/cpu/amd/model_fxx/processor_name.c as described in the Revision
Guide for AMD NPT Family 0Fh Processors, AMD Document ID 33610 Rev 3.00,
October 2006.
Signed-off-by: Sven Kapferer <skapfere@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the new src/southbridge/amd/cs5536 code completely replaces it.
The Artecgroup dbe61 board currently uses it, but that is broken anyway
at the moment. A fix to use the new CS5536 code for it is being worked on.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add missing IT8712F_GPIO definition.
- Add functions for entering and exiting MB PnP mode.
- Add some more device init lines to pnp_dev_info[].
Signed-off-by: Philipp Degler <pdegler@rumms.uni-mannheim.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- the Transmeta TM5800 northbridge
- the Densitron DPX114 mainboard (the only one using the TM5800)
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
devices conflicting with the northbridge devices on PCI bus 0.
Signed-off-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CPU: vendor AMD device
30ff2
CPU: family 0f, model 3f, stepping 02
All I know is this makes it boot when it didn't before, YMMV.
Signed-off-by: Jeremy Jackson <jerj@coplanar.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
hardware, rather than always on at full speed. Set temperature treshold values
to safe defaults, rather than the not-so-safe power-on defaults.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Yinghai Lu <yinghailu@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is nothing more than the result of running
indent -npro -kr -i8 -ts8 -sob -l80 -ss -ncs adm1027.c
Signed-off-by: Ward Vandewege <ward@gnu.org>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
function (power-on strapping). Although this is already done in superio.c,
it's not being done when w83627thf_early_serial.c is executed.
As such, no console_init() without it.
Signed-off-by: Roger Zauner <roger@eskimo.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
setup as the host on USB port4. In client mode the headers remain
available. Also fixes an outb to 0x80 to use the post_code() function.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
With CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0, 1 million outb():s are used
for timer calibration, which takes about one second.
All EPIA-M boards have timer2 so we use it to boot faster.
Only some EPIA boards have the Nehemiah CPU with timer2 so we default to IO
calibration but add the TSC options so that they can be set in Config.lb.
src/mainboard/via/epia*/reset.c is dead code (entire file within #if 0) so we
set HAVE_HARD_RESET=0 for both boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
on the 440BX are 8 MB units we need to shift left by 13 to get it into KB.
Signed-off-by: Ceri Coburn <ceri.coburn@gmail.com>
Signed-off-by: Roger Zauner <roger@eskimo.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
able to find to test with the Epia.
Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(power-on strapping). Although this is already done in superio.c, it's
not being done when w83977tf_early_serial.c is executed. As such, no
console_init() without it.
Signed-off-by: Roger Zauner <roger@eskimo.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2645 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
problems with the asi/mb_5bmlp (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2644 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
minor changes, to bring them up to par. It also should remove (but might
just clean out) the irq_tables.c from both boards, because they were
just copied from Via Epia to begin with, and weren't usable. As far as I
can tell, these are the only changes needed to the targets for now,
aside from fixups to reset.c when the time comes. Both have been build
tested, but not checked on hardware since I don't have it. I have left
Uwe as the copyright holder since the only changes I've made are trivial.
Signed-off-by: Corey Osgood <corey_osgood@verizon.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2642 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the IGEL Winnet III thin client.
It boots a Linux kernel, but there are some problems. The login
prompt is never reached, it simply hangs at some point.
One possible reason is the IRQ table, which needs fixing.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2641 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the 5c register in the southbridge so that interrupts are routed
correctly.
With this patch, ethernet works quite well.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
adds a symbol to the model_lx/cache_as_ram.inc, and modifies some
files in the mainboard directory. This patch has been tested but there
is a remaining problem which I am tracking down. Expect one more patch
to "get it all working".
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
-This line, and those below, will be ignored--
M cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I'm self-acking as this is pretty trivial. I tested both a normal build
and an abuild-run, and nothing breaks.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
broke and stopped FILO
from being able to boot.
The fix is a simple one line change plus a comment to
src/mainboard/via/epia/auto.c to write to the IDE
configuration register 0x42 . This has always been done here, however
at some point
something broke it.
The same register was also being set correctly in ide_init(), however
for some reason
this does not work. Possibly the register needs to be set before the IDE
peripheral is enabled
or maybe it is a timing issue.
The section of code in ide_init() (
src/southbridge/via/vt8231/vt8231_ide.c ) that does
write to register 0x42 has been commented out as it is superfluous
and I have added a comment to indicate the reason, should someone at a
future date wonder
why.
I have also changed the default COM speed from 19200 to 115200 in
src/mainboard/via/epia/Options.lb
There has been mention before about the EPIA board not being able to use
115200 but I have seen
no such problems with my board.
Signed-off-by: Ben Hewson <ben@hewson-venieri.com>
This patch worked for me and allowed me to boot Debian kernel
2.5.16-4-486 on an epia 800 mhz system. It is able to consistently get
through the initialization and start init now.
However, after that it crashes at various points in the boot process.
Acked-by: Alex Mauer <hawke@hawkesnest.net>
Note from comitter: I am commiting this, although:
1. it's not the exact right way to fix it up, the chip.h for the sb
should change
2. Alex reports problems, which are almost certainly memory issues.
But it is as close as we've gotten. I can't test it.
Ron Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Geode changes.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
AMD GX and LX processors. This aguments the previous code, which was
very specific to the OLPC platform with general purpose support and
better integration with the VSA and CPUs.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Geode LX platform, including memory and graphics. (rediffed for whitespace)
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
based on the Geode LX processor. The Norwich is the canonical
Geode reference, and will server as a good basis for other
Geode based platforms.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The following original authors agreed to the license:
- Ronald G. Minnich <rminnich@gmail.com>
- Indrek Kruusa <indrek.kruusa@artecdesign.ee>
- Stefan Reinauer <stepan@coresystems.de>
- Andrei Birjukov <andrei.birjukov@artecdesign.ee>
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
as that is not RAM but used for other stuff.
First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.
Use a real payload (FILO) per default now.
Note: this cannot boot a payload, yet, but it gets a lot further now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For files derived from the Linux kernel we merely add a small header
which states the origin of the file and the copyright owners of the
modifications to the file.
We know all files from Linux are licensed under the GPLv2.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Comment out code which currently doesn't compile. Needs fixing later.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Ronald G. Minnich