Based on updated schematics, change polarity of USI_INT, and add
the reset and enable GPIOs to the touchscreen ACPI node. The stop
GPIO can't be used with the current implementation of _ON, as the
way it's wired will cause power sequencing to fail.
BUG=b:137133194, b:138240502
BRANCH=none
TEST=Compiles, don't have next board rev to test with
Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Enable I2C0 in fleex then verify EMR function successfully
BUG=b:135968368
BRANCH=octopus
TEST=EMR function working normally with I2C0 in Grob360S.
Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The 'Jacuzzi' is a different base board that will share most of Kukui
design. For AP firmware, there will be only a few changes expected,
mostly in display (for MIPI bridge) and EC/keyboard so we want to create
it as variants inside Kukui folder, not forking a new directory.
BUG=b:137517228
TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build.
Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is based on the grunt variant.
BUG=b:135551210
BRANCH=none
TEST=emerge-grunt coreboot chromeos-bootimage
Ensure that image-treeya.*.bin are created
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change provides an implementation of variant_devtree_update() for
kindred that disable eMMC controller when SKU ID = 1 or 3
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1 or 3
Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We would like to wake eve up in suspend from an MKBP event. This commit
simply enables MKBP events to wake the system in suspend using the
existing host event interface. There is an accompanying series of
patches in the EC firmware for eve that will allow a MKBP wake mask to
be configured.
BUG=chromium:786721
BRANCH=firmware-eve-9584.B
TEST=Build and flash eve, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable unused USB devices in the device tree so that the concerned ACPI
objects do not get exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based
on port status and the concerned ACPI objects are not exported.
Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add devicetree configuration for USB devices so that USB Port
Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects
can be exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are
exported for the configured USB devices in the SSDT table.
Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We would like to wake nocturne up in suspend from an MKBP event. On
Nocturne, MKBP events are notified to the host via a GPIO from the EC,
EC_INT_L. However, the AP cannot wake from suspend from this GPIO.
Therefore, we'll use the host event interface to wake the system
instead.
This commit simply enables MKBP events to wake the system in suspend.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down.
As per schematics SD host controller SD_WP pin is not connected to
uSD card connector. Configured gpio pin as NF1 with internal pull down
in order to overcome gpio default state in hatch which makes SoC
SD_WP pin is enable.
BUG=b:137729527
BRANCH=None
TEST=Able to write/read data to/from sd card after mounting card device.
Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Following changes are done to enable ALC1011 codec on Helios
1. ACL1011 4 devices to I2C4
2. GPIO H13 is set to GPO as per schematics
Verified SSDT table and i2cdetect from kernel.
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Change-Id: I0d71e3bd2d4493d059a33023c1afe1b630181d4f
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides an implementation of variant_memory_sku() for
helios that overrides memory ID 3 and 4 to 0 and 1 to workaround the
incorrect memory straps in hardware for board id 0 and unknown.
BUG=b:133455595
Change-Id: I38fab1f91decac5d0a146e5a6c74e88f677af305
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This change adds support for variant_memory_sku() that allows variant
to return memory SKU ID. Current implementation of memory_sku() is
renamed to weak implementation of variant_memory_sku(). Functionally
this change should be the same as before for all hatch variants. This
function will be overriden by helios in a follow-up CL.
BUG=b:133455595
Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Autoport generates these structures as static so let's make it consistent.
See also commit 128205fd with Change-Id
I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve
gpio.c generation").
Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes VGPIO_3 GPIO PIN output and low independent of
cnvi is connected or not.
BUG=b:123062346
BRANCH=None
TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low.
Change-Id: I629b99676f56747de1b244724709e14069250097
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These configuration files can be used to build Kodama firmware.
BUG=b:135490566
TEST=check variant: kodama via make menuconfig; make -j
Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elan's touchpad requires min 0.3us data hold time.
To fine tune the data hold time of i2c1 to meet
specification of Elan's touchpad.
BUG=None
BRANCH=None
TEST=Verified data hold time of i2c1 is around 320ns
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix
overridetree.cb to advertise the right IRQ.
Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluebird needs to use different SAR values than Casta.
Bluebird sku id is 2.
CQ-DEPEND=CL:*1435310
BUG=b:129725065
BRANCH=octopus
TEST=build
Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the AC/DC loadline values for all domains. Using the same
values as in arcada.
BUG=None
BRANCH=None
TEST=Build and Boot hatch EVT
Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.
BUG=b:136987483
TEST=emerge-kukui coreboot
Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
increase reset off delay time
Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.
BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen
Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.
BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.
Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.
BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config. Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.
BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
through "mosys eventlog list" that the wake source is the trackpad.\
3. Run "echo mem > /sys/power/state", wait until device goes into S3,
click trackpad to ensure device wakes.
Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.
BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
sure can move cursor and wake by clicking on the trackpad
after running powerd_dbus_suspend.
Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct i2c address of trackpad. It should be 0x20.
BUG=None
BRANCH=None
TEST=Verified trackpad works on pre-evt system
Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
A FPMCU power-control pin (GPP_C11) is added to the latest
hatch reference schematic.
Even though this is not implemented in hatch rev1 board, the future
hatch family boards with FPMCU should all have this control pin.
On the old boards without this control pin, GPP_C11 is a floating TP,
and thus this patch should be backward-compatible.
BUG=b:130307667, b:135216932
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no need to add internal termination (PU/PD) on the
not-connected pads. This change gets rid of the terminations on the NC
pads.
Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Garg proto build has 3 SKUs:
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Cq-Depend: chrome-internal:1380847
Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This does the following:
- select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1)
- Remove stale Kconfig option on intel/saddlebrook
- select SOC_INTEL_KABYLAKE on intel/kblrvp
Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Increase the size of bootblock from 96K to 128K.
Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is already an external pull-up/down resistor tied to
this pin to identify if the board is single-channel or
dual-channel memory SKU.
BUG=b:135496271
BRANCH=none
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly
to get faster boot process.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RTC so that we can see correct timestamp in CrOS eventlogs.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS
BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.
Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb
Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Move the memory strap gpios to variant/gpio.h, as the memory straps
are different for helios.
Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Helios has a number of GPIO changes w/r/t to its baseboard.
Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452
BRANCH=none
TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change tcc offset from 0 to 10 degree celsius for bloog.
BUG=b:135225497
BRANCH=octopus
TEST=Build and verify test result by thermal team.
Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Memory id's are 1-indexed for DDR4, so we need to check that the SPD
index is non-zero before converting it to the 0-indexed value in the
bitmap.
Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1387028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing
devices to wake up on pen insertion instead of removal. Changed to
EV_ACT_DEASSERTED.
BUG=b:134547896
BRANCH=none
TEST=Verified in OS, device only wakes up on pen removal
Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One variant is asking for support for 16G 2666 LPDDR3, so adding
generic SPD for that.
BUG=b:133455595
BRANCH=None
TEST=None as this is not being used yet
Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
One variant is asking for support for 8G 3200 DDR4, so adding generic
SPD for that.
BUG=b:132920013
BRANCH=None
TEST=None as this is not being used yet
Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wisley Chen