Commit graph

50 commits

Author SHA1 Message Date
Pratik Prajapati
03a2353df6 soc/intel/apollolake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:02 +00:00
V Sowmya
752dc8e425 soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
Rename BAR0 and BAR2 SRAM base and size macros to align with the spec.
* PMC_SRAM_BASE_0 -> SRAM_BASE_0
* PMC_SRAM_SIZE_0 -> SRAM_SIZE_0
* PMC_SRAM_BASE_1 -> SRAM_BASE_2
* PMC_SRAM_SIZE_1 -> SRAM_SIZE_2

Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20539
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-15 23:11:16 +00:00
Furquan Shaikh
ea4ece61b6 soc/intel/apollolake: Enable UART debug controller on S3 resume
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug controller is enabled.

2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.

3. Provide helper functions required by intel/common UARRT driver for
enabling controller on S3 resume.

BUG=b:64030366

Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20888
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10 16:25:14 +00:00
Hannah Williams
a61884a8a1 soc/intel/apollolake: Add CNVI and PCIE IRQs for GLK
Change-Id: I0387ccf6970e6169cbebd232ae210731338d0900
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/20755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28 16:27:53 +00:00
Martin Roth
b4560cd523 Update files with no newline at the end
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:16 +00:00
Hannah Williams
3ff14a0c85 soc/intel/apollolake: Bring in delta for GLK SOC
Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21 03:59:09 +00:00
Mario Scheithauer
c2363d0fa4 soc/intel/apollolake: Implement _PIC method into ACPI
The _PIC method is called by the OS to choose between interrupt routing
via the i8259 interrupt controller or the APIC.

Change-Id: I2bc16f9c096c095c02de3692e76c0906cec54cb5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20 04:44:41 +00:00
Hannah Williams
12bed18951 soc/intel/apollolake: Use common gpio for apollolake
No regression observed on a APL platform

Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/19949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-03 23:29:49 +00:00
Barnali Sarkar
9e55ff6a87 soc/intel/apollolake: Rename ACPI Base Address and Size Macro
Rename these two Macros to help use Common Code -
ACPI_PMIO_BASE --> ACPI_BASE_ADDRESS
ACPI_PMIO_SIZE --> ACPI_BASE_SIZE

Change-Id: I21125b7206c241692cfdf1cdb10b8b3dee62b24a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20038
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09 19:27:14 +02:00
Martin Roth
e18e6427d0 src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07 12:09:15 +02:00
Subrata Banik
d18b53f45d soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
Systemagent common code will use MCH_BASE_ADDRESS macro,
hence cleaning current APL code to adhere such changes.

Change-Id: Iace1cf786b08221c3955101186509ac5161c3841
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-01 21:48:43 +02:00
Furquan Shaikh
a0729d9a56 soc/intel/apollolake: Change IOSF_BASE_ADDRESS to PCR_BASE_ADDRESS
With recent change to use common block PCR (ccd8700c),
IOSF_BASE_ADDRESS was renamed to PCR_BASE_ADDRESS. However, SD card
change (99ce8a9b) was not rebased on top of it, so IOSF_BASE_ADDRESS
slipped into the tree. Fix this by replacing all occurrences of
IOSF_BASE_ADDRESS by PCR_BASE_ADDRESS.

Change-Id: I40eb07be306035c940fc960896e0807d6c73bafa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19277
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-13 22:16:21 +02:00
Venkateswarlu Vinjamuri
99ce8a9bba soc/intel/apollolake: Set sdcard card detect (CD) host ownership
Currently sdcard CD host ownership is always owned by the GPIO driver.
Due to this sdcard detection fails during initial boot process and OS
fails to boot from sdcard.

This implements change in host ownership from acpi to GPIO driver when
kernel starts booting.

BUG=b:35648535
TEST=Check OS boot from sdcard.

Change-Id: I042a8762dc1f9cb73e6a24c1e7169c9746b2ee14
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18947
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13 19:50:34 +02:00
Subrata Banik
ccd8700cac soc/intel/apollolake: Use common PCR module
This patch use common PCR library to perform CRRd and CRWr operation
using Port Ids, define inside soc/pcr_ids.h

Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-10 20:05:35 +02:00
Zhuo-hao Lee
07f60aa56f soc/intel/apollolake: Reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Apollo Lake system such as Snappy.
The cause is the Linux Kernel setting the firmware reset time to
100 ms by default.

This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.

BUG=b:35774937
BRANCH=none
TEST=update snappy coreboot and test i/o latency is under 100ms

Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Change-Id: Idcfe4252b20bead15c2e5b9cb000ff797295f06a
Reviewed-on: https://review.coreboot.org/18806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17 03:36:09 +01:00
Venkateswarlu Vinjamuri
6dd7b402d5 soc/intel/apollolake: Add PM methods to power gate SD card
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.

This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.

Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.

CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.

Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-03-10 11:11:13 +01:00
Lijian Zhao
37742f6870 soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.

BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.

Change-Id: Ib0a300febe1e7fc1796bfeca1a04493f932640e1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/17181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-11-07 20:14:32 +01:00
Furquan Shaikh
5d0847f757 Revert "soc/intel/apollolake: Add pmc_ipc device support"
This reverts commit 28821dbb22.
(https://review.coreboot.org/16649)

This change causes the kernel to boot really slow. Maybe there is an
interrupt storm that prevents the kernel from making any
progress. Reverting until the proper kernel dependency is met.

BUG=chrome-os-partner:57364
BRANCH=None
TEST=Kernels boots to prompt fine on DVT.

Change-Id: I1c9913b4476a08303f9dd887b8631601c847dcf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7014ee1bb88df7a2d7f6b3dced797fef75b252d
Original-Change-Id: I061c0b03b43b516a190b370c04888e73a410fcf1
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/391233
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/16881
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07 17:55:29 +02:00
Lijian Zhao
28821dbb22 soc/intel/apollolake: Add pmc_ipc device support
A dedicated pmc_ipc DSDT entry is required for pmc_ipc kernel driver.
The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and
Punit Mailbox.

BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successfully and check with dmesg to see the
driver has been loaded successfully without errors.

Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/16649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28 22:01:01 +02:00
Aaron Durbin
c64a6d63ed soc/intel/apollolake: provide power button ACPI device
Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.

BUG=chrome-os-partner:56677

Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-26 23:52:32 +02:00
Shaunak Saha
6fcfd919f1 soc/apollolake: Correct the comment section in gpio.asl
This patch corrects the comment section in gpio.asl for
GPE method.

Change-Id: I45771a295ee1eda00b9699f42cddd120223ff7bf
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16647
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:59:40 +02:00
Shaunak Saha
c8ae5995bb soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15 03:16:46 +02:00
Vaibhav Shankar
ef8deaffcb soc/intel/apollolake: Add PM methods to power gate PCIe
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.

BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-14 22:17:47 +02:00
Furquan Shaikh
477bc97ba0 soc/intel/apollolake: Use consistent convention for community names
Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO
community names, follow one single convention. This allows for re-using
macros easily.

Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16353
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-01 07:30:56 +02:00
Vaibhav Shankar
93f34e1a74 soc/intel/apollolake: Add ASL methods for eMMC
Implement PS0 and PS3 methods to support eMMC power gate
in S0ix suspend and resume.

BUG=chrome-os-partner:53876
TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
System should resume from S0ix.

Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16233
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-24 06:44:48 +02:00
Elyes HAOUAS
038e7247dc src/soc: Capitalize CPU, ACPI, RAM and ROM
Change-Id: I7f0d3400126d593bad8e78f95e6b9a378463b4ce
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15963
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31 19:27:53 +02:00
Martin Roth
4c72d3612b Remove extra newlines from the end of all coreboot files.
This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:19:33 +02:00
Shaunak Saha
5dd2b18540 intel/apollolake: Add soc specific DPTF values
This patch adds apollolake soc specific change. DPTF
ASL files are now in src/soc/intel/common so that
they can be reused but different soc can have different values
e.g., for skylake cpu soc thermal reporting device is at
Bus 0, Device 4, Function 0 while for apollolake it is Bus 0, Device 0,
Function 1. This patch adds a dptf asl file in soc directory where we
can define all values which can change across soc's and can be
included in mainboard dptf asl.

BUG=chrome-os-partner:53096
TEST=In Amenia and Reef board verify that the thermal zones are
       enumerated under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a thermal
       zone of type TCPU exists there.

Change-Id: I888260a9c799d36512411a769f26dd30cf8d5788
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15619
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-28 20:10:15 +02:00
Jagadish Krishnamoorthy
df7ad44853 soc/intel/apollolake: Correct the gpio bank irq
The gpio bank irq is not correct and hence gpio
bank handler is never called in case of gpio based irq.
Correct the gpio bank irq to enable gpio based irq.

BUG=chrome-os-partner:55433
TEST=cat /proc/interrupts | grep INT3452 should
output 14.

Change-Id: I54253786425b7d4c2007043d49a91dfa6db0397b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/15756
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-22 18:57:48 +02:00
Shaunak Saha
7f149c7bb4 soc/intel/apollolake: Add handler for SCI
This patch adds the handler to enable bit for gpio_tier1_sci_en.
gpio_tier1_sci_en enables the setting of the GPIO_TIER1_SCI_STS
bit to generate a wake event and/or an SCI or SMI#. We are setting
the bit for gpio_tier1_sci_en from the ASL code as OS clears this bit
if set from BIOS. As per ACPI spec _GPE is defined as the Named
Object  that evaluates to either an integer or a package. If _GPE
evaluates to an integer, the value is the bit assignment of the SCI
interrupt within the GPEx_STS register of a GPE block described in
the FADT that the embedded controller will trigger. FADT right now
has no mechanism to acheive the same.

Change-Id: I1e1bd3f5c89a5e6bea2d1858569a9d30e6da78fe
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15578
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-12 20:37:57 +02:00
Saurabh Satija
3d0e2871cb soc/intel/apollolake: Add NHLT table region to ACPI global nvs
Add address and length of NHLT table in ACPI.

Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15025
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-28 22:56:22 +02:00
Saurabh Satija
cbaa2abd6f apollolake: Add ACPI device for audio controller
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if set in NVS.

Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15026
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-28 21:57:34 +02:00
Hannah Williams
8ecd6f849c soc/intel/apollolake: Include _PTS, _WAK and _SWS
Change-Id: I3400611095978421c7b35a7ea9c68b8571942ae9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15138
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-24 19:11:21 +02:00
Hannah Williams
057ac4da0e soc/apollolake: Include PCI _OSC method
Change-Id: I2545fc184ebfaa006a75783bf3d55f009066eed3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15110
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-20 23:51:29 +02:00
Furquan Shaikh
1f40ae2d74 intel/apollolake: Correct the offsets in gnvs
Offsets start from 0 instead of 1. Fix this in the gnvs definitions.

BUG=chrome-os-partner:54342

Change-Id: Id6766a8766ef430d19ffcb801bfab43d38de37db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15180
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-15 18:47:34 +02:00
Furquan Shaikh
d01f5a01e6 intel/apollolake: Add CBMEM console to GNVS
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.

1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console

BUG=chrome-os-partner:54342

Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-06-15 17:56:52 +02:00
Hannah Williams
85e3c77226 soc/apollolake: remove _RMV and _DSW methods from xhci.asl
Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-01 22:27:05 +02:00
Shaunak Saha
d6463dd42c intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.

BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
       src/ec/google/chromeec/acpi/ec.asl

Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-01 22:26:21 +02:00
Hannah Williams
1cdce27cad soc/apollolake: Enable Wake from USB devices
Change-Id: Ib0b30a5779681488e80000a2570fc2fd4c69e908
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-25 19:10:04 +02:00
Lance Zhao
1bd0c0c497 soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.

Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:47:30 +02:00
Zhao, Lijian
164e8f1d9b soc/intel/apollolake: Add GPIO devices
Add GPIO controller in ACPI device description.

GPIO controller driver is probed in kernel and all
the pins in the banks are showing respective values.

Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/14478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:46:00 +02:00
Zhao, Lijian
2b9a5f5688 soc/intel/apollolake: Fix northbridge _crs scope
Move _CRS scope from MCHC device only to whole pci root bus. Otherwise
ACPI will not able to assign resource to devices other than MCHC.

Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:14:47 +02:00
Andrey Petrov
d047ab590e soc/intel/apollolake: Actually include ACPI PCI IRQ definitions
Without ACPI PCI IRQ definitions kernel is left only with informaiton
available in PCI config space, which is not sufficient.

Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14465
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-28 05:10:53 +02:00
Martin Roth
433e8d272d intel/apollolake: Fix whitespace issues
Change-Id: Ia5bcd19d994e23375d7e6d2050113c809ae57296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14368
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-04-16 01:52:43 +02:00
Zhao, Lijian
44d009dc7f soc/intel/apollolake: Fix northbridge _CRS
Fix build break on current _CRS method with correct scope.

Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14288
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-15 00:25:06 +02:00
Hannah Williams
4e63077d6b soc/apollolake: Add ACPI platform sleep capability
Change-Id: I6854f410b4d3847238f0253b7fbb9bbe8f9da395
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14282
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:29:04 +02:00
Martin Roth
ebabfadcec soc/intel: Update license headers
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-14 16:54:33 +02:00
Zhao, Lijian
cf482c1794 soc/intel/apollolake: Fill _PRT entry in DSDT
ACPI aware OS will need _PRT table to get desired interrupt
resource assigned and make device driver working. The logical
device within SOC gets fixed interrupt line.

Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14243
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-11 18:24:12 +02:00
Zhao, Lijian
51d43fc9c5 soc/intel/apollolake: Add lpss dsdt entry
Add southbridge and LPSS device DSDT table.

Change-Id: I0607398408900d8c5d543ecd5e5d4830d2a70bf1
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14218
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-11 18:23:08 +02:00
Zhao, Lijian
e036270953 soc/intel/apollolake: Fill northbridge ASL
Northbridge resource assignment:
Dynamicly update memory resources for northbridge devices, exclude any
fixed MMIO resources.

Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-04 23:25:21 +02:00