Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Compared SSDT with this patch against DSDT without this patch, they are same
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.
Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot to OS and verify acpi tables.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These PCIe and DMA ports are not available for adlrvp_m.
BUG=none
TEST=Boot device
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps
rebooting with hash error.
Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.
BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board
Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.
BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform
Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.
BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DPTF functionality for Alder Lake based adlrvp board
BRANCH=None
BUG=None
TEST=Built and tested on adlrvp board
Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry
since it is not used anymore.
BUG=none
TEST=Check lsusb to see if BT enumerated.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.
TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.
Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.
This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.
BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.
Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.
Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.
Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.
BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP
Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC
TEST=Build, Boot and Verify streaming in both Camera
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5
BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP
Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP
TEST=Able to build ADL-M
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST= Built and booted on ADL-P LP4 RVP
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, we used to stitch extra VBT files to ADLRVP build using
Makefile. With enablement of emerge build, we should be able to
integrate more than 1 VBT binaries using ebuild.
This removing these lines to avoid compilation issues in emerge builds
BUG=None
BRANCH=None
TEST=Check if compilation passes on emerge build. Stitched additional
VBT files using emerge and checked that coreboot picks up correct VBT.
Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.
Mainboard users can pass required rcomp from memory.c file.
Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.
BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.
Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.
Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.
2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.
3. Also, update RcompResistor value for ADLRVP.
BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.
Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=None
TEST=Verified BT offload working on ADL RVP
Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.
Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support to pick the right vbt from cbfs according to
SKU-ID.
Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.
Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Add mainboard Kconfig to Kconfig.name files
2. Handle mainboard names in Kconfig file for adlrvp
3. Created a new devicetree.cb for Adlrvp-m.
3. Add override devicetree for ADL-M RVP.
4. Configure proper PCI and USB ports as per schematics for ADL-M
BUG=None
BRANCH=None
TEST=Able to build ADL-M RVP variants adlrvp_m and adlrvp_m_ext_ec.
Signed-0ff-by: Maulik Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I997b89ba87fb03dfa6a836caec51efd05baa2e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49871
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.
Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).
ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).
Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT,
rather than force-select it.
Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
1. Make CLKSRC -> 7 and CLKREQ -> 6
2. CLK 6 is using free running CLK
3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ
hence remove the unused GPIO.
Wrong GPIO configuration is causing platform reboot issue on
ADLRVP with Chrome SKU.
Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
1. Add 2 ports and 2 endpoints
2. Add support for OVTI5675
WFC Cam is on I2C5 and UFC is on I2C1
BUG=None
BRANCH=None
TEST=Build and Boot adlrvp board and able to capture image
using camera.
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C related GPIO as per ADL-P schematics.
This is based on Revision 0.974 of schematics.
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
List of changes in SPD:
1. SPD Revision (of JEDEC spec)
2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB)
3. MSB -> CAS Latencies Supported, First Byte
4. CAS Latencies Supported, Second Byte
5. CAS Latencies Supported, Third Byte
6. LSB -> CAS Latencies Supported, Fourth Byte
7. Minimum CAS Latency Time (tAAmin)
8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax)
9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin)
10.Cyclical Redundancy Code (0- 125 byte)
TEST=Able to build and boot with updated SPD.
Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
List of changes:
1. Initialize dq_map array in a single line
2. Make dqs_map array also in a single line
TEST=Able to build and boot ADLRVP LP4 SKU.
Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
