The correct type-signature of 'do_smbus_write_byte' is:
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
and so storing the return type in a 'u32' is inappropriate, leading
to a tautological compare of 'ret < 0' and 'err < 0'.
Change-Id: I65486df7156c70af84fa00c336142d9a45998620
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8209
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's not a SPI related macro, hence move it to stddef.h where
other similar macros live.
Change-Id: I1008894af7a272f1bc36d3ae6cee3881132b6ba9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8109
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
No reason to carry timestamps on CAR stack, as implementation
of timestamps internally stashes on CAR_GLOBAL table and migrates
those to CBMEM.
Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8022
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This reverts commit 320647abda, because it
introduced the following regression.
$ LANG=C make V=1
Warning: no suitable GCC for arm.
Warning: no suitable GCC for aarch64.
Warning: no suitable GCC for riscv.
/bin/sh: --: invalid option
Usage: /bin/sh [GNU long option] [option] ...
/bin/sh [GNU long option] [option] script-file ...
GNU long options:
--debug
--debugger
--dump-po-strings
--dump-strings
--help
--init-file
--login
--noediting
--noprofile
--norc
--posix
--rcfile
--restricted
--verbose
--version
Shell options:
-ilrsD or -c command or -O shopt_option (invocation only)
-abefhkmnptuvxBCHP or -o option
make: -print-libgcc-file-name: Command not found
It also introduced trailing whitespace.
Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8223
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains, compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with verstage_.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0
Reviewed-on: http://review.coreboot.org/8159
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Allow for reading from cbfs media without having a handle
to a non-CBFS_DEFAULT_MEDIA cbfs_media. In conjunction with
cbfs_locate_file() one can locate and cbfs_read() a file
without bringing the entire file through a potentially
temporary buffer (non-memory-mappable cbfs media platforms).
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built.
Original-Change-Id: Ib5d965334bce1267650fc23c9e9f496675cf8450
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205991
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 85200f28863e5ea8888322f5787dc6de9a2999f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I25e3221beefd0155305ad63da6be9f47e756f7d0
Reviewed-on: http://review.coreboot.org/8181
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
cbfs_locate_file() can be used to locate the data within the
cbfs file. Based on the offset and length of the file it can
then be read into any address without bringing the contents
into another buffer (platforms without memory-mapped access
to entire contents of cbfs at once).
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and booted rush into romstage (stage load still works).
Original-Change-Id: I2932f66478c74511ec1c876b09794d9a22a526b3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206000
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 56c958facd379ca0eeebe1b689e3b80d5e692699)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c4964132af615a069258c0eb37153bd84fbbfae
Reviewed-on: http://review.coreboot.org/8180
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When included for the CAR transition, this was causing the error:
error: invalid storage class for function 'DebugDeadLoop'
Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8193
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Put functions in appropriate pre-processor sections to avoid
false-positive 'unused function' compiler warnings.
Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8157
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Put function under same guard as its call site so that the
compiler does not emit a warn about unused functions upon
a false branch of the guard.
Change-Id: I899d539ec5fbb87e7469415cc8d15837ba8e63f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8156
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
I would appear from commit a6354a1 that this is now dead code.
Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
These boards don't have Super I/O's, rather they use Embedded
Controllers instead. No need to confuse with Super I/O related
stuff showing up in menuconfig.
Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7986
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Function was orginally used for reverse engineering.
Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8158
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
This just fixes name members of mainboard_ops for daisy and
peach_pit, which were never officially supported but used for
development and proof-of-concept.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96
Reviewed-on: http://review.coreboot.org/8184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Place the mrc.cache file at top of CBFS. There is no real requirement
for it to have a fixed location though.
Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Due to the CST entries the machine uses less power running
GNU/Linux-libre. This can be seen by monitoring CPU temperature
and time left the machine can run on battery. CPU temperature
measurements have been done with lm_sensors, battery querying
with acpi. Tests have been done before applying this patch and
after. In both cases the battery was fully loaded and the machine
powered up on battery, without AC. In both tests the machine was
idleing for more than 1 hour.
Without this patch battery was predicted to last 01:52:30 hours,
CPU temperature first measurement showed 38 degrees. After 15 min
idle, temperature has reached its maximum value in this test of
61 and 62 degrees (Core 0 and 1). Fan speed begins to increase
shortly after 15 min. From its minimal value 1800 rpm it reaches
3100 rpm after 40 min. CPU temperature did not increase any further.
After 60 min idle, the battery was predicted to still last 57 min.
With this patch battery was predicted to last 02:22:40 hours. That
is plus 30 min. CPU temperature begins at 35 degrees. After 15 min
temperature has reached 45 degrees; after 30 min it has reached
the maximal temperature during this test of about 50 degrees.
That is 10 degrees improvement. The fan stayed at minimal speed.
After 60 min idle, the battery was predicted to still last 01:22:48
hours; a 25 minute improvement.
Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13
Signed-off-by: Axel Holewa <mono@posteo.de>
Reviewed-on: http://review.coreboot.org/7923
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This adds a generic primitive memory test. We should look into
using tests in src/lib/ramtest.c, but they seem to rely too heavily
on x86 asm and this test has been useful on multiple ARM platforms.
BUG=none
BRANCH=none
TEST=builds and runs on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed
Original-Reviewed-on: https://chromium-review.googlesource.com/186309
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Conflicts:
src/lib/Makefile.inc
Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b
Reviewed-on: http://review.coreboot.org/8150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
In the original fix for the 'Lost arb' we were seeing on
Nyan* during reboot stress testing, I had the name of
BC_TERMINATE's bit setting wrong. Fix this to use the
IMMEDIATE (1) setting. The setting didn't change, just
the name. According to Julius this is the optimal
setting for bus clear in this instance. Also widened
the SCLK_THRESHOLD mask to 8 bits as per spec.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206409
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff
Reviewed-on: http://review.coreboot.org/8152
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same
as PLLP. But that is incorrect, BootROM had switched it to pllp_out2
with the rate 204MHz. So actually the warm boot procedure was running at
the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz.
And the CPU complex power on sequences were different with what we used
in kernel and Coreboot. Fix up the sequence as below.
* enable CPU clk
* power on CPU complex
* remove I/O clamps
* remove CPU reset
Update the time of the CPU complex power on function for record.
* power_on_partition(PARTID_CRAIL): 528 uSec
* power_on_partition(PARTID_CONC): 0 uSec
* power_on_partition(PARTID_CE0): 4 uSec
Finally, removing the redundant routine of a flow controller event with
(20 | MSEC_EVENT | MODE_STOP).
BUG=chrome-os-partner:29394
BRANCH=none
TEST=manually test LP0 with lid switch quickly and make sure the last
write to restore register successfully
Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205901
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If21d17dc888b2c289970163e4f695423173ca03d
Reviewed-on: http://review.coreboot.org/8151
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Propagate commit 9107e53 from amd/agesa and fix some
related #includes under cpu/amd/pi.
Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.
Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8171
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial; Use tab over space for indent.
Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8015
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This serves as supplemental patch to CL:197732. After clearing bus, we
should also redo controller init (because controller has been reset
before bus clear). On the upper layer, upon receiving error return status,
it should just retry instead of simply call cpu_reset().
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Built and tested on nyan and nyan_big.
Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202784
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984
Reviewed-on: http://review.coreboot.org/8145
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.
BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0
Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204525
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351
Reviewed-on: http://review.coreboot.org/8142
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a block in the SMI handler to call init functions for
drivers which may be used in SMM. A static variable is used to
ensure the init functions are only called once.
BUG=chrome-os-partner:29580
BRANCH=mccloud
TEST=Built and booted on mccloud, system no longer hangs when
pressing power button at the dev mode screen. Also tested on parrot.
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee
Original-Reviewed-on: https://chromium-review.googlesource.com/204764
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861
Reviewed-on: http://review.coreboot.org/8134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable the ACPI Device for the EC ALS.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d
Reviewed-on: http://review.coreboot.org/8133
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC can export ALS information if the sensor is attached
to it directly rather than to the host. This adds a basic
ACPI ALS device and implements the required information.
The kernel does not use the _ALR tuple set but it is required
by the ACPI spec so this just adds the sample two point
response curve defined in ACPI 5.0 section 9.2.5.
The EC does not currently send events for lux value changes so
a polling interval of 1 second is defined.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f
Reviewed-on: http://review.coreboot.org/8132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This marks the bottom chunk of memory, which is used by various IP
blocks, as reserved so that Depthcharge does not attempt to wipe it.
BUG=chrome-os-partner:30067
BRANCH=storm
TEST=Built and booted for storm, depthcharge shows:
Wipe memory regions:
[0x00000041500000, 0x00000051000000)
[0x000000510006a0, 0x00000053000000)
[0x00000054141260, 0x0000007fffd000)
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77
Original-Reviewed-on: https://chromium-review.googlesource.com/206516
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a
Reviewed-on: http://review.coreboot.org/8149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The actual storm device has a single USB interface, which needs to be
explicitly turned on using GPIO51.
BUG=chrome-os-partner:29871
TEST=verified that depthcharge finds and boots a kernel from USB stick
Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205329
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7
Reviewed-on: http://review.coreboot.org/8147
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.
BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge
Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205182
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f
Reviewed-on: http://review.coreboot.org/8146
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*.
Back in the day, like more than half a decade ago, we migrated a lot
of boards to printk, but we never cleaned up the existing code to be
consistent. Instead, we worked around the problem with a very messy
console.h (nowadays the mess is hidden in romstage_console.c and
early_print.h)
This patch cleans up the generic code pieces to use printk() on all
non-ROMCC boards.
Our two remaining ROMCC boards are fixed up in this commit:
bifferos/bifferboard and dmp/vortex86ex.
Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8115
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Remove @param command for #define - this isn't valid.
- Rename duplicate @section names - All of the renamed @sections
have other @section names in the same file.
- Remove blank @brief and @param commands - Doxygen seems to REALLY
dislike this...
- Add a missing @param name.
Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8175
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Join doxygen file command with the file description
- Give extended file location so doxygen knows which early_sbmus.h
the file is. (I don't get this either, but it fixes the warning)
Change-Id: Ia91fb1ac1e9687e1a5a5cb5234696b3c24d4cd24
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8174
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Take unused reverse eng function out of build by wrapping in #if 0.
Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8167
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove 'read_mchbar8_bypass()' as 'read_mchbar8()' does the same
thing and 'read_mchbar8_bypass()' is unused.
Change-Id: I0dc2325e6205c38b63e5200c408ece65e4f938dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8166
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This convenience API was never used.
Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8108
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Missing base may have enabled SMI for all GPI inputs.
Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8169
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- @todo has to be lowercase for doxygen
- Fix some parameters that had changed in the code.
- The @file entries needed to be more specific.
Change-Id: Icdce08735f581609cd25cce41e986c71435368a4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8154
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
- Add missing parameter names in several files
- remove parameter types in several files
- remove lines from doxygen documentation. These should be outside the
doxygen comments.
- Some of the comments shouldn't have been doxygen style. Turn these
into regular non-doxygen comments.
Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8153
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Remove useless comment pretaining to abusing pragma's for old
GCC/GDB interaction issues.
Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8017
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This file will have CBMEM init hooks API one day.
Change-Id: I0c31495d4217a5eb235b13e6d8e8c99a87a3b840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.
Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8111
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the cpu code to use printk() on all non-ROMCC
boards.
Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8114
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8110
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.
Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This code is unused, and the same functionality is in superiotool
already.
Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
console_tx_byte() is defined in stream.h, not console.h. This will cause
problems later, when untangling more ROMCC and console code. Hence, fix
the issue beforehand.
Change-Id: If4e04bd6c69b630912414676950157d06c364d74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8121
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Somewhere along the line, the sb_cfg parameter name was changed to
config, but this wasn't carried into the documentation or the function
prototypes everywhere.
Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8098
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Doxygen gives an error when processing #defines inside doxygen comments.
Normal comments are ignored. The choice for this fix was to make this
a standard comment starting with '/*' instead of '/**', or to make the
comment not a #define.
Change-Id: I97fbbcea6f045d80ec7c0ab5e196d57e5da16d86
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8099
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
These files were trying to document the parameters, but didn't have
the syntax quite right. Change the comments from @varname to
@param varname as required by doxygen.
Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8100
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The doxygen parameter names in the comments no longer matched the
functions they were attached to. Doxygen complains about extra
parameter comments and uncommented parameters in the functions.
Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8101
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These comments are left over and are not relevent in the coreboot
code, but created a new section titled "Release Content" in the
doxygen documentation produced by the coreboot code. In an effort
to clean up the output, I'm removing these doxygen comments.
Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8069
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting
and passing information to coreboot. These seem to me like they should
be in their own file, so I'm splitting them out of fsp_util.c. I'll
be adding a couple more functions in the next patch.
These functions should all be compliant to the Hand Off Block spec.
Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8065
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by
Clang complaining that the function 'to_flash_offset' is unused.
Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As `#ifndef` and not `#if` is used in the check for
include guards, setting it to 1 is not needed.
Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8103
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Use 'delay.h' header rather than directly including 'delay.c'
source. N.B. Some amdfam10 and K8 boards are not included in
this changeset since unrelated issues are woven in there.
Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8086
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Provide proper Makefile and Kconfig components so
that this superio is built as object code. Select
superio component in mainboard Kconfig's to bring
in the link-time symbols and thereby removing the
need for .c inclusion.
N.B. The LPC47N207 Super I/O does not physically exist
on these boards. The Super I/O is found on external LPC
debug card hardware and so should really be made selectable.
However, this is beyond the scope of this specific fix, that
rids us of .c inclusions in romstage.c
Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8084
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.
Timestamp implementation for ARMv7
Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.
The ARM implementation uses the monotonic timer.
Original-Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps
Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)
Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The hp/abm board is used in network/server applications.
Notes:
- The hp/abm board is headless and therefore does not define
CONFIG_GFXUMA, and does not require a video bios.
- The micro USB connector on the board edge is connected to COM4
(i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3.
- If you are using SeaBIOS it would also need to be configured to
use the UART at I/O=2E8h.
- This board has been tested with headless installed versions of
Ubuntu 12.10 and Fedora 19.
Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6116
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This is just bit-rotting and its likely this will continue to rot
by the time someone notices it exits it will be too late (i.e., today).
Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8087
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Remove types from the param declarations.
- list needed to be uppercase.
Change-Id: I8b9ed78908e5d3e1d99e7ba2ea9013be109b8e27
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8072
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Remove PeiServices param for OemInitEarly - it doesn't exist in the
function.
Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8073
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
- Move @def BIOS_SIZE description to the next line
- SB_GEN2 changed to SB_GPP_GEN2
- Move the SIO_HWM_BASE_ADDRESS description to the next line
Change-Id: Ia3496b0108484f557627304553461932a100dfa5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8071
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Correct the param to match the functions.
Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
- @v & @i need to be @param v & @param i
- add the @file command
Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8075
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This doxygen directive was creating a top level modules section, which
had the vx900_int15 code as its only member. I do think that breaking
the code into documented sections is a good plan, but in an effort to
clean up the output, I'm removing this for now.
Change-Id: I3f7e2f704136ebbd1961c5946bac4c2edbd6a371
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8070
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8083
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8082
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This brings mainboard up to being consistent tree-wide now for
all superio header path inclusions.
Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8052
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This explicitly casts CONFIG_SYS_SDRAM_BASE to an unsigned type so
we don't get compilation errors when increasing CONFIG_DRAM_SIZE_MB.
BUG=chrome-os-partner:29871
BRANCH=storm
TEST=compilation no longer fails with DRAM_SIZE set to 1024
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9717c39d87682d43ec4e7a4042d9b559a1d7eedb
Original-Reviewed-on: https://chromium-review.googlesource.com/206010
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 178db896346ae8cbc5ddec5373a83688f32c62ba)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I68c11d398820684ad928bdfdd74f7a6885247333
Reviewed-on: http://review.coreboot.org/8059
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
When the IPQ SPI driver was ported to coreboot, a few GPIO related
definitions ended up in a wrong include file. Move them to the proper
place and get rid of duplicated definition of GPIO_OUT.
BUG=chrome-os-partner:27784, chrome-os-partner:29871
TEST=proto0 still boots with the new firmware
Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4
Reviewed-on: http://review.coreboot.org/8058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Depthcharge clears up all unused DRAM before starting Linux, and does
not know the translation table location. Instead of adding an
exclusion term to the memory wipe descriptor let's move the table to
the top of IMEM, it is also likely to be a good location in the
future, when EFS is introduced.
BUG=chrome-os-partner:27782
TEST=manual
. built and ran firmware on ap148
Original-Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203624
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 4250f8574d6cc0bbec5ba0411f22d801f034afb8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I12cd74e3d318b878e7703414a7ddaaed0812cb7a
Reviewed-on: http://review.coreboot.org/8057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Hynix 2GB/4GB configs have been fine-tuned.
Kingston 2GB config is new, uses RAMCODE 0x6.
BUG=none
TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my
Big 2GB system (PVT1/SKU1) and it booted OK.
BRANCH=nyan_big
Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd
Reviewed-on: http://review.coreboot.org/8045
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For some panels, the plld can't provide the pixel clock that
the panels wants, so we give it a good enough one. And we
should calculate the dp/dc settings by the real pixel clock.
BRANCH=nyan
BUG=chrome-os-partner:29489
TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
No screen flicker is observed. No sor dp fifo underflow found.
Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203358
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac
Reviewed-on: http://review.coreboot.org/8044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.
BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Original-Reviewed-on: https://chromium-review.googlesource.com/203447
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe
Reviewed-on: http://review.coreboot.org/8043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
CrOS devices with Chromeos EC need only use hostevent to communicate
recovery assertion to the BIOS. This CL removes wired GPIO from
determining recovery as it appears under certain conditions (cold
reset) the internal PU on the AP isn't strong enough and therefore the
value is sometimes seen as asserted.
BRANCH=none
BUG=chrome-os-partner:29333
TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot.
Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2
Original-Signed-off-by: Todd Broch <tbroch@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202996
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f
Reviewed-on: http://review.coreboot.org/8042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix
BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
XHCI driver was not enabled in libpayload and some ports were
disabled that should be enabled.
The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to
properly indicate unused so crossystem does not attempt to
export GPIO number 255 in the kernel and trigger a warning.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2
Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/203184
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 328362469b00c9467908a7d18a031fee73753def)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434
Reviewed-on: http://review.coreboot.org/8047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Both DDI ports may be used on this board so it needs to be
able to detect a device on either port.
BUG=chrome-os-partner:28234
TEST=None (needs hardware)
Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099
Reviewed-on: http://review.coreboot.org/8046
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Put all the SPD related information in one place including
the onboard SPD sources and the board specific parsing.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201082
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123
Reviewed-on: http://review.coreboot.org/8006
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Convert wtm2 board to use the broadwell soc chipset.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226
Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The driver as it was copied from u-boot provided a function to
transmit multiple characters in one invocation. This feature was not
ported to coreboot, there is no need to maintain the complexity when
only one character at a time is transmitted. It is also very desirable
to get rid of a 1024 byte array allocated on the stack.
The array was necessary to allow to convert multiple newline
characters in the transmit data flow into two character sequences
CRLF. Now just a single word is enough to keep one or two characters
to transmit.
[EDIT km: newline translation is now part of printk]
BUG=chrome-os-partner:27784
TEST=verified that coreboot with the new code prints generates console
output.
Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201782
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8011
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The static allocator only worked for x86 anyway.
Change-Id: Ibe4e172bb654f6414949bd11787c9407d091a858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8028
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The static allocator only worked for x86 anyway.
Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The recently introduced page table location value is wrong, it
overlaps with other areas of the code. This patch fixes the location,
a more robust scheme is needed for memory layout management.
BUG=none
TEST=manual
. occasional random failures disappear after this patch is applied
Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202641
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7afcab42db259e53541fb991b36d680fc2186304
Reviewed-on: http://review.coreboot.org/8019
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.
BUG=chrome-os-partner:27784
TEST=manual
. booted coreboot successfully on ap148
Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202046
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481
Reviewed-on: http://review.coreboot.org/8012
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.
BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
address. Also observed that the SPI driver takes 900 ns to
process a byte as opposed to 1.5 us in case caching is not
enabled.
Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200332
(cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
Reviewed-on: http://review.coreboot.org/8009
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.
BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe
CPU: Qualcomm 8064
in the ramstage console output as well as not failing to load
depthcharge any more.
Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199675
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
Reviewed-on: http://review.coreboot.org/8000
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Squashed the correction patch with the original to avoid confusion in
coreboot.org review.
All what's needed apart from configuring the feature is to provide a
function which would report the top of DRAM address.
BUG=chrome-os-partner:27784
TEST=manual
. with all other patches applied, the image proceeds all the way to
trying to download 'fallback/payload'.
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3
Original-Reviewed-on: https://chromium-review.googlesource.com/197897
(cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
storm: initialize dynamic cbmem properly
Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.
Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).
BUG=chrome-os-partner:27784
TEST=build boot coreboot on ap148, observe the following in the
console output:
Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
coreboot table: 256 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74
Reviewed-on: http://review.coreboot.org/7996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is based on x220 and t520. Tested on i7 model with usb3.
There is no support for nvidia gpu and optimus.
Change-Id: I6ca9436ccec3024095d02078e5e450147841e463
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
This change updates the cfg file for Hynix/Micron/Samsung 4GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202059
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c
Reviewed-on: http://review.coreboot.org/8008
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.
BUG=chrome-os-partner:27784
TEST=manual
. with this change and the rest of the patches coreboot on AP148
comes up all the way to attempting to boot the payload (reading
earlier stages from the SPI flash along the way).
Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This service is required by various coreboot code modules. It looks
like the 8064 SOC does not provide anything better than a 32 KHz free
running counter (it is used in u-boot for us timer as well). Let's use
this for now.
BUG=chrome-os-partner:27784
TEST=manual
. with the rest of the patches applied AP148 boots all the way to
trying to start the payload.
Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197896
(cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id37ed21193db67ceee11a795713c34ef26383380
Reviewed-on: http://review.coreboot.org/7993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ARM processors save the PC value in the Link Register when they handle
and exception, but they store it with an added offset (depending on the
exception type). In order to make crashes easier to read and correctly
support more complicated handlers in libpayload, this patch adjusts the
saved PC value on exception entry to correct for that offset.
(Note: The value that we now store is what ARM calls the "preferred
return address". For most exceptions this is the faulting instruction,
but for software interrupts (SWI) it is the instruction after that. This
is the way most programs like GDB expect the stored PC address to work,
so let's leave it at that.)
Numbers taken from the Architecture Reference Manual at the end of
section B1.8.3.
BRANCH=none
BUG=chrome-os-partner:18390
TEST=Provoked a data abort and an undefined instruction in both coreboot
and depthcharge, confirmed that the PC address was spot on.
Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199844
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6
Reviewed-on: http://review.coreboot.org/7992
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This adds a generic helper function for adding boot reason in the
ChromeOS case. If vboot is enabled, it will use information passed
in via the vboot handoff table in cbmem to determine mode and
reason in the case of recovery.
BUG=chromium:373467
BRANCH=nyan
TEST=built along with follow-up CL and booted on Big under various
modes, verified entry was added to eventlog with "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b
Original-Reviewed-on: https://chromium-review.googlesource.com/199690
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75
Reviewed-on: http://review.coreboot.org/7991
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The static allocator only worked for x86 anyway.
Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8029
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I9210241c902ad8a88980a7c9cdb0d52c460b2541
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8025
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
It was showing up as a menu item and it should not.
Change-Id: I448f683fbf4187b11821381332f971b1daea29f8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix a trivial tab/space indent inconsistency while here.
Change-Id: I819d85293e1a070817cd13349a220ba85ba89951
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.
samus: Move SPD handling to separate file
The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.
It relies on the updated pei_data structure from broadwell instead
of the haswell interface.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Move PEI data structure init to separate file
This needs to be executed in both romstage and ramstage
for the different PEI binary stages.
It uses the broadwell interface now instead of haswell.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Convert mainboard to use soc/intel/broadwell
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922
(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Add some code to print basic info from SPD
The handling of LPDDR is a bit messy in Intel platforms. There
is no traditional SPD so instead one is created by hand from the
provided datasheets.
These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.
This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Hook the soc/intel/broadwell directory into the configuration
and build system so it can be used by mainboards.
BUG=chrome-os-partner:28234
TEST=build and boot on wtm2
Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b
Reviewed-on: http://review.coreboot.org/7940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.
- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic
Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
A typical SPI operation consists of two phases - command and data
transfers. Command transfer is always from the host to the chip (i.e.
is going in the 'write' direction), data transfer could be either read
or write.
We don't want the receive FIFO to be operating while the command phase
is in progress. A simple way to keep the receive FIFO shut down is to
not to enable it until the command phase is completed.
Selective control of the receive FIFO allows to consolidate the
receive and transmit functions in a single spi_xfer() function, as it
happens in other SPI controller drivers.
The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the
next byte can be written or received, respectively. While data is
being received the 0xFF bytes are transmitted per each received byte,
to keep the SPI bus clocking.
The data structure describing the three GSBI ports is moved from the
.h file into .c file. A version of the clrsetbits macro is added to
work with integer addresses instead of pointers.
BUG=chrome-os-partner:27784
TEST=not yet, but with the res of the changes the bootblock loads and
starts the rombase section successfully.
Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197779
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f
Reviewed-on: http://review.coreboot.org/7983
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
The original patch from chromium was a bit of a mishmash.
Between that, rebasing and using the coreboot.org UART infrastructure,
the patch has changed a bit from the original. It seems reasonable to
keep these changes together.
- build in the ipq UART and turn on bootblock console
- sets LPAE and ROM header address
- adds cpd.c to storm
The original commit:
ipq8064: make UART driver work in bootblock
This patch it the last one in the chain adapting the ipq9064 UART
driver for use in coreboot. A new config option
(CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of
the driver.
The previously introduced uart_wrapper.c is now included in the build
to provide the console driver structure used by ramstage.
Necessary configuration options are added to allow use of UART in the
bootblock.
BUG=chrome-os-partner:27784
TEST=with this change the coreboot image on AP148 prints a banner on
start up:
coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting...
Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196663
(cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91
Reviewed-on: http://review.coreboot.org/7875
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
We relocate GDT to CBMEM, this can be done late in ramstage.
Note: We currently do this for BSP CPU only.
Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
GPIO init marcos are not enough to initialize different gpio attributes
BUG=none
TEST=emerge-rambi coreboot works well
Original-Change-Id: I193fa7b3e22632cacb555e726e3dd3991f4f4faa
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200531
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5e0fcbcd7cefcfccb5b565003336d197bb29e4cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6bf4db9397733a003dfdedc6eb63b82127917851
Reviewed-on: http://review.coreboot.org/7953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.
BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.
Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The kernel will not track wakeup events for devices unless they have
a defined _PRW. There is no EC output of the lid signal coming to
a GPIO and instead it pulses PCH_WAKE#.
BUG=chrome-os-partner:27631
TEST=Manual on Rambi.
- Run lidclose + lidopen on EC console, verify that wakeup_count
increments.
- Run lidclose + lidopen in rapid succession, verify that suspend
request is aborted.
BRANCH=Rambi.
Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200289
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a
Reviewed-on: http://review.coreboot.org/7945
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the empty weak function clear_recovery_mode_switch().
Problem:
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set,
the following will happen:
1. Boot device in recovery mode with Esc + F3 + Pwr.
2. Turn device off with Pwr button.
3. Turn device on with Pwr button.
Device still boots to recovery screen with
recovery_reason:0x02 recovery button pressed.
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the
device off and on again with the Pwr button does a normal boot.
Solution:
Unconditionally clear the recovery flag.
BUG=chromium:279607
BRANCH=TOT
TEST=Compile OK.
Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197780
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae
Reviewed-on: http://review.coreboot.org/7895
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function
which expects size_t. This change converts uint32_t to size_t on call and
size_t to uint32_t on return.
BUG=None
BRANCH=None
TEST=Booted Nyan Big to Linux
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9
Original-Reviewed-on: https://chromium-review.googlesource.com/198016
(cherry picked from commit 6830747eb47568f2a2b494624522d37d8945c030)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I20741759e7bbd60dd7044c532287d6b55047e19a
Reviewed-on: http://review.coreboot.org/7894
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
To avoid LCD_VCC glitch on cold reset, set SOC_DISP_ON as GPIO output high.
After gfx initialize is done, set it to native function 2.
BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Tested on Rambi and squawks, no LCD_VCC glitch anymore.
Original-Change-Id: If16af498e910a8da1d77a9a66456eb767286a61a
Original-Change-Id: Icf62588fa0338f89fafb3fe9246c26f16bcdaa60
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 6f7d621678f22133c9825565fedc77d19198b08c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibaf547b8d1c27811a1bec9fa3254d559c505a361
Reviewed-on: http://review.coreboot.org/7893
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
If the kernel does not properly handle the TPM and send it a
TPM_SaveState command before suspend then it will not be in
the correct state on resume. In order to easily detect this
case add a new post code for TPM failure and use it in the
vboot resume path.
BUG=chromium:371105
TEST=Build and boot on wtm2.
Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199371
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559
Reviewed-on: http://review.coreboot.org/7936
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.
BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan
Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4fad296ecfeff8987e4a18054661190239245f32
Reviewed-on: http://review.coreboot.org/7891
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a
driver for it which implements the new RTC API.
BUG=None
TEST=Built and booted with the event log code modified to use this interface.
Verified that events had accurate timestamps.
BRANCH=nyan
Original-Change-Id: I400adccbf84221dcba8d520276bb91b389f72268
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197796
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 011e49beba3a99abbd122866891e3c20bf1188d2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibc1d342062c7853a30d195496c077e37a02b35b0
Reviewed-on: http://review.coreboot.org/7890
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.
The old commit message and identifiers are kept below for reference:
The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This brings in the banana_cs version of the SPI driver.
BUG=chrome-os-partner:27784
TEST=none
Original-Change-Id: Ie93ec8c962c26fff1f0a235516cd8a4062cab40b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194225
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3cada6e4ed51a6d4f637aa31a1a836352a99d13d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0a58a4ddaf9375c22c9b2b249a2baa2c5538ba6c
Reviewed-on: http://review.coreboot.org/7982
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There is a hub in USB port2 downstream.
BUG=chrome-os-partner:28964
BRANCH=None
TEST=emerge-nyan_blaze coreboot depthcharge chromeos-bootimage and verify usb
port2 is workable
Original-Change-Id: I0e698970729911f401f89594232f9d49e4da93cc
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200417
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 9316acfe8791585f778eecead95943e6422ca419)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I76e4331ea6e803bfbbddefab449310421c0c1d9c
Reviewed-on: http://review.coreboot.org/7949
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Our tests with the I2C bit clear mechanism (recovering from "lost
arbitration" errors) show that the bit clear hardware does not work
correctly in some situations. When a wedged slave device tries to send
more than one 0-to-1-to-0 transition to the host (e.g. leftover bits
from an aborted read), the controller never transitions the BC_ENABLE
bit back to zero.
This patch adds a long timeout to the bit clear code that waits for
register transitions as a safeguard. This way, We will still eventually
exit the function (probably followed by a reboot). Our tests show that
this will recover from all conditions after at most a few reboots.
BRANCH=nyan
BUG=chrome-os-partner:28323
TEST=Ran wedge_ack and wedge_read tests with software_i2c patch, system
recovered as expected in all cases.
Original-Change-Id: I6c37119130e1240e1ef3a5944582abbcd2e39ff0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200265
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4c8d0af25cf107a38c856b38067b8f2f74384f22)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I600d5c9a8e68719cf8795c083c5fac63f626f5bf
Reviewed-on: http://review.coreboot.org/7948
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch adds I2C emulation in software through raw toggling of the
SDA/SCL lines. Platforms need to provide bindings to toggle their
respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs,
currently only enabled for Tegra).
This is mostly useful as a debugging feature, to drive unusual states on
a bus and closely monitor the device output without the need of a bus
analyzer. It provides a few functions to "wedge" an I2C bus by aborting
a transaction at certain points, which can be used to test if a system
can correctly recover from an ill-timed reboot. However, it can also
dynamically replace the existing I2C transfer functions and drive
some/all I2C transfers on the system, which might be useful if a driver
for the actual I2C controller hardware is not (yet) available.
Based on original code by Doug Anderson <dianders@chromium.org> and
Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded
controller project.
BRANCH=None
BUG=chrome-os-partner:28323
TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable()
through the code and see that everything still works.
Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198791
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682
Reviewed-on: http://review.coreboot.org/7947
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When doing DP attach, we need to make sure the register change to
take effect immediately, otherwise it may fail to catch the attach
timing.
BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big
Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200414
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a
Reviewed-on: http://review.coreboot.org/7951
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We initialized the dc before the plld's initialization. So some
of the dc init settings did not took effect. This patch moves
the clock_display() before the dc init call.
BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big
Original-Change-Id: If2c40e2526fdf7a6aa33a2684ba324bd0ec40e90
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200413
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit dc3cc253c319c21772c30962d963ec9dfc4944a7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I021290f4293c740666d460f73fecbe79146896a4
Reviewed-on: http://review.coreboot.org/7950
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=nyan
TEST=built and booted on Big under various modes, verified that
expected boot mode showed up using "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8d98487a2cb910874c8d741008ae59a6c89102e7
Original-Reviewed-on: https://chromium-review.googlesource.com/199691
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 9f4b2574c1af23dcdc01706e9a118441f46a0f97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibbf264a1e05323dfddb7cdb270ee6f2d49e83eff
Reviewed-on: http://review.coreboot.org/7946
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Provide elog stub functions so eventlog support can be omitted
without littering code with "#if CONFIG_ELOG".
This makes it so coreboot can be built without eventlog support for
these platforms for debugging purposes.
BUG=none
BRANCH=none
TEST=compiled for Nyan and Rambi with CONFIG_ELOG unset
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibf56d29a09234068773378f99ad9bffd5480dc9c
Original-Reviewed-on: https://chromium-review.googlesource.com/198647
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 8e83dd460647972c4f46c19f8dc3d3ad7baeb550)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3c0803ceb7a1c06da717416c42b6b7730c029ed0
Reviewed-on: http://review.coreboot.org/7901
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The IO accessor wrappers are used to allow integer register addresses.
A structure defining UART interface configuration is declared and
defined. A few long lines are wrapped. Interface functions are renamed
to match the wrapper API.
cdp.c is edited to fit into coreboot compilation environment, and the
only function required by the UART driver if exposed, the rest are
compiled out for now.
BUG=chrome-os-partner:27784
TEST=after all patches are applied the serial console on AP148 becomes
operational.
Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196662
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Reviewed-on: http://review.coreboot.org/7874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These patch modifies .h files to match the coreboot API. A few more
significant changes are:
- UART specific fields removed from common board structure in cdp.h.
These fields are set at compile time in u-boot (where this
structure comes from), they will be set in a different structure in
the UART driver in an upcoming patch.
- an inline wrapper is added in gpio.h to provide GPIO API the UART
driver expects.
- the ipq_configure_gpio() is passed the descriptor placed in ro data.
BUG=chrome-os-partner:27784
TEST=none
Original-Change-Id: Id49507fb0c72ef993a89b538cd417b6c86ae3786
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196661
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit ea400f1b720eb671fa411c5fd1df7efd14fdacd6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2c7be09675b225de99be3c94b22e9ee2ebb2cb9a
Reviewed-on: http://review.coreboot.org/7873
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make sure it is initialized at different stages.
BUG=chrome-os-partner:27784
TEST=manual
. not much at this point, just verified that it compiles
Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on:
https://chromium-review.googlesource.com/196592
(cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f
Reviewed-on: http://review.coreboot.org/7981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The following patches had to be squashed
to properly build all the different ARM boards.
ipq8064: storm: re-arrange bootblock initialization
The recent addition of the storm bootblock initialization broke
compilation of Exynos platforms. The SOC specific code needs to be
kept in the respective source files, not in the common CPU code.
As of now coreboot does not provide a separate SOC initialization API.
In general it makes sense to invoke SOC initialization from the board
initialization code, as the board knows what SOC it is running on.
Presently all what's need initialization on 8064 is the timer. This
patch adds the SOC initialization framework for 8064 and moves there
the related code.
BUG=chrome-os-partner:27784
TEST=manual
. nyan_big, peach_pit, and storm targets build fine now.
Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197835
(cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
arm: Redesign mainboard and SoC hooks for bootblock
This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.
Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.
Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().
Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57
Reviewed-on: http://review.coreboot.org/7879
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Original-Reviewed-on: https://chromium-review.googlesource.com/198324
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e
Reviewed-on: http://review.coreboot.org/7935
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
The Eon SPI25 code had a number of issues:
- fix page write calculation
- fix erase segment
- fix id check
- fix sector size
- make commands EN25 generic
This makes the code similar to other SPI25 devices used in coreboot.
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198323
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8917e778cd62f3745189336d23c0c6118887d893
Reviewed-on: http://review.coreboot.org/7934
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Since the same driver is going to be used at all coreboot stages, it
can not use malloc() anymore. Replace it with static allocation of the
driver container structure.
The read interface is changed to spi_flash_cmd_read_slow(), because of
the problems with spi_flash_cmd_read_fast() implementation. In fact
there is no performance difference in the way the two interface
functions are implemented.
BUG=chrome-os-partner:27784
TEST=manual
. with all patches applied coreboot proceeds to attempting to load
the payload.
Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197931
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2
Reviewed-on: http://review.coreboot.org/7933
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Coreboot has all necessary infrastructure to use the proper SPI flash
interface in bootblock for CBFS. This patch creates a common CBFS
wrapper which can be enabled on different platforms as required.
COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the
common CBFS interface and prevents default inclusion of all SPI chip
drivers, only explicitly configured ones will be included when the new
feature is enabled. Since the wrapper uses the same driver at all
stages, enabling the new feature will also make it necessary to
include the SPI chip drivers in bootblock and romstage images.
init_default_cbfs_media() can now be common for different platforms,
and as such is defined in the library.
BUG=none
TEST=manual
. with this change and the rest of the patches coreboot on AP148
comes up all the way to attempting to boot the payload (reading
earlier stages from the SPI flash along the way).
Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197800
Original-Tested-by: Vadim Bendebury <vbendeb@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41
Reviewed-on: http://review.coreboot.org/7932
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Add the device ID definitions and properties for the SPI chip used on
the AP148 board (Google Storm).
BUG=chrome-os-partner:27784
TEST=manual
. with the rest of the patches applied AP148 boots all the way to
trying to read the payload.
Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197895
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b
Reviewed-on: http://review.coreboot.org/7931
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This CL adds an API for RTC drivers, and implements its two functions,
rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the
CMOS as lost state now uses the RTC driver instead of accessing the those
registers directly.
BUG=None
TEST=Built and booted on Link with the event log code modified to use
the RTC interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the first half of the patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883
Reviewed-on: http://review.coreboot.org/7889
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CBMEM IDs are converted to symbolic names by both target and host
code. Keep the conversion table in one place to avoid getting out of
sync.
BUG=none
TEST=manual
. the new firmware still displays proper CBMEM table entry descriptions:
coreboot table: 276 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
. running make in util/cbmem still succeeds
Original-Change-Id: I0bd9d288f9e6432b531cea2ae011a6935a228c7a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199791
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5217446a536bb1ba874e162c6e2e16643caa592a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0d839316e9697bd3afa0b60490a840d39902dfb3
Reviewed-on: http://review.coreboot.org/7938
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Always build CBMEM for romstage, even for boards that will not use it.
We further restrict car_migrate_variables() runs to non-ROMCC boards without
BROKEN_CAR_MIGRATE.
This fixes regression of commit 71b21455 that broke CBMEM console support
for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME.
Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7877
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.
Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Disable Super I/O related topics showing in menuconfig.
Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7985
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If it's a 4 byte format (as per documentation), there
are some reserved bits, so let's mark them as such...
Unfortunately undone while upstreaming changes.
Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Originally-Reviewed-on: http://review.coreboot.org/7674
Reviewed-on: http://review.coreboot.org/7964
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The "((1ull << (sizeof(modules) * 8)) - 1)" statement evaluates to
0xffffffff, but there's no need to AND with that value, as 'modules'
is already 32-bit. The '&&' is most likely a typo, which meant bitwise
and, as indicated by the structure of thus operation.
Remove this superfluous statement. This also fixes a clang warning.
Change-Id: Ie55bd9f8b0ec5fd41e440f56dcedd40c830bf826
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7965
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable
CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS.
Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only
used with PLATFORM_FSP.
CPU_MICROCODE_CBFS_LEN was no longer used at all.
Change-Id: I0454397924d2526d97b1f095cc371ba962873c99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7957
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbol map_oprom_vendev is no longer NULL.
Always have empty stub function defined.
Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7956
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbols are no longer NULL.
Always have empty stub function defined.
Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
We had NULL reference with cache_loaded_ramstage() if
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never
proceeded to ramstage.
Cache implementation outside CBMEM provides means for platform-specific
location so there is no need of weak attributes here.
Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7954
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It's not needed, as we can use a simpler macro instead.
Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7925
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This change updates the cfg file for Micron/Samsung 2GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad
Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/199296
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7
Reviewed-on: http://review.coreboot.org/7902
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. That puts the machine in a funny state and may prevent it
from booting properly.
BUG=chrome-os-partner:28559
TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC
reset, software reset ("reboot" command from the terminal), and through watch
dog reset. Verified that the new code only triggered during the watchdog reset
and that the system rebooted and was able to boot without going into recovery
mode unnecessarily.
BRANCH=nyan
Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198582
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7900
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. In order to detect those situations we can check the
rst_status register in the PMC.
BUG=chrome-os-partner:28559
TEST=With this and a change which uses the new function in the nyan boards,
built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
software reset ("reboot" command from the terminal), and through watch dog
reset. Verified that the new code only triggered during the watchdog reset and
that the system rebooted and was able to boot without going into recovery mode
unnecessarily.
BRANCH=nyan
Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198581
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72
Reviewed-on: http://review.coreboot.org/7899
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The original sdram-hynix-2GB-792.inc was just copied from nyan
bct file. This change updates the cfg file for Hynix 2GB, 792MHz
DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197660
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec
Reviewed-on: http://review.coreboot.org/7898
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reduce difference with exynos5420/clock.c by fixing some whitespace
and an include directive.
Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7926
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use 'd' instead of 'hhd' when printing absolute year of manufacture. This
is the correct type in this case, as the result is autoatically promoted
to int.
Change-Id: Ice4155bb1a04f206ae55c45c260089d6971b77d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7885
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Edward O'Callaghan