Fix dual LAN sku can't inherit correct MAC from VPD setting.
BUG=b:77836343
BRANCH=Fizz
TEST=Program the mac address to VPD in shell
vpd -s ethernet_mac0=<mac address1>
vpd -s ethernet_mac1=<mac address2> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: Ic357a3f1435d6d08107520e40872f1003ef2edf3
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/25587
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds board-specific implementation of
mainboard_vbt_filename which returns "vbt.bin" by default. This is in
preparation to allow multiple vbt binaries to be added to single
image. More sku_id specific names will be added in follow-up CLs.
BUG=b:79396300
Change-Id: I3821d55bfbe9e5773bd2eb0b0003045a80158d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms
BUG=b:78541692
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/26214
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new SPD entry for samsung's new 4GB memory and updates
atlas to use it instead of the previous gen memory.
BUG=b:79444337
TEST=booted on atlas
Change-Id: I19567736c45a1321586378c3d964c2cbebe24755
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/26185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This keeps Audio clock and data pins ON in S0ix to support
Wake on Voice.
BUG=b:77605180
BRANCH=none
TEST=Checked that S0ix suspend/resume works. Validation of WoV
was done on glkrvp previously. For Yorp, audio topology firmware
updates are required for testing WoV.
Change-Id: Idafe4e7d24fe16f8e8ff3dd86e299776ea860d03
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26202
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
A name cannot be defined and declared external in the same table (GPID)
A name cannot be defined and declared external in the same table (CTOK)
Change-Id: Ica80b59ad6a8af865bf1551ac4e014ec5f4e7d08
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26122
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the below:
1)
Nocturne board has only Max98373 speaker amp.
Update both NHLT and DT entries to include only Max98373
and not include DA7219.
2) I2S2 is used for Boot Beep.
So, update GPP_F0 ~ F2 pins accordingly.
3) Include DMIC-4ch configuration.
BUG=b:79362472
TEST=None [Waiting for HW to verify]
Change-Id: I0e9b3a564c22de6e84e96e5e937a3aca4ae73d75
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26143
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds subsystem_id for eve as 0x006B. The value
is set in nhlt structure which will be used by endpoints as well.
Change-Id: Id6910678c4d6e92ed45c776f174855efd26f9e27
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change:
1. Allows mainboard to add OEM table to CBFS
2. Provides mainboard specific smbios_mainboard_manufacturer that reads
OEM ID from EC using CBI and compares it against the OEM ID in CBFS
table to identify the right OEM string.
BUG=b:74617340
Change-Id: Iff54b12745de3efa7be0801c9a3a9f2a57767dde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use SUPERIO_DEV for global control device instead of DUMMY_DEV.
Change-Id: If3555906d359695b2eae51209cd97fbaaace7e61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25852
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From coreboot side, include DMIC 4ch NHLT configuration and its
DMIC blob. In OS side, cras picks the needed channels using UCM's
channel map configuration.
So, this patch updates to include DMIC 4ch config.
BUG=b:79158926
TEST=Verified 4-ch record with arecord
TEST=Also verified internal mic record with cras using
'cras_test_client --capture_file dmic.raw --rate 48000
--num_channels 2 --duration 10'
Change-Id: Ic6df00c2f26ad9cdf54152ab021c2b10499c429c
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses GPIO macro to define rt5663 headset codec's irq as
ExclusiveAndWake. This change allows jack detection even when
device is in D3 state.
TEST=Plug in/out jack when the system is in deep sleep and wake up
the system to ensure that jack insertion/removal is detected.
Change-Id: Icb72337025a8408ed7ea9b6e60e938dcb88eae76
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26016
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change OEM ID values to 6 characters to fix error compiling with IASL
version 20180427.
Also update table creator to 8 characters from 7.
Change-Id: Id6c9a7b08dc4a9efeb69011393e29aa5a6bc54c4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This gpio should be active low, but is not currently configured that way.
Changing gpio configuration to reflect that.
BUG=b:73121017, b:77941823
BRANCH=None
TEST=iotools mmio_read32 0xfdae0588 (GPP_E1) Make sure that when pen
is ejected, gpio is low and when pen is inserted, gpio is high.
Also tested that wake upon pen eject is working.
Change-Id: Ic49eea6412c3378dca39a3338b43df12bc27037d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit edf2f59b1d.
(google/kahlee: Resume on AC insertion)
The requirement to wake on AC insert is just to wake enough to charge,
not to wake the entire system.
BUG=b:77602394
TEST=None
Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add raydium controller
- Update elan controller with reset and enable GPIOs.
- Enable 'probed' so Linux will check which controller is being used.
BUG=b:78929054
TEST=Both elan and raydium touchscreen controllers work
Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't
exist in the apollo lake code. Remove it from reef as part of the
cleanup to update to the new version of IASL.
This was in commit 4f803ac28f (mainboards/google/reef: Add support for
tablet mode switch.)
Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up
the boot process by over a half second. Also, increase the Normal
Read speed to 33MHz as supported by the W25Q128FW.
BUG=b:70558952
TEST=Run cbmem -t to get boot times.
Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Changes in pin usage between yorp and bip
- LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66
- I2S0 interface is not used in bip. It was used in
yorp for DMIC Wake on Voice through Nuvoton EC.
Also fix both bip and yorp pin settings for
LTE_OFF_ODL (Enable LTE and add an internal pull up).
Internal pull up can be removed later when sub-board (which
will have an external pull up for this signal) is available.
BUG=b:77869623
BRANCH=none
TEST=Build coreboot for octopus.
Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures GPP_A23 as a wake source for the trackpad. We also
need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any
interesting signals in GPP_B, so we won't be missing it.
I don't have hardware with A23 wired up, so i just tested the wake
source using A19 which is essentially identical to A23.
BUG=b:78541883
TEST=verified we can trackpad can wake system from suspend
Change-Id: If800464c8b2319d758b1823850571919f85bdc6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This creates a phaser variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:78572180
TEST=None
Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.
BUG=b:78009842
Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change configures a weak internal pull-up on ESPI_IO1 line for
octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and
is expected to be open-drain. However, there is no external pull on
this line and so an internal pull-up is required to ensure proper eSPI
communication.
BUG=b:78497502
TEST=Verified that there is no eSPI communication failure between AP
and EC during boot-up and on suspend/resume.
Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the
stoneyridge Kconfig.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock.
This setup is needed when moving AGESA out of the bootblock. It sets the
SPI bus speed of the TPM access in verstage.
BUG=b:70558952
TEST=Boot with AGESA moved out of the bootblock.
Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The grunt touchpad interrupt can be used as a wake source. For grunt,
the touchpad interrupt uses GPIO5 which corresponds to GEVENT7.
BUG=b:77602771
TEST=In OS: # cat /proc/acpi/wakeup
=> D015 S3 *enabled i2c:i2c-ELAN0000:00
TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3.
Change-Id: I510642108a1257f6601f18c77cf3107573427f39
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25827
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO24 maps to GEVENT (GPE) 15.
The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO2 maps to GEVENT (GPE) 8.
BUG=b:78461678
TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3.
TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3.
Change-Id: Ib1809740837e686992ff70b81933159a5dff7595
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses
GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI
definition format a bit to match the format in the baseboard/gpio.h.
BUG=b:78461678
TEST=build coreboot for kahlee
Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch sets the NPK device off for octopus.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not
report "PCI: 00:00.2 not found, disabling it".
Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When GPIO tables were created, there was no study on which pins had to be
programmed ASAP and which could be programmed later. Execute such study and
move all non-critical gpios from reset to late.
BUG=b:76097508
TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video
playback, track pad, keyboard).
Change-Id: Icbc9370050d619800026035caaac3e89536a460a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With the increase of dimm->module_part_number size from 19 to 21 (commit
35b273eea3) "include/memory_info.h: Change part number field from 19 bytes
to 21", this code is now advancing outside DDR3 SPD designated space. The
correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make
sure to 0 terminate the string.
BUG=b:77943312
TEST=Build cyan.
Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds keyboard backlight feature for Nami platform
BUG=b:78360907
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.
Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These settings are identical to yorp settings except
overrides are not provided for sleep_gpio[] table which
is currently empty for yorp and cros_gpios[] table which
is not expected to change for bip.
BUG=b:77869623
BRANCH=none
TEST=Build coreboot for bip.
Change-Id: Icc205f576691427d78c9159dfdbced87e41a0517
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of preparing to make GPIO code independent of vendor code references,
convert GPIO table format using newly defined macros.
BUG=b:77999987
TEST=Build and boot kahlee.
Change-Id: I0af768bb4dbcbfef0d2d08ffe869c1dfb6827974
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change sets VmxEnable to 1 to match the kernel setting.
If this feature is enabled at the kernel level and not in FSP,
then there is an issue where FSP expects it to be disabled so
it forces a cold reboot on every warm reboot.
BUG=b:78129261
BRANCH=poppy
Change-Id: Idedbde1d8eb0c9e959733b7b50e5dec804d61cae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25698
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC code should not have been removed from devicetree when moving
over from grunt. This was causing various bewildering issues that
would happen on the first boot but not on subsequent reboots.
BUG=b:73235377
TEST=Grunt powers off and stays powered off at dev screen.
Change-Id: I225138fede66c6e189e0e79d1261d0d579f7cbdc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The EC pin definitions are GPEs, not the GPIO numbers.
BUG=b:74022675
TEST=Power status updates immediately when power is inserted.
Change-Id: Icc8330a606f7a85e72b65094462a684927986829
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25689
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating some GPIOs based on changes in the latest schematics. Also
renaming signals to match that of latest schematics.
BUG=b:73749640
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Make sure different SKUs still boot.
Change-Id: I7d912f4bc6765f065c75c68a45bdf9ee844e0c1d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With one additional EC change, Yorp is able to flash the EC as part of
software sync and successfully boot. This change is only made for Yorp
as we want this disabled for Bip bringup.
BRANCH=none
BUG=b:77874283
TEST=Successful flash and boot on Yorp with this change
TEST=Checked GBB flags on Yorp and Bip images with gbb_utility
CQ-DEPEND=CL:1014397
Change-Id: I4969b254c6a58fba9dd8d2f31feb25b55c7a0c65
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25692
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generalize cbfs_boot_load_struct() by passing in CBFS type
Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The commit enables DPTF function. The DPTF parameters are provided by
thermal team.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot then check the parameters in DPTF ui tool
Change-Id: I9b7ae34ee64f19ef783a8c1571831b2293105a18
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SPD file for sdp hynix_dimm_H5AN8G6NCJR-VKC (ram id: 15).
BUG=b:77893710
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I434d42ff12e6dae39e5676f36ba6cf00b3a48b06
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SPD file for sdp micron_dimm_MT40A512M16LY-075E (ram id: 14).
BUG=b:77930401
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: Ia44e70948e57c2f19664d874ae005ac39d748f92
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The EC should wake the system from S3 when the AC connector is plugged.
BUG=b:77602394
TEST=verify resume on insert with Grunt
Change-Id: I4bcaef2fe75283aaa6260b5b9efd408ff4b05f4c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
bt-pad-enable property is used by kernel driver to set
BT I2S PAD on ACP_BT_UART_PAD_SEL mux, for those platforms which
use these pins for BT I2S. By default the pins are set for UART.
BUG=b:72360151
TEST=Tested playback and capture on audio device connected to BT I2S
Change-Id: Id76bfa1fa1dde904f02a03b0c15986ecb1bbcc97
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25653
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit aef0d6b0a7.
This commit can only pass far-end USB eye diagram but will fail on
near-end. Confirmed with Intel we should revert it.
Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/25651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Turn on keyboard backlight in romstage to indicate that the system is
booting.
BUG=b:77921345
TEST=Boot grunt, keyboard backlight comes on.
Change-Id: Ib215b19ebdee2f8c4f431af775905eca42436d1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25636
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 70ba1b7e78.
This commit can only pass far-end USB eye diagram but will fail on near-end.
Confirmed with Intel we should revert it.
Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI interrupt routing file routing.asl is not reflecting AGESA settings to
the NB Interrupt Routing Registers. The AGESA settings are:
Device self INTA INTB INTC INTD
GPP 0 23 0 1 2 3
GPP 1 24 8 9 10 11
GPP 2 25 16 17 18 19
GPP 3 26 24 25 26 27
GPP 4 23 3 0 1 2
HDA none 22 23 20 21
GBIF none 6 7 4 5
Fix the routing table, considering that NB IOAPIC starts at interrupt 24.
BUG=b:74104946
TEST=Build and boot to a modified grunt board to enable the emmc. Then used
"cat /proc/interrupts" to get active interrupts. Also checked IOAPIC
redirection registers, which are now being programmed.
Change-Id: I60847c46f3f938f9e97d7b323b27d20e36aa2d02
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This reverts commit 06e3e1f055.
This commit can only pass far-end USB eye diagram but will fail on near-end.
Confirmed with Intel we should revert it.
Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25629
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables EC SMI when ESPI is enabled.
BUG=b:77857802
TEST= SMI is working in depthcharge.
Change-Id: I52726194b8346488e5ad781e78e33c5d286d132f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25569
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the recovery cache to speed up recovery flows. Also
enable clearing of the normal mrc cache on recovery forced retrains.
BUG=b:77871444
TEST=went into recovery twice. 2nd time it boots faster.
Change-Id: Idfce42ac835637fa521545fadfedecd65df91d4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Grunt supports a keyboard backlight, so enable the ASL code.
BUG=b:77455525
Test=Boot Grunt, verify that the string 'KBLT' is in the DSDT.
Change-Id: Idf0f23581bcba0b035c126c68fb167274d7c698a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25470
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of moving AGESA calls from bootblock to romstage, OemCustomize.c
of all boards using stoneyridge must be available at romstage.
BUG=b:74236170
TEST=Build grunt and kahlee, actual test will be performed at a later patch.
Change-Id: Ide9efdbff6a07c670034391c0d62e8b74fa5c02b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25528
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Vayne.
We need to disable rear camera on all Vayne sku.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera shown on Vayne
Change-Id: I6e7c1e8791462f00ad8336372954ee0a9465d9b8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the wake for EC to proper gpios.
BUG=77605178
TEST=Test that lidopen wakes up the system from S3.
Change-Id: Icbf30007403191005396027e74b9b6fb7319e006
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25539
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6).
BUG=b:77290144
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace
Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
The WP signal to the AP isn't inverted as it is on other platforms, so
it was reporting incorrectly. Change the ACPI table to be active low,
and invert the signal when reporting it to everything else.
BUG=b:74946358
TEST=Boot grunt with battery inserted, WP signals both report 1. Remove
battery, WP_CUR reports 0, WP_BOOT still reports 1.
Change-Id: Ic1369dbda609e34b308af308880449643be6af39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets PL1 value to ~6W. Here, 8W setting gives
a run-time 6W actual measured power.
Also, this patch sets PL2 value to 15W.
BUG=None
BRANCH=None
TEST=Build and read the MSR 0x610.
Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/25341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch selects `HAVE_APCI_RESUME` to enable S3 resume. This
has a dependency on EC to store the hash.
BUG=b:72472969
TEST=suspend and resume from S3 should work.
Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25390
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new variant of Poppy for the Atlas board.
BUG=b:75454415
TEST=tested on a P0 board. System boots and is mostly
functional, though some peripherals are not ready so there
are no touchpad/touchscreen devices configured yet.
Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates devicetree and GPIO configurations to match the
schematics:
1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and
deemphasis_enable for [2] need to be set instead of [0].
2. WLAN power enable, wifi disable and PERST# GPIOs need to be
configured correctly.
BUG=b:76180142
TEST=Verified that wlan0 scan works.
Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves the sandybridge both smm setup and smihandler code to a
common place.
Tested on Thinkpad X220, still boots, resume to and from S3 is fine
so smihandler is still working fine.
Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch disables debug consent in the devicetree. When debug
consent is set to DBC by default, it prevents some clocks from turning
off during S0ix. This blocks S0ix entry.
This patch also enables S0ix from the devicetree.
BUG=b:76163091
TEST=enter S0ix and check if slp_s0 is asserted
Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/25312
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8).
BUG=b:76086834
TEST=Verified that the device with this memory part boots to OS fine.
Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25379
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add an SPD for this particular Hynix memory type to the poppy board
so it can be used by poppy variants.
BUG=b:75454415
Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Current emmc tuning parameters for octopus were copied over from other
boards and result in failure to boot from emmc. This change gets rid
of the emmc tuning parameters in devicetree. Once emmc tuning tests
are run for octopus, these parameters can be added back.
BUG=b:75986903
BRANCH=None
TEST=Verified that octopus boots from eMMC without any errors in
depthcharge.
Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change remove work-around code for the power issue of MIPI and
USB cameras on previous board revision. With the work-around code,
PMOF ACPI method cannot turn off MIPI camera. So we need to remove
it.
BUG=b:74214248
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/25337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=build
Change-Id: I32d185741ce20a3a82e6895de3026ade52d0bcc8
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Build for octopus.
Change-Id: I2239aa70cb708e6e1c06339ca9d517e7eaa198ed
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25310
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new Kconfig option for mainboard octopus "HAS_TPM"
that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA
is not selected.
BUG=b:76203913
TEST=Compiles fine with mocktpm.
Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25340
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Always report that EC is in RO mode. This is a temporary workaround
for a hardware issue that is causing EC to appear to be in RW mode
when it is not. This change will be reverted once transition is made
to newer hardware.
BUG=b:74215817
BRANCH=master
TEST=Verify meowth can boot to recovery's insert screen.
Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase
it was idle.
Google CFM add-in card is going to use this I2C bus so it needs to be
re-enabled.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is
working properly.
Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/25258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This creates a bip variant for octopus. Nothing is set in the variant
files here-- everything is picked up from baseboard.
BUG=b:75976864
TEST=None
Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to
read the sku id. In order to support "-1", we need to use
uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type.
Otherwise, tools/scripts will read 65535 instead of -1.
Another reason to change this is that sku_id can be
supported by ec up to 4 bytes.
BUG=b:73792190
TEST=mosys output "Platform not supported" for -1 sku id
arc-setup read -1 sku id
Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Audio machine driver will enable/disable clock by making it as
a CCF clock in kernel.
BUG=b:74570989
TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/
on 4.14 kernel
aplay -vv <file>
check register to see clock enabled
kill aplay
check register to see clock disabled
Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the EC communication a little earlier so we can read the board
ID before programming GPIOS.
BUG=b:73078053
TEST=Build & Boot grunt, board_id() now gets ID correctly
Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25286
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the schematic, Octopus boards have WLAN_PE_RST connected to
GPIO_164. This change configures that properly in devicetree.
BUG=None
TEST=None
Change-Id: I2ba4839e036f02c5e0316d08599894879133894a
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25248
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO pad configurations for GPIO68-71 are incorrectly configured as
outputs. This change corrects them to be inputs.
BUG=b:74932341
TEST=None
Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25217
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO for EEPROM write-protect should be configured early, before
romstage. This change configures that pad earlier. This pad is the same
on the existing Octopus schematics.
BUG=None
TEST=None
Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We are enabling at the kernel level, but that is triggering an issue
where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot, clearing the ramoops logs. Enabling in BIOS so it
matches what the kernel expects.
This is the same change that were done for eve:
https://review.coreboot.org/#/c/22449/
BUG=None
BRANCH=None
TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT
check for /dev/pstore/console-ramoops
Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO
results in EC communication failure. This change removes the
configuration of GPIO_149 as GPO in ramstage so that it remains
configured for ESPI (as it was when AP came out of reset).
BUG=b:75348718
Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1) Set the critical temperature threshold to 100C to match changes
on other boards. This is intended to reduce DPTF-initiated thermal
shutdowns before it has had a chance to react.
2) Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
BUG=b:67459049
BRANCH=eve
TEST=manual performance/power testing on Eve hardware
Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in
the latest schematics.
BUG=b:74347464
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).
BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.
Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/25110
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable System Agent dynamic frequency support by default.
BUG=None
TEST=Build and flash with debug version FSP, check SaGv in serial print
to be set to "4".
Change-Id: I7dd29db206b06e600407bb0b1d0bc7530f4ac93e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25093
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since nami proto did not have any external pull on MEM_CONFIG_4, use a
weak internal pull down before reading it.
BUG=b:74420123
TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami.
Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current lpddr4 skus entries do not match the RAMID table in the
schematic. This commit updates that so they are consistent. Thankfully,
the values are the same as for glkrvp, so I just copied from there.
BUG=b:74392818
TEST=None
Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following gpios are no longer needed and are now configured as
no-connects : GPP_C6, GPP_H4, GPP_H5
BUG=b:74406599
BRANCH=master
TEST=none
Change-Id: I55769336195db0e57dfbaf5b5770e15050138341
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make sure that fields that are not updated in
variant_memory_params keep a default value of 0.
In particular, use_sec_spd is intended to have a default value of
0 on all platforms. Without this patch, a random value is used
and all boards (except nami) get stuck on boot.
BRANCH=poppy
BUG=b:74439917
TEST=Nautilus and poppy can boot, and do not get stuck at
"CBFS: 'sec-spd.bin' not found."
Change-Id: I06c6511625de930903ae13788bdcd27667a17886
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://review.coreboot.org/25101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
we had disabled software sync for bringup - we now have enough
functionality in place to turn on software sync.
Change-Id: Ib7f5a24ed8a47cb44b3f505e3cd49e0cb6931dc0
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23630
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the
spd target expects.
TEST=Verified that sec-spd.bin is present in coreboot.rom
Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GPIO 40 isn't currently being used, so set it to be an input.
BUG=b:73387647
TEST=Build & boot grunt
Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Bayhub part is not used on proto with board_id 0, so disable it.
BUG=b:74248569
TEST=Build & boot Grunt. Bayhub part is disabled.
Change-Id: I635356d41bab637726594d403d66dde730f12256
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This #define tells superio.asl to add a "PNP0501" "Plug and Play
16550A-compatible COM port" entry to kahlee's ACPI tables.
The EC on kahlee boards do not provide a "Serial Port 1" that should
be exposed via ACPI to the OS. In fact, this entry confuses the
kernel and in some cases can cause it to try to redirect output to a
non existing port.
BUG=b:74200887
TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and
"earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel
command line, and with an image with serial console enabled.
=> System boots with (kernel) serial console enabled, starting from
0.00 (earlycon), with no gaps in its output, and serial console
also allows logging in.
Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Hardware updates have suggested we need to configure the K&D panel's
power sequence in software, not in hardware. Without this change, K&D
panels will no longer power on correctly and will instead display a
black screen.
Per K&D's suggestion, we tweak these two commands. From the little HW
docs I have, this looks like it's:
(Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to
1
(Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from
MIPI_TE(0001b) to BC_CTRL (0010b)
BRANCH=scarlet
BUG=b:73133861
TEST=KD display with and without HW fix on Scarlet
Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://review.coreboot.org/25023
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures the gpios for all the gpio communites.
Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Per vendor datasheet, corrected linkfreq of imx258 as
{633600000, 320000000}
BUG=None
BRANCH=None
TEST=Verified the MIPI and USB camera function on DUT board
Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/24990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We want to report the board SKU via the SMBIOS tables. Add support for
this, obtaining the ID itself from the EC.
BUG=b:74175244
BRANCH=none
TEST=manually on grunt with another CL:
mosys platform sku
0
Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/25011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As per the latest schematics, this change configures GPP_B0 as wake
source for WLAN.
BUG=NONE
BRANCH=master
TEST=emerge-nautilus coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b
Reviewed-on: https://review.coreboot.org/23526
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alkali will use LPDDR3, so need to have Nami support both
DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO.
BUG=b:73514687
BRANCH=None
TEST=None
Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add spd files for LPDDR3 based on info received from factory team.
BUG=b:73287172
BRANCH=None
TEST=None
Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/25001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some type-c monitors do not immediately assert HPD. If we continue
to boot without HPD asserted, Depthcharge fails to show pictures
on a monitor even if HPD is asserted later.
Also, if an HDMI monitor is connected, no wait is needed. If only
an HDMI monitor is connected, currently the API always loops until
the stopwatch expires.
This patch will make the AP skip DisplayPort wait loop if it detects
an HDMI monitor. And if an HDMI monitor is not detected, the AP will
wait for DisplayPort mode (like before) but also its HPD signal.
This patch also extends the wait loop time-out to 3 seconds.
BUG=b:72387533
BRANCH=none
TEST=Verify firmware screen is displayed even when a type-c monitor
does not immediately assert HPD. Verify if HDMI monitor is connected,
AP does not wait (and firmware screen is displayed on HDMI monitor).
Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot
and should not be used as a UART device. coreboot is setting the
pins to GPIO Mode but FSP is re-configuring them for Native Mode
and the behavior is unexpected when the kernel tries to initialize
the UART device.
The UART 0 device is PCI function 0 so it needs to be enabled for
other functions to be visible to the OS so it can't just be disabled.
Instead, set the device to PchSerialIoSkipInit so that FSP will not
change the pin state.
BUG=b:73006317
TEST=Tested with add-in card on fizz hardware to ensure the pin state
does not change when FSP runs or the kernel boots.
Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/24973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 2e81f394cf, as it will
have side effect that will make system shutdown failure. System will not
enter S5 sleep state, instead a global reset will be generated.
Once camera driver ACPI framework ready, isclk programing will be moved
into APCI method, in _PS3, isclk will be turned off to save power.
BUG=b.72532565
BRANH=master
TEST=Apply the changes and flash coreboot, on meowth devices, issue
"halt" in OS stage, system can shutdown successfully.
Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for variants to use secondary SPD if
required. This enables a variant to have different types of memory
supported using the same image.
BUG=b:73514687
Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Similar to Soraka, this change sets the pch_trip_temp value to
75C. This is important so that PMC can shutdown the thermal sensor
when CPU is in C-state and DTS temp <= pch_trip_temp.
BUG=b:74089135
Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/24968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a
common location) makes some platforms use the wrong OIC register defi-
nition. It was extended to 16-bit in the corporate version of ICH10.
So let's give the new size and location a new name: EOIC (extended OIC).
This only touches the systems affected by the mentioned change. Other
platforms still need to be adapted before they can use the common RCBA
definitions.
Change-Id: If9e554c072f01412164dc35e0b09272142e3796f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/24924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3.
BUG=b:72120814
TEST: Boot to OS via NVMe
Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/23208
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel DCI (direct connect interface) allows debug Intel target using
USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0
only.
BUG=None
TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot
image. Using DAL to halt/run CPU.
Change-Id: I39e68dabfcb9e659733019334299e562eee3681d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
If switch to VT2 on nautilus, screen flicker appears. We found if we
rollback the change of slew rate setting, then the flicker issue will
be gone: https://review.coreboot.org/c/coreboot/+/22588
But nautilus board needs slew rate tuning to reduce EE noise, so we
decided to change only SlowSlewRateForSa to 2 (Fast/8) instead of
rollback the whole change of the CL:22588. It can remove the flicker on
VT2.
BUG=b:71397040
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: Id1d4bd8b1316c02c783de708ec4658e030193a26
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Due to there are some chances USB devices can not be detected.
USB2 port#1 and #4 PHY register need to be overridden for variants
Santa/Lava/Blue/Bruce/Astronaut.
port#1:
PERPORTPETXISET = 4
PERPORTTXISET = 4
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
port#4:
PERPORTPETXISET = 7
PERPORTTXISET = 7
IUSBTXEMPHASISEN= 1
PERPORTTXPEHALF= 0
BUG=b:72623892
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I401905685cc3078df657919b162272c3de320296
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/23881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The GPIOs for PCIe reset and power enable for WLAN must be set up before
amdinitearly for wlan to function.
BUG=b:73898539
TEST=Boot, see WLAN controller in lspci
Change-Id: I568a3240a54817ab6dcf15fe39f7f1336943852b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24916
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- consolidate commonality in meowth and zoombini's SPD makefiles into
a common zoombini/spd/Makefile.inc
- move all SPD hex files into zoombini/spd directory
- move SPD_SOURCES definitions to variants/$(VARIANT_DIR)/Makefile.inc
BUG=b:69011806,b:71776625
BRANCH=master
TEST=Verify 'emerge-meowth coreboot' and 'emerge-zoombini coreboot'
compile and boot successfully.
Change-Id: I2291ebaf0ef5da1b22eb0e8fa7af8dbb50848c29
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23874
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
While programming interrupts, a message "perhaps this device was defined
wrong?" shows up twice. This is caused because some devices have
interrupt programmed for APIC mode, but not for non-APIC mode. Fix
mainboard_picr_data table by identifying devices programmed with value
0x1F while programmed differently on mainboard_intr_data table. Do so
only for devices that are used by kahlee or interrupt required by old OS.
BUG=b:70788755
TEST=Build and run kahlee, Verify that message disappears from serial
output.
Change-Id: Ic285036290519ed3ee617dffa616bd26c61575c5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit uses newly defined macros to make it easier to read which
iomux function pads are being configured to use.
TEST=Booted grunt, confirmed display backlight came on.
BUG=b:72875858
Change-Id: I24e5091fc7ef696f8e9c932ce04664e6cc3ccb90
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's no need to set the output enable here; this is already handled
by the native function. I'm making this correction in this change to
prevent the GPIO pin descriptions from getting confusing.
BUG=b:72875858
TEST=Booted, confirmed S5_MUX_CTRL high with and without this change.
Change-Id: I9e047be7169586c59892ef2bdab915683feeebda
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on PCH iSCLK for meowth platform.
BUG=None
TEST=Boot up into OS and check register programming with iotools, the
command is iotools mmio_read32 0xfdad8000, returned value is 0x03.
Change-Id: I1e44e3748c9b37c8f60adcc47a866d445d77cfaa
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed
from the latest EC codebase, so don't try to build them by default
anymore.
Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For variants that have a cr50 tpm, this enables faster polling when
interacting with the tpm.
BUG=b:72838769
BRANCH=none
TEST=verified on grunt that irq is used and not timeouts for tpm
Change-Id: I5786d334b6c1cc70f4c7107c75b07a7e27ac4428
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the Pmax setting in device tree. The Pmax is from
MAX(PL4_sku1, PL4_sku2, ..) + ROPmax. Given ROPmax is 30W and
the maximum PL4 is from U42, hence the Pmax = 71W + 30W = 101W.
BUG=b:72138778
BRANCH=None
TEST=USE=fw_debug emerge-nami chromeos-mrc coreboot chromeos-bootimage
& ensure the Pmax value is passed to FSP-S.
Change-Id: Ief6a134dc5b6bd2b8e07b4a44450e99ff26402d9
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
AmdInitPost returns AGESA_WARNING. This is because AGESA by default
enables bank interleaving, while the HW does not meet the requirements
for it. Disable bank interleaving, thus clearing AGESA_WARNING.
BUG=b:73118857
TEST= Build and run kahlee. Search for "agesawrapper_amdinitpost()
returned AGESA_SUCCESS".
Change-Id: Ice9270f9b10051dbb622344919223cf5439f5d7b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fizz fails to show pictures on a type-c monitor because VBIOS runs
before DisplayPort link is ready.
With this patch, when firmware needs to display something, Fizz calls
google_chromeec_wait_for_display to make sure display is ready.
The penalty is up to 2 sec per boot in dev and rec boot. Normal boot
won't affected unless there is EC update.
BUG=b:72387533
BRANCH=none
TEST=Verify screens are displayed on Fizz as follows:
1. Put DUT in normal mode
2. Flash EC image to trigger EC sync (critical update)
3. Trigger manual recovery (insert)
4. Hit ctrl+d to switch to dev mode (to-dev)
5. Confirm to reboot (dev warning)
6. Warm reboot (dev warning)
7. Cold reboot (dev warning)
8. Flash EC image to trigger EC sync (critical update)
9. Trigger manual recovery (insert)
Change-Id: I90befe94f93e13904987acda50b2598d034b0031
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Soraka, Poppy & Nautilus are designed to operate at max power of
45 Watt. Hence set psys_max to 45W.
BUG=b:66066340
BRANCH=None
TEST=Build and boot soraka.
Change-Id: If6f624733830b462329b5f539c20e2aea664143e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/23757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable the micro-controller interrupt line as a real IRQ.
BUG=b:71986991
BRANCH=none
TEST=on Meowth, run 'ectool --name=cros_fp fpmode capture' and see the
number of interrupts incrementing and the MKBP event happening.
Change-Id: Ic0cf03d2a3508148b6482a5a595eaa213eff52c7
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Turns out the write-protect GPIO polarity for Scarlet is different than
for Kevin/Gru, and nobody ever told us. Also, it must not be configured
with an internal pull-up or we'll not read the correct value. This patch
fixes both issues.
BRANCH=scarlet
BUG=b:73356326
TEST=Booted Scarlet, confirmed that crossystem wpsw_boot returns the
right value in all cases.
Change-Id: Idd348ecdf9da8fff7201b83e869ba097b8570f32
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change enables DPTF and configures the policy. DPTF parameters were
provided by internal power team.
BUG=b:67877437
BRANCH=master
TEST=emerge-nautilus coreboot
Change-Id: I31b31d5282ab38278bc68045ce75fdc6192f1144
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/23731
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Original SPD provided by the vendor had bytes after 254 shifted by 16
bytes. This change fixes the SPD data based on the latest details
received from the vendor.
BUG=b:72749394
TEST=Verified that the device with this memory part boots to OS fine.
Also, mosys is able to dump the right memory information.
Change-Id: I6938dea761c5785048aad69eeeaf50e2d0fa8ca1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
