Scarlet don't have eDP and MIPI driver is not ready, skipping
display for now or else Scarlet would be stuck in
reading eDP HPD because there even not power for it.
TEST=boot to kernel on Scarlet
Change-Id: I02ab4ef21bf77b98414f537aca57b46c11922348
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19237
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Due to issues with stability limit the SKU with K4EBE304EB-EGCF
memory to 1600MHz instead of 1866MHz.
BUG=b:37172778
BRANCH=none
TEST=pass stress testing on devices with this memory
Change-Id: I02af7e9c35e2c5b0b85223d58025cbd29841d973
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19227
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is needed if one wants to use the header more than once.
Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Update the I2C rise/fall timings based on newly measured values
on a new board with updated pull-up resistor values.
Touchscreen: rise time 98ns, fall time 38ms
Touchpad: rise time 111ns, fall time 41ns
TPM: rise time 112ns, fall time 34ns
BUG=b:35583133
BRANCH=none
TEST=Each I2C bus frequency was verified on a scope to be ~400MHz
Change-Id: Ibb3a15fa0cc862f36c1b9c63ac7847221020c4c0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19202
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This fixes the following issues, with no functional changes:
ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful
2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
Verified that the binary was the same before and after the changes.
Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19078
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
All boards select INTEL_EDID, move it to nb folder.
Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
Change-Id: I88b5ef8e12ac606751952a493f626e1b146e98f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add package options to the CPU Kconfig that may be selected by the
mainboard's Kconfig file. Stoney Ridge is available in FP4 and FT4
packages and each requires a unique binaryPI image. Default to the
correct blob used by the northbridge by looking at the CPU's package.
Also modify Gardenia to select the right package.
See the Infrastructure Roadmap for FP4 (#53555) and FT4 (#55349) for
additional details for the packages.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 7b8ed7b732b7cf5503862c5edc6537d672109aec)
Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18989
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I0ad1cbf244501207af96e0ac415a5b80ced91052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The term 'callout' has a specific meaning in AGESA, meaning
invoking the said function from AGESA / PI proper.
OemPostParams() does not fall into that category.
Change-Id: I45913d93323b3813fc35b1dd1fdca3d782d4b01f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
BUG=b:35583511
TEST=check i2c bus 0 initializes from ap console log
Change-Id: Ibb6709159f5ed28ad0b62397d2ddb504dec55167
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/19105
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
Even though the i2c spec has no minimum data hold time in fast
mode the trackpad vendor indicates 300ns is their minimum. However,
the topology of the board uses FET isolation to cross voltage
domains. Therefore, the default 300ns which should work isn't reflected
on the device side of the voltage isolation circuit. Therefore,
increase the data hold time to show an observed data hold time of
more than 300ns on the device side.
BUG=b:36469182
Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19065
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC
provides a display controller with three independent pipes (1x eDP and
2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device
that enables connectivity between an eDP source and LVDS display panel
(http://www.nxp.com/documents/data_sheet/PTN3460.pdf).
The bridge contains an On-chip Extended Display Identification Data
(EDIT) emulation for EDIT data structures.
This patch sets up PTN3460 to be used with the appropriate LCD panel.
Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19043
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adjust gpio settings according to the hardware layout.
Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18995
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/19018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Tested-by: build bot (Jenkins)
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This callback was only required for a single mainboard, and it can
easily be moved to mainboard-specific code. This patch removes it from
the global namespace and isolates it to the Jecht board. (This makes
it easier to separate vboot and chromeos code in a later patch.)
Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18980
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in
practice. We can't have a dynamic work buffer unless we start in/after
romstage, and there'd be no reason to go with a static buffer if we do.
Let's get rid of one extra option and merge the two.
Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18979
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18619
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This board has a socketed SOIC-8 4 MB flash chip. All the flash
regions are unlocked by default but unfortunately flashrom
doesn't work with the original firmware and the stock UEFI flash
tool refuses to flash the coreboot image (different image ID).
For now, the external programmer seems to be the only option for
the first coreboot flashing.
Tested and working:
* Debian GNU/Linux Stretch (with Linux kernel 4.9, SeaBIOS)
* Microsoft Windows 7 installer with VGA blob (SeaBIOS)
* Internal GPU, both with VGA blob and libgfxinit (VGA and DVI)
* External GPU
* RAM (tested 8 + 8 GB)
* S3
* USB, both the 2.0 and 3.0 ports
* Sata
* Thermal management
* Sound
* LAN
* Bluetooth
* VT-x and VT-d
* me_cleaner
Not working:
* Microsoft Windows 7 installer with libgfxinit
Untested:
* Backside Mini PCI-E port
* DisplayPort and HDMI ports
Issues:
* The USB is always powered, even is S3 and S5 (like in the
original firmware).
* Internal flashing with flashrom doesn't work after resuming
from S3.
* The raminit is unreliable, as the RAM training sometimes fails
and sometimes succeeds, with the same couple of RAMs. Once
a MRC cache has been created, the raminit works fine.
* If an external card is inserted and the option
ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU
disappears completely from the PCI bus.
Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18564
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining SIO_EC_ENABLE_PS2K by default for all boards and
doing an undef in variant/onboard.h, move the definition of
SIO_EC_ENABLE_PS2K to variant/onboard.h. This avoids dependency
between different *.asl files.
Change-Id: I83e4ce42a594e952a443c618d7ef9840113027b9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18965
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Change preprocessor #if to standard C if. This will get optimized
out if the config option is disabled, but lets the compiler check the
contents.
- CONFIG_USBDEBUG is always going to be defined even if it's disabled,
so this check is not going to work as expected.
See the coreboot Kconfig documentation in /Documentation/core/Kconfig.md
Change-Id: Ia63438d9525e79307d9229ad3ffa2962978611d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18974
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
1. Remove CPU throttling effect of the charger sensor
Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
2. Change TSR1 influence from 200 to 100
3. Change TSR2 sample period from 120s to 30s
BUG=b:35585781
BRANCH=reef
TEST=built, and verified on snappy by thermal team.
Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Creating google/fizz directory based on poppy (using kabylake and FSP
2.0). Only making name changes and Copyright year changes. Many
poppy-specific configs left in and will be updated in follup CLs.
BUG=b:35775024
BRANCH=None
TEST=Compile fizz board
Change-Id: Icab3639a53fef65e904e797028916fda879fff7c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/18796
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Replace the use of the old device_t definition inside
mainboard/samsung/stumpy.
Change-Id: Ie6209b3b40d9aad0723690e7aeb3edfd0bfcc4a8
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17304
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace the use of the old device_t definition inside
mainboard/samsung/lumpy.
Change-Id: I39fe6bad42b3b0772d09d0fa7af357b797b8e04f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17303
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace the use of the old device_t definition inside
mainboard/technexion/tim5690.
Change-Id: I661daa5ab34c70db8ed783e5bf1114877f13b548
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17307
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
1. correct DPTF TCHG target device to TSR2
2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18920
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since SD card controller is expected to enter D3hot by runtime power
management if there is no card inserted, we need to use a sideband IRQ
pin which is not under the control of the controller. Thus, configure
GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect
pin.
BUG=b:35586693
BRANCH=None
TEST=Verified on a reworked poppy board that card detect works fine.
Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18926
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, it’s impossible for the user to select `NO_POST`, for boards
selecting `CONSOLE_POST` in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS) selects CONSOLE_POST which has unmet
direct dependencies (VENDOR_SIEMENS && BOARD_SIEMENS_MC_BDX1 || !NO_POST)
```
This is currently done for Intel Camelback Mountain and Siemens MC-BDX1.
Selecting the option `CONSOLE_POST` in board specific configuration is
not a good idea, as this should be user configurable over Kconfig, and
also the tree-wide defaults should be the same for these options.
Kconfig is different, as commit 97535558f1 (mainboard/{google,intel}:
Change config option selection) only touch the Intel board.
Change-Id: I91c1e0cb92ed218b6bbc7c33759b91f748cf6f51
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18878
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently, it’s impossible for the user to select `NO_POST`, for boards
selecting it in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct
dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M ||
BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M
|| BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 ||
PC80_SYSTEM && !NO_POST)
```
This is currently done for Intel Mohon Peak, and its descendants.
Selecting the option `POST_IO` in board specific configuration is not a
good idea, as this should be user configurable over Kconfig, and also
the tree-wide defaults should be the same for these options.
Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18877
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We just support Raydium touchscreen instead of Elan.
Thus we have to remove Elan touchscreen device
and add Raydium touchsrcreen device.
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18789
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is achieved by setting up Kconfig and Kconfig.name very similar
to how variants are used.
Change-Id: I22089ff29e3879d7956527a092a0ac6425b05cb3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17894
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by
standard hid i2c Linux driver.
BUG=b:35586513
BRANCH=reef
TEST=build, boot on snappy, and verified acpi node "WDHT0002" created.
Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18874
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
It's not relevant to throttle CPU based on the charger sensor.
So, remove this CPU throttling effect.
BUG=b:35908799
BRANCH=master
TEST=Built and booted on Electro DUT
Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We have code for certain Veyron variant names that were either never
made into an actual board (Gus, Nicky, Thea) or used for Google-internal
test boards that no longer exist (Pinky, Shark). Let's clean them out to
avoid confusing people.
Change-Id: Icdce5f0f3613e089d0994318b02dba54170f0c42
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18860
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With a recent patch (google/veyron_*: Add new Micron and Hynix modules)
we switched RAM codes for Veyron boards to tri-state since we were
running out of binary numbers. Unfortunately we only tested that change
on Minnie and Speedy, and it turns out that it broke Jaq, Jerry and
Mighty. The "high" RAM code pins on those boards were incorrectly
strapped with 100Kohm resistors (as opposed to 1Kohm on Minnie and
Speedy), which is too high to overpower the SoC-internal pull-down we
use to differentiate "high" from "tri-state". Since we already used
tri-state codes on some Minnie and Speedy SKUs we have to hack up the
code to work differently on these two groups of boards to keep
everything working.
BRANCH=veyron
BUG=b:36279493
TEST=Compiled, confirmed ram_code called the right function depending on
board.
Change-Id: I253b213ef7ca621ce47a7a55a5119a167d944078
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18859
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that EC on poppy is stable, it is time to switch on EC SW sync.
BUG=b:36178824
BRANCH=None
TEST=Verified that EC SW sync is done properly and device boots to OS.
Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18838
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
This is a clone of Duncan's patch for eve
at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
BUG=none
BRANCH=none
TEST=test on poppy that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18853
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The kernel driver for rt5663 expects to get an interrupt on both
a rising and falling edge, and using a legacy interrupt doesn't
provide that flexibility.
Instead configure this pin as a GPIO and use the interrupt through
the GPIO controller. This allows using GpioInt() with ActiveBoth
setting and results in correct operation of the headset jack.
BUG=b:35585307
BRANCH=none
TEST=test on Eve that headset jack detect is read properly at
boot, and that plugging in and removing both generate a single
interrupt event in the driver.
Change-Id: I6f181ec560fe9d34efc023ef6e78e33cb0b4c529
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18836
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On the ASRock E350M1, with Linux 4.10 after resuming from S3, the PS/2
keyboard does not work. Adding the ASL code, fixes this.
The Linux messages change like below.
Before (equivalent to `i8042.nopnp`):
```
kernel: i8042: PNP: No PS/2 controller found.
kernel: i8042: Probing ports directly.
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: serio: i8042 AUX port at 0x60,0x64 irq 12
kernel: mousedev: PS/2 mouse device common for all mice
```
After:
```
kernel: i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
kernel: i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
kernel: serio: i8042 KBD port at 0x60,0x64 irq 1
kernel: mousedev: PS/2 mouse device common for all mice
```
Change-Id: I0a06311860398cac9cf1a077e3aba75da779f45d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18574
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_DVT_v0.6_20170314.xlsx)
1. Increase PL2 Max to 15W.
BUG=b:35583586
BRANCH=reef
TEST=build and verify PL2 Max value on electro dut
Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
commands:
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I02eb0ef647cd34c13a5fe8be0bdbe1bb38524d0c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18821
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Keep the BOOT0 pin triggering the MCU bootloader as an input,
so the Servo debug board doesn't have to fight with the PCH to program
it, the net already has an external pull-down to ensure that the MCU is
in normal mode at boot.
By default, do not drive the FP sensor reset from the PCH, the MCU is
now managing the reset line (but the PCH still has a connection on the
current boards).
BRANCH=none
BUG=b:36025702
TEST=manual testing, program the MCU through a Servo v2 board, and use
the FP sensor through the MCU and verify it is not stuck under reset.
Change-Id: I19113b5d78013d0ab6ec5a72c6f71dd4c67a88e8
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/18830
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Set the AC and DC loadline values based on the KBL-Y 2+2 defaults
that are applied by FSP. These will be tuned later and are exposed
as defaults so the engineers know what to start with.
BUG=b:36228330
BRANCH=none
TEST=Build and boot on Eve and check debug FSP output to ensure that
it is applying the provided loadline values
Change-Id: Ieae4f2b201d8210e75bdb9438070a3a2e1fda6b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.
This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.
Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.
BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve
Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
On this platform the DMICs are connected to the rt5514 DSP instead
of directly connected to the SOC. Use the new rt5514 NHLT blob
instead of the 4ch DMIC blob and add the required I2C and SPI
entries in devicetree so this can get probed properly.
BUG=b:35585307
BRANCH=none
TEST=build and boot on Eve P1 and check for rt5514 driver enumerated
by the kernel
Change-Id: I0f2cb532771ee1857df7f33c52a96acf96dc1f54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18817
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch make some general adaptations in relation to commit 6a489237
(mainboard/intel/leafhill: Clean up).
- add necessary defaults to Kconfig
- remove irrelevant entries from FMD file
- include romstage file for better understanding
Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18808
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add FPF_STATUS region under MISC_RW. The purpose of the region is to
store FPF status.
Change-Id: I2997b3d39a94bf444df51068f254edcf49c47afd
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18773
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
#!/bin/sh
#
# The necessary tools were built and installed using the following
commands:
#
# pushd 3rdparty/vboot
# make
# sudo make install
# popd
#
# The keys were made using the following command
#
# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
# --4k --4k-root --output $PWD/keys
#
#
# Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
#
# Add the empty GBB to the coreboot.rom image
#
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
#
# Add the keys and HWID to the GBB
#
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
#
# Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sand is not convertible and no EC sensor sends event from EC to AP.
That event default is tablet mode, we don't have to enable tablet event.
Modify the ec.h, is based on <baseboard/ec.h>
BUG=b:36108742
BRANCH=reef
TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work.
Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable an internal pull-up on the power button input as short
press is resulting in power button override being asserted.
BUG=b:36111214
BRANCH=none
TEST=tested on poppy board to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/18734
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock
code as pnp devices.
Fixes USB and serial on the dock, if it is already connected when
computer is powered on. DVI and ethernet worked without this patch.
Hot-plug is yet to be fixed.
Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.
Assign the sdcard card detect pin in devicetree for reef variants.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=None
Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below.
```
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20160108-64
Copyright (c) 2000 - 2016 Intel Corporation
dsdt.aml 245: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 262: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 277: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 295: Method(_CRS, 0) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
```
Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18323
Tested-by: build bot (Jenkins)
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.
BUG=b:35775104
Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.
BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.
Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We build with WARNINGS_ARE_ERRORS, while IDS tracing will
raise various (non-fatal) printk() format warnings.
Change-Id: I9dc81c89ee60d17a6556a412380fed1413af66bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18560
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is required to transmit button information from EC to kernel.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18642
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.
The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.
Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.
BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.
Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fine tune USB2, need to override the following registers.
port#1:
PERPORTPETXISET=7
PERPORTTXISET=0
BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel
Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Declaration of main in cpu/amd/car.h conflicts with the
definition of main required for x86/postcar.c in main_decl.h.
Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18615
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.
Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix the error detected by checkpatch and update the copyright date.
TEST=Build and run on Galileo Gen2
Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram
frequency, while bob uses 800 MHz.
It's normal some variants can't meet 928 MHz SI requirement and hence
have to use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800 MHz on bob
Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2
Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/420208
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Original-Reviewed-on: https://chromium-review.googlesource.com/448277
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18581
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0.
For clarity, sdram-ddr3-samsung-2GB now is used by
- K4B4G1646D-BYK0
- K4B4G1646E-BYK0
- K4B4G1646Q-HYK0
BUG=chrome-os-partner:62131
BRANCH=veyron
TEST=emerge
Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4
Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/446197
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405)
Original-Reviewed-on: https://chromium-review.googlesource.com/446300
Reviewed-on: https://review.coreboot.org/18519
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This adds SDRAM entries for the following modules:
- Micron: DDMT52L256M64D2PP-107
- Hynix: H9CCNNNBKTALBR-NUD
They are compatible with Samsung K4E8E324EB-EGCF, so this just
copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used
in the comment near the top.
Notes on our "special snowflake" boards:
- veyron_danger's RAM ID is hard-coded to zero, so I skipped changes
involving the binary first numbering scheme.
- Rialto's SDRAM mapping is different, so I padded its SDRAM entries
to 24 to match other boards.
- veyron_mickey requires different MR3 and ODT settings than other
boards due to its unique PCB (chrome-os-partner:43626).
BUG=chrome-os-partner:59997
BRANCH=none
TEST=Booted new modules on Mickey (see BUG)
Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3
Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/412328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com>
Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com>
Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6)
Original-Reviewed-on: https://chromium-review.googlesource.com/446299
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18518
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Configure the right GPIOs for finger print sensor interrupt and reset
lines.
As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.
Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18389
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Status:
- The primary PCIe 16x slot works:
It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
When plugging a GPU inside, it's not seen with lspci
- SATA works: The board fully boots GNU/Linux
- Serial doesn't work
- Populating the RAM slots might have to follow
the recommended memory configuration that is described
in the mainboard manual in order to be able to boot.
Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.
Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.
Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/16931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This file is only static defines.
Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This is selected by default and not overwritten anywhere else for this
board.
Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18541
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.
Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: https://review.coreboot.org/18502
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18491
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18487
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18479
Tested-by: build bot (Jenkins)
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow up to https://review.coreboot.org/#/c/18460/
Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.
On Kevin board, if we connect usb device with Samsung U2 cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.
This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.
BRANCH=gru
BUG=chrome-os-partner:62320
TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
Type-C port, check if the USB device can be detected.
Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e
Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/431015
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Inno Park <ih.yoo.park@samsung.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18462
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
As David commented the "Bob and other follow-ons match Gru, Kevin should
be the special case here", and update the calculations value for gru/bob
board.
From the actual tests, some regulator voltage than the actual set of less
than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the
{min, max} regulator voltage for Bob board. Make sure we get the accurate
voltage.
BUG=chrome-os-partner:61497
BRANCH=none
TEST=boot up Bob, measure the voltage for little cpu and C-logic.
Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4
Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/424523
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Original-Reviewed-by: Brian Norris <briannorris@chromium.org>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/430403
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18460
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17926
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18476
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
The children of Gru should share the benefits. In the real world, Bob can't
pass the eye diagram tests.
BUG=chrome-os-partner:62714
BRANCH=firmware-gru-8785.B
TEST=build coreboot
Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd
Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/440745
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/441468
Reviewed-on: https://review.coreboot.org/18461
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
These parameters are probably the result of copying from the Thinkpad
X60 code.
Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18374
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There was a 'typo' where the subsystem id was set instead of the codec
vendor id. This caused the lynxpoint HDA codecs init to fail to find
the proper codecid verbs so codecs were never initialized. That caused
the headphones jack to not work.
Change-Id: I975031643fc42937ecaea2300639b90632543f67
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18411
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
The M.2 SSD is on the SATA port 3, which also required the DTLE setting
to be set.
This fixes issues with the M.2 SSD not being detected/stable.
Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18409
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I538c28fb1bc412947ef9df947fa3f6a3312aeb4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18322
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
poppy board uses Maxim 98927 speaker codec and Realtek RT5663
for headset. Select the apropriate NHLT blobs to be packaged in CBFS.
Also, generate the required ACPI NHLT table for codec and the supported
topology in poppy.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=With the required driver support in kernel verify that
the Audio plays on on-board speakers and headset, recording
works from on-board mics and headset mics.
Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed
Signed-off-by: M Naveen <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18214
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18397
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the audio devices to Eve mainboard:
- Describe Maxim 98927 speaker amps and RT5663 headphone codec
in ACPI so they can be enumerated by the OS.
- Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH.
BUG=chrome-os-partner:61009
TEST=manual testing on Eve P1 with updated kernel to ensure that
both speakers and headset are functional. DMIC support is
is still being worked on and is not yet functional.
Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18398
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.
This model uses the same ENE KB9012 EC as the G505S.
Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works
Known issues:
- Patches needed for EC battery support
https://review.coreboot.org/#/c/18348/https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
and needs to be reverse engineered.
Not tested:
- msata/wwan (probably works)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Reviewed-on: https://review.coreboot.org/18351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18399
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.
Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18380
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18368
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18396
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18395
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.
Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)
Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
