This patch increases the SPI clock for the ROM to 24.75MHz on all rk3288
(veyron) boards. This increases flash read speeds (and thereby decreases
boot time) significantly, but we don't seem to get any more increases by
going even higher. We have also seen occasional read failures at higher
speeds in certain configurations, so this frequency seems to be the best
option.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted on Jerry with Servo attached.
Change-Id: I9bdb62eff169fe2be33558caafe9891668589372
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a1d07da4266f2922b076dfae8396c24c6a84252b
Original-Change-Id: If3fd96c8cb5648d12fc4ee56fb6b6d5f3a0bf720
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262645
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9889
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The hardware initialization is now split in basic
initialization (MIPS and system PLL, system clock,
SPIM, UART), and initialization of other hardware
blocks (USB, I2C, ETH). The second part uses board ID
information to select setup that is board specific
(currently only I2C interface is selected through
board ID).
BRANCH=none
BUG=chrome-os-partner:37593
TEST=tested on bring up board for both Urara and Concerto;
to simulate the use of Concerto (I2C3) DIP SW17 was
set to 0.
it works with default settings on Urara
Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e
Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/257401
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9888
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The code to calculate the RK3288 SPI controller's internal clock divisor
is wrong: it assumes that the divisor register was an "n-1" divisor when
it actually isn't (due to some misleading kernel code that was copied in
here). This means that all SPI clocks are currently running lower than
expected.
This patch fixes the calculation and changes all callers such that the
effective speeds stay the same.
BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted Jerry with and without the patch, dumping the divisor for
flash and EC clocks. Made sure it stays the same.
Change-Id: I2336e2b81c2384b5076175fcf32717a3ab2ba0c5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fd5b990f937019a9bee7bd693c91d6e2fca1adb
Original-Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/262269
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some platforms cannot access the 900h-9ffh region over the LPC bus, so
it's necessary to access memmap data over the ACPI cmd / data ports.
BUG=chrome-os-partner:38224
TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify
system boots cleanly and battery status is updated immediately on plug /
unplug.
BRANCH=None
Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d
Original-Reviewed-on: https://chromium-review.googlesource.com/262314
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/9886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=None
BUG=None
TEST=build coreboot, make sure there are fmov instructions
generated by the compiler, and boot to kernel
Change-Id: Ia99c710be77d5baec7a743a726257ef3ec782635
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f770a436a0692c8e57a8c80860a180330b71e82c
Original-Change-Id: Iab4ba979b483d19fe92b8a75d9b881a57985eed7
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/262242
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the serial number from VPD on ryu.
BRANCH=none
BUG=chrome-os-partner:37813
TEST=devicetree is populated with "compatible", "hardware",
and "serialno" properties
Change-Id: I1e84933a01a34028a062d31aad026f91c3bd29e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18cefb655651c9097ff7f2ef3cb735efbbe32370
Original-Change-Id: I14439c37df0fde7f2328c7caae1adf6a122e8f5f
Original-Signed-off-by: Stephen Barber <smbarber@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260646
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On embedded devices with limited input capabilities it is necessary to
clear the developer mode condition when entering recovery. The new
configuration option will enable such behavior using the new vboot2
flag.
CQ-DEPEND=CL:261630
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=with the rest of the patches applies observed desired behavior on
SP5
Change-Id: I99c3d1330bea9980a2af3b9fd99e29ab96f2cf07
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c0a6315d6b4ede8d43e736ee6c82f1023f4716d
Original-Change-Id: I8e4a521e574b53a670daf692f7b45dc21635f272
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261620
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9878
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It is better to explicitly disable the call to read the physical
switch setting than to leave it up to implementation. In fact no
implementation would be even required.
BRANCH=none
BUG=none
TEST=verified that storm works as expected
Change-Id: I4b39827dba34ec0124960d0634e45d4554252d9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c9fd014f1bfec6570b20ed8fed16d14d7e4e11b9
Original-Change-Id: I5d6d223f0c684e105a5e3d0b407e0fb181c7a7df
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/261588
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9876
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.
BUG=None
BRANCH=None
TEST=Built on ryu.
Change-Id: I29ea2371d034c0193949ebb10beb840e7215281a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5ab28b5d73c03adcdc0fd4e530b39a7a8989dae
Original-Change-Id: I8d5f648c995534294e3222e2dc2091a075dd6beb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260949
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9871
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These Kconfig options provided a level of configurability that is
almost never necessary, so they are being moved into ordinary
preprocessor defines in elog_internal.h. The new threshold to
trigger shrinking is relative to the number of additional
(maximum-size) events that can fit, and the new target
post-shrink size is a percentage of the total ELOG area size.
BUG=chromium:467820
TEST=Add loop at the end of elog_init() that fills the ELOG area
to just below full_threshold with dummy events. Observe
successful shrinkage when the next event is logged.
BRANCH=None
Change-Id: I414c4955a2d819d112ae4f0c7d3571576f732336
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce439361e3954a2bf5186292f96936329171cf56
Original-Change-Id: I926097f86262888dcdd47d73fba474bb2e19856a
Original-Signed-off-by: Sol Boucher <solb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260501
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/9869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old parameters are wrong. K4B8G1646Q: rank = 2, row = 15 is right.
BUG=None
TEST=Boot from veyron
BRANCH=None
Change-Id: I41848c158f3ea028035cc8c0d969a4a449390a54
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 601ba06c636ff0f0779e6ef9357b53060a1ec19b
Original-Change-Id: I5bc6798890b3ba0f5134d048ae6bbf2bfd696676
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/260483
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Paul Ma <magf@bitland.com.cn>
Reviewed-on: http://review.coreboot.org/9866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
in depthcharge we will use "backlight" gpio which in lb_gpio table
to control backlight, we use lcd_bl before, but it will not meet
the backlight power sequence, so we change it to bl_en.
BUG=chrome-os-partner:37348
TEST=Boot from speedy, and backlight work well
BRANCH=None
Change-Id: I19e488c7d3f1fe5cb91f8a93fae6b848f58b36b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb594ce612e1cedeabced4531fbd954f3698da98
Original-Change-Id: Ib0dac7c48bce7d0b28ec287b32d8c5bad575893f
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/259900
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It has become necessary to be able to "factory reset" certain devices
on firmware request.
The vboot package has been modified to provide the necessary API, this
patch introduces a configuration option and uses the API when
enabled.
CQ-DEPEND=CL:259857
BRANCH=storm
BUG=chrome-os-partner:37219
TEST=with all the patches applied, on storm, holding the recovery
button at startup for 10 seconds, causes 'crossystem
wipeout_request' to report '1'.
Change-Id: I5e57bc05af3753f451626021ba30c7726badb7b4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f70e03e9a8c55bf3c45b075ae4fecfd25da4f446
Original-Change-Id: I4c2192da4fabfdef34d527e5b80d137634eb6987
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/259843
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9862
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
DDR init blob version string can be found at a fixed location in
memory once the blob is loaded. Maximum size of the string is 48
bytes.
The RPM RW version is defined in a 32 bit version stored at yet
another fixed address once RPM RW has started.
BRANCH=storm
BUG=chrome-os-partner:30623
TEST=ran this command on the booted system:
localhost ~ # egrep '(DDR|RPM)' /sys/firmware/log
Loaded DDR init blob version 99ce41d@-AAABANAZA
DDR initialized
Starting RPM
Started RPM version 1.0.128
localhost ~ #
Change-Id: If3c3c8368845b978605ccfda7e09c21ae2e5ab9a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 328c9c57cf93110bc0fdd267134d72e386d70834
Original-Change-Id: If411f6f7bca53ea20390b7e851cb3d120681eade
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/256738
Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com>
Reviewed-on: http://review.coreboot.org/9860
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SP5 whirlwind is the earliest hardware version equipped with the LED
ring.
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=none
Change-Id: I4c90a75911350bafd8ccb8755b2491e9447f285b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dfee90457295668a2b60d5a1e913caf52557877
Original-Change-Id: I6bffdcc47fe9c72796e3bac44d211f907538ef0b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/258270
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9857
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Concerto board does not have the means of detecting the identity of
the device it is controlling. But it is very beneficial to be able to
use the same firmware image on Concerto boards running different
devices.
The suggested solution is to keep the device identity as a string in a
raw CBFS file called 'board_id'.
With this patch coreboot maintains a table of possible board name
strings and their matching board IDs.
BRANCH=none
BUG=chrome-os-partner:37593
TEST=verified that without the board id file addition the default
Board ID of zero is used. Adding the file as follows:
echo -n 'concerto' > /tmp/bid
cbfstool /build/urara/firmware/image.serial.bin add -f /tmp/bid \
-t raw -n 'board_id'
results in firmware reporting board ID setting of 1.
board_id: failed to locate CBFS file board_id
board_id: name urara, ID 0
Change-Id: I5a02192740dc94b1ea8090092cc325fe0ac42aa6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f41f9b07f155f0c719c36e0cd93081205624557e
Original-Change-Id: I8341782005b101be78f5c9a6b375c8f73179c1ad
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/257170
Reviewed-on: http://review.coreboot.org/9856
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
cygnus' serial driver wasn't part of the tree when the
big transformation was done, so follow up.
Change-Id: Ic1a53bea9bcaf1e568b50b9c2ad7782e65e36328
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9852
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This add hynix-2GB SDRAM(H5TC4G63AFR-PBA), whose timing is the same as
H5TC4G63CFR-PBA, to veyron boards.
BUG=None
BRANCH=veyron
TEST=build on mighty and boot on mighty board with ram-id reworked
Change-Id: I3ae5e65e60e18414cf4de6fbcc5bed736b1492de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b22029f9b05ebb9a775266a7e3aae38b50c1883a
Original-Change-Id: If17fb002f2816990e1706833b37ac6be345e540b
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256307
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/9848
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing DDR setup configures the burst length to be 8. However
the DDR controller can only be given sufficient data per clock to
satisfy a burst length of 4, hence the bursts are only half
populated. This results in a 50% drop of efficiency.
Fix this by configuring the burst size to 4.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
BRANCH=none
Change-Id: I761ba73a04688841ca39a370b7cb99b6e0b22964
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0e590ab8387dbbccef45dc84d1eeafee2abc9e2e
Original-Change-Id: I585385b65e330624ad70292349e50c6695eeeb6c
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The DDR On Die Termination was incorrectly configured at 75R,
where as the data sheet suggests for DDR2-800 it should be
set to 50R.
Correct this by adjusting the ODT setting in the EMR register.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
BRANCH=none
Change-Id: I2f0242c422b1cb3d1f64ce3dd17b62fef5e7e155
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac081ac59c0dc3d16a7b540cd379fb870b6cfe40
Original-Change-Id: If7951812033c4e88f4be3c143fb49526eddba142
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256304
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proper way to initialize DDR2 is for the PHY to
automatically establish precise timing configuration
through the training process. The alternative (used
initially for testing) is no longer needed.
This change determined the removal of some local
variables as they ended up being used in one location only.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly.
BRANCH=none
Change-Id: I31e9a8975d176a04061f9c84fe06cce850bb53b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e28f3ef9a22436bb0fa949df6f5a5c6a67002dfd
Original-Change-Id: Ifb9c1bb6e0b71af72340381bd2349850d1b4af2d
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256303
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some platforms may pass as a parameter the maskrom or vendor startup
code information when calling the bootblock.
Make sure the bootblock startup code saves this parameter for use by
coreboot. As we don't want to touch memory before caches are
initialized, save the passed in parameter in r10 for the duration of
cache initialization.
Added warning comments to help enforcing that cache initialization
code does not touch r10.
BRANCH=storm
BUG=chrome-os-partner:30623
TEST=with the rest of the patches applied see the QCA uber-sbl report
in the coreboot console output.
Change-Id: Ic6a09e8c3cf13ac4f2d12ee91c7ab41bc9aa95da
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e41584f769eb042604883275b0d0bdfbf5b0d358
Original-Change-Id: I517a79dc95040326f46f0b80ee4e74bdddde8bf4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255144
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com>
Reviewed-on: http://review.coreboot.org/9842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This describes the structure of the information passed through a
pointer by uber-sbl to be processed by the coreboot bootblock.
BRANCH=storm
BUG=chrome-os-partner:30623
TEST=with the rest of the patches applied observed uber-sbl
information added to the coreboot console log.
Change-Id: If04c4ee0ccfda3df45bd22eb576aaa5b51f1c4b5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed39e2bcd793fd490416b407f627b5a9a86b8f78
Original-Change-Id: I1dffbf4559853a818e81ca5fdeff013cf008dd6a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255143
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com>
Reviewed-on: http://review.coreboot.org/9841
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The I2C MFIO setup function now supports all interfaces.
Also, the API for the clock setup function changed to support
all interfaces.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; all I2C interfaces
were tested with the TPM and they all work properly.
BRANCH=none
Change-Id: I6dfd1c4647335878402cabb2ae512d6e3737a433
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8a7ffb54e3f5092c9844b9b502949d3cfc053d1
Original-Change-Id: Ibd67c07acf3d1d9c594faa8ced5ab56d9abb2e40
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256362
Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; all I2C interfaces
were tested with the TPM and they all work properly.
BRANCH=none
Change-Id: I02202585140beb818212c02800f6b7e4966a922a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d
Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/256361
Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch removes quite a bit of code duplication between cpu_to_le32()
and clrsetbits_le32() style macros on the different architectures. This
also syncs those macros back up to the new write32(a, v) style IO
accessor macros that are now used on ARM and ARM64.
CQ-DEPEND=CL:254862
BRANCH=none
BUG=chromium:444723
TEST=Compiled Cosmos, Daisy, Blaze, Falco, Pinky, Pit, Rambi, Ryu,
Storm and Urara. Booted on Jerry. Tried to compare binary images...
unfortunately something about the new macro notation makes the compiler
evaluate it more efficiently (not recalculating the address between the
read and the write), so this was of limited value.
Change-Id: If8ab62912c952d68a67a0f71e82b038732cd1317
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fd43bf446581bfb84bec4f2ebb56b5de95971c3b
Original-Change-Id: I7d301b5bb5ac0db7f5ff39e3adc2b28a1f402a72
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254866
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is a manual cleanup of all the rubble left by coccinelle
waltzing through our code base. It's generally not very good with line
breaks and sometimes even eats comments, so this patch is my best
attempt at putting it all back together.
Also finally remove those hated writel()-style macros from the headers.
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d
Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254865
Reviewed-on: http://review.coreboot.org/9837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is a raw application of the following spatch to src/:
@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)
BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)
Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch changes the argument order for the (now temporarily unused)
write32() accessor macro (and equivalents for other lengths) from
(value, address) to (address, value) in order to conform with the
equivalent on x86. Also removes one remaining use of write32() on ARM
that slipped through since coccinelle doesn't inspect header files.
BRANCH=none
BUG=chromium:444723
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.
Change-Id: Id5739b144f6a5cfd40958ea68510dcf0b89fbfa9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f02cae8b04f2042530bafc91346d11bb666aa42d
Original-Change-Id: Ia91c2c19d8444e853a2fc12590a52c2b6447a1b9
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:
@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)
This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.
BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.
Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adding a new field to a CBMEM structure does not work if there are
systems with older RO that do not have this new field as it means
romstage did not prepare the field and ramstage is using it
uninitialized.
To deal with this instead of adding a new field split the existing
s3_resume variable into bytes, using the first byte for the existing
s3_resume variable (which is always just 0 or 1) and the second byte
for the new varible, which will always be 0 for the old RO and can
be set by new RO.
BUG=chrome-os-partner:37108
BRANCH=samus
TEST=manual testing on samus:
1) ensure that if vboot requests reboot after TPM setup that it still
works and the reboot happens after reference code execution.
2) ensure that if RO is older without this change that it does not
cause a continuous reboot if newer ramstage is added
3) test that suspend resume still works as expected
Reviewed-on: https://chromium-review.googlesource.com/253550
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 1ccb7ee5fc6980ca0f26fa52b385d2cc52f396c9)
Change-Id: I6e206b4a3b33b8a31d102d64bd37d34657cf49ac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe85678ee788ff939bc8c084829a1b04232c4c6c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: If69d0ff9cc3bf596eee8c3a8d6e04951820a26fe
Original-Reviewed-on: https://chromium-review.googlesource.com/256114
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This applies the same hack to Danger and Brain as on Rialto which
allows us to remove the EC-related sections from their respective
flashmaps.
BUG=none
BRANCH=veyron
CQ-DEPEND=CL:255669
TEST=built and booted on Brain w/ depthcharge and mosys changes,
was able to read vbnv data from userspace
Change-Id: I95715d59a21cd081ac4a3a2216576ede5620f1a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4de4273be9ac80ca77a34bc076d1f265fbb94e9f
Original-Change-Id: I6c2041e8c17ab157599255a505aaef5e2447a241
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255780
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
if DCDC_UV_ACT_REG setted, when the buck voltage drop to 85%,
rk808 will reset this buck, but now when the current consumption large,
rk808 may miscarriage of justice this status, so we must disable this function
BUG=chrome-os-partner:34834
TEST=Boot from jerry, and do RUNIN test sucess
BRANCH=None
Change-Id: I08cef73b88d6c2722b389c632c7db29605f4545d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 858c8abc11a824fc3d991a39a49710243f4b1473
Original-Change-Id: I46ebe332c576eebd3386b5042b146a8b57a5c194
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/254496
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We found that we should better keep ODT off for LPDDR3 on our boards.
BRANCH=veyron
BUG=chrome-os-partner:37346
TEST=Boot veyron_speedy normal
Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599
Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255381
Reviewed-on: http://review.coreboot.org/9830
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds all SDRAM configurations currently in use for any Veyron
board to all boards. In the future we might decide that we want to reuse
known good memory from one board on another, and having all of these in
there already might help us avoid a firmware rev. We can still
differentiate them later if the need ever arises.
Not touching Rialto since it already decided to go its own way and
replace an existing RAM code with it's own 1GB configuration. Also
adjusting the names of the recently added DDR3 4GB configs to fit the
existing scheme.
Includes changes from "veyron: The ODT function is disabled LPDDR3".
BRANCH=veyron
BUG=None
TEST=Compiled all Veyron boards, booted on Jerry.
Change-Id: I817efd4b467a5a9587475a82df207048173e7bd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 36d3fe138b154a16700e3c7adbb33834ff1c5284
Original-Change-Id: I4d037967dcb5cbd6b2b82f347f6b19541559b61a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255665
Reviewed-on: http://review.coreboot.org/9829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The wrong offsets were being used for the GRF_SOC_CON2 register. This also
configures odt based on the value of odt in the sdram_params for lpddr systems.
BUG=chrome-os-partner:37346
TEST=boot veyron_speedy and veyron_jerry
BRANCH=None
Change-Id: I13ec3d0df162fe73fabf8af40dd5472e15d6f6af
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 403ab13de17290dc3766bd6f1a03b6effbe58b41
Original-Change-Id: Ic0c18cc7ccf861ef8749e6c950fab9a2802e5f26
Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255584
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the absolute offset value to the CBFS log, to make it easier to
understand which particular CBFS section the file is loaded from.
BRANCH=storm
BUG=none
TEST=rebooted a Whirlwind device, observed an empty line before the
ramstage section of the log and absolute offsets reported by
CBFS.
Change-Id: Ifcb79ab386629446b98625a5416dfa5850a105f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ecc4d1df7c51a263230c45ecac5981d53bdd44b1
Original-Change-Id: I5cc727127374d6e55b8ff6f45b250ef97125a8ec
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/255120
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9827
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
add the K4B8G1646Q-4GB and H5TC8G63XXX-4GB ddr3 inf file,
and use ram_id 1110 correspond to K4B8G1646Q-4GB ddr3
use ram_id 1111 correspond to H5TC8G63XXX-4GB ddr3
BUG=None
TEST=Boot veyron_jerry normal
BRANCH=None
Change-Id: I3398516a9f2c2e44c9f5d08d0a3ab6e76b5c6f5f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b8dfc455bb93c2daf567e3b6e39c0a715e44311c
Original-Change-Id: I90250cb84eb140f93c4fc655fb3b90584dd515c0
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/255010
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9826
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix build bug that is referencing vboot_data from
vendorcode/google/chromeos/gnvs.c when CONFIG_HAVE_ACPI_TABLES is not
set.
BRANCH=none
BUG=None
TEST=Build and run on Glados
1. Checkout updated patches for config, skylake and glados through
FspNotify1
2. Verify that mainboard/intel/glados/Kconfig does not select
HAVE_ACPI_TABLES
3. emerge-glados coreboot
4. Test passes if build completes successfully
Change-Id: Ida5ab8b8dafe30b11dc80dab935e3223d4c760d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1908079360aa065a36956d487eb93142e9c012a1
Original-Change-Id: Icac3845f7e2d1ddffa5f787a640033fba286c13e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/254360
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9825
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I2c transfer may consist of multiple segments (for instance write
segment to set the register address and then a read segment to read
the register value). Transfer should be stopped as soon as a segment
processing error has been reported.
BRANCH=master
BUG=chrome-os-partner:35328
TEST=transfer shall not process the read segment when the write segment fails
Change-Id: I85b7b59b376ce33ba3f6d2526be86e9f6585d97b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50cd4d40851b3cea99183c549c47b4486a3deb4a
Original-Change-Id: Id65f995d860dd670b289fbdd9eb0ca19a50d7007
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254494
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The qup_i2c_write_fifo() made to query QUP_I2C_MASTER_STATUS after QUP
transitions into PAUSE state to ensure that it captures the correct status.
Handled more error bits.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:35328
TEST=Booted up storm P0.2, verified that the TPM on GSBI1 works.
Verified that SUCCESS is not reported when the write FIFO has failed.
Change-Id: Ia91638d37b3fa8449630aa2cf932114363b2db78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75e0d59d2e6ba03182003f22944dbf99ce3eb412
Original-Change-Id: Ic4e8e85686499ce71ad3258b52e687ceff36a1f8
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254495
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9823
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Cache operations are simplified by removing assembly
implementation and replacing it with simpler C code.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; caches are properly
invalidated;
BRANCH=none
Change-Id: I0f092660549c368e98c208ae0c991fe6f5a428d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bf99849e75813cba865b15af9e110687816e61e4
Original-Change-Id: I965e7929718424f92f3556369d36a18ef67aa0d0
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250792
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9820
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When using single-channel ddr, DMC channel 1 need to reset dll,
otherwise it will lead to pmdomain idle request fails.
BUG=chrome-os-partner:35654
BRANCH=veyron
TEST=boot rialto
Change-Id: Id6b673187c688d238e9a391b3d98720c783e3af4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 927e8426104f8869e139c3f60a04cd49bf726e61
Original-Change-Id: I8be1567040ddb5f2a2b0d06568e517d794ead87a
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/250060
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9819
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Using identity_map(), map the DRAM/SRAM regions to themselves (which
happens to be using KUSEG on urara).
The bootblock (which still runs in KSEG0) sets up the identity mapping
in bootblock_mmu_init() so that ROM/RAM stages can be loaded into the
KUSEG address range.
The stack and pre-RAM CBMEM console also remain in KSEG0 since we
don't really care about their physical addresses.
Also splitting CBFS cache to pre and post RAM, to allow for larger
rambase images.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=With the rest of coreboot and depthcharge patches applied:
- booted urara into the kernel login prompt
- from depthcharge CLI tried accessing memory below 0x100000 -
observed the exception.
Change-Id: If78f1c5c54d3587fe83e25c79698b2e9e41d3309
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9668b440b35805e8ce442be62f67053cedcb205e
Original-Change-Id: I187d02fa2ace08b9fb7a333c928e92c54465abc2
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246694
Reviewed-on: http://review.coreboot.org/9816
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Introduce identity_map() function. It takes a memory range and
identity maps it entirely in the TLB table, if possible. As a result
the virtual and physical address ranges are the same.
The function attempts to use as large of a page size as possible for
each region in order to conserve TLB entries.
BUG=chrome-os-partner:36258
BRANCH=none
TEST=Build and boot on Pistachio with the rest of the patches applied.
Change-Id: I4d781b04699e069a71c49a0c6ca15c7a6b42a468
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 234d32edfd201019b7a723316a79c932c62ce87e
Original-Change-Id: If3e2392b19555cb6dbae8b5559c1b1e53a313637
Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/246693
Reviewed-on: http://review.coreboot.org/9815
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Found that any non-USB3.0 devices connected to type-C ports
(displayPort dongles) cause XHCI port to see connection which in turn
leads us to enter USB compliance mode.
That in turn causes the port to wake the system for a yet-to-be
determined reason. Clearing the PORTSC status bits (actually just
CSC) seems to remedy the wake.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:35320
TEST=manual,
1. Plug hoho into type-C port on samus and remove
2. powerd_dbus_suspend
Device stays asleep.
Change-Id: Id3a291579ffca0152a7ef32e37ecae80ca08a82b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0be5cba4916681dceb0372e76d9643e6c7175db5
Original-Change-Id: I1396b9f8013dbbb31286c1d8958af592b3da7475
Original-Reviewed-on: https://chromium-review.googlesource.com/247410
Original-Commit-Queue: Todd Broch <tbroch@chromium.org>
Original-Tested-by: Todd Broch <tbroch@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9814
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I97920e7eb64c05034184f9a4e1c8f2dfa44d3fdd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9813
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the board is configured with a pre-graphics delay it should
be skipped in the resume path.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=measure resume time in dev mode to be same as normal mode
Change-Id: I5a4ad5bba9e5316c89f7935d8811759b041429d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b44a7167532410fc44ca9df1c91c91aaf541ae49
Original-Change-Id: Ic9f2cda71d8a567f57e863409f0f3fb98ab68bcf
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/245116
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9812
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch fixes the use of the recovery button, and the value is stored
in a SATA controller scratch register.
BUG=chrome-os-partner:35241
BRANCH=none
TEST=Use recovery button and run firmware_RecoveryButton
Change-Id: Ia06f147c7e44d6c4eea2c2e4f502c233c956ee9b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34c7ee922a9602b3448a72cd669fd68feeed1bba
Original-Change-Id: I1667c7f188b0f87c4bc7caa82f9c977b2b4c0611
Original-Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241772
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9811
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is a no-op change just sorting the CBMEM entries' definitions for
easy look up and comparison.
BRANCH=storm
BUG=none
TEST=Booted a storm device, observed the expected CBMEM entries
present in the console output.
Change-Id: I26365285f20ecb256918277b60e178cd61dc8213
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f140fd8d85ded30d1b89f5d4c64f8b9f31d6b27b
Original-Change-Id: Ibcd4f184ef1bade10ad677384f61243da7e3c713
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/225259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9810
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This was added in upstream but not in Chromium OS where
pistachio support was developed.
Change-Id: I54f883776f19aa7bd357841731166e92d03145d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9808
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
ChromeOS/vboot devices expect the TPM PCRs 0 and 1 to be extended with
digests that attest the chosen boot mode (developer/recovery) and the
HWID in a secure way. This patch uses the newly added vboot2 support
functions to fetch these digests and store them in the TPM.
CQ-DEPEND=CL:244542
BRANCH=veyron
BUG=chromium:451609
TEST=Booted Jerry. Confirmed that PCR0 contains the same value as on my
vboot1 Blaze and Falco (and PCR1 contains some non-zero hash).
Original-Change-Id: I7037b8198c09fccee5440c4c85f0821166784cec
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/245119
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 8b44e13098cb7493091f2ce6c4ab423f2cbf0177)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I549de8c07353683633fbf73e4ee62ba0ed72ff89
Reviewed-on: http://review.coreboot.org/9706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ramstage is loaded from romstage, so the LZMA scratchpad buffer used
to decompress it is part of the romstage BSS in SRAM. On RK3288, SRAM
cannot be cached which makes the decompression so slow that it's faster
to just load an uncompressed image from SPI. Disable ramstage
compression on this SoC to account for that.
[pg: implementation avoids restructuring all of Kconfig]
BRANCH=None
BUG=None
TEST=Built for Pinky and Falco, confirmed that the former didn't have
COMPRESS_RAMSTAGE in its .config and the latter still did. Measured a
speed-up of about 35ms on Pinky. (For some weird reason, the
decompression of the payload also takes way longer than on other
platforms, although not as long as the ramstage. I have no explanation
for that and can't really think of a good way to figure it out... maybe
the Cortex-A12 is just terrible at some operation that LZMA uses a lot?)
Change-Id: I9f67f7537696ec09496483b16b59a8b73f4cb11b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/234192
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9792
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We recently restructured where the CBFS header is stored
and how it is looked up, with less magic. The RISC-V port
didn't get the memo, so have it follow the pack now.
Change-Id: Ic27e3e7f9acd55027e357f2c4beddf960ea02c4d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/9795
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
When CONFIG_MULTIPLE_CBFS_INSTANCES is enabled, the image is expected
to have CBFS instances in rw-a and rw-b sections of the bootrom.
This patch adds code which makes sure that CBFS header points at the
proper bootrpom section as determined by vboot, and the RW stages load
from that section.
BRANCH=storm
BUG=chrome-os-partner:34161, chromium:445938
TEST=with the rest of the patches in, STORM boots all the way into
Linux login prompt.
Original-Change-Id: I187e3d3e65d548c672fdf3b42419544d3bd11ea1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/237662
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 71ad0bb41b183374a84a5b9fb92c3afd813ceace)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia05cb713981c44da8cb379b72dfbe17fe1f6c5ff
Reviewed-on: http://review.coreboot.org/9704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch aligns our verstage code to the new API addition in vboot2.
The hardware crypto functions are stubbed out by default and just
pretend that all algorithms are unsupported, causing vboot to fall back
to the normal software hashing code. These weak symbols can be
overridden by individual platform code to provide actual hardware
crypto engine support.
CQ-DEPEND=CL:236453
BRANCH=None
BUG=chrome-os-partner:32987
TEST=Booted Pinky, confirmed vboot falls back to software crypto.
Original-Change-Id: Idf6a38febd163aa2bff6e9a0e207213f01ca8324
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236435
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 9b5ee7f575f1aa3b0eb6ef78947ca93a4818f57b)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I6f0e19255a9bc5c5cd1767db76f1e47897ef0798
Reviewed-on: http://review.coreboot.org/9703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this allows each board to decide what to do after firmware verification is
done. some board needs to return back to the previous stage and let the
previous stage kick off the verified stage.
this also makes it more visible what is going to happen in the verstage since
stage_exit now resides in main().
BUG=none
BRANCH=tot
TEST=booted cosmos dev board. booted blaze in normal and recovery mode.
built for all current boards.
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I3cb466cedf2a9c2b0d48fc4b0f73f76d0714c0c7
Original-Reviewed-on: https://chromium-review.googlesource.com/232517
(cherry picked from commit 495704f36aa54ba12231d396376f01289d083f58)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ic20dfd3fa93849befc2b37012a5e0907fe83e8e2
Reviewed-on: http://review.coreboot.org/9702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ipq806x UART is based on the same universal serial port which can
be also configured as i2c or SPI. Configuring it is not a trivial
task, so in case the kernel wants to use earlyprintk() the port needs
to be configured by the firmware.
Invoking uart_init() when the console is not enabled causes include
file collisions, which would require changes to more than 100 files.
Leaving this to another day, rearranging the ipq806x driver to be able
to invoke UART initialization function even when serial console is not
configured.
Also add a check to avoid initialization if UART has been already
set up.
BRANCH=storm
BUG=chrome-os-partner:35364
TEST=verified that storm console is still fully operational when
enabled, and that the kernel boots fine to the serial console
login prompt even if the firmware console is disabled.
Change-Id: Ibbbab875449f2ac2f0d6c504c18faf0da8251ffa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c512d6c1d0c0868137d1213ea84cd4bca58872db
Original-Change-Id: I421acba3edf398d960b5058f15d1abb80ebc7660
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240516
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9794
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Originally ported QCA UART driver used hardware accessor macros where
both address and data were represented by 32 bit integers. Coreboot
uses macros where addresses are represented by pointers, this make the
code more robust, as accidental swap between address and data does not
go unnoticed.
This patch converts ipq806x UART driver to use coreboot accessors. It
relies on gcc void pointer arithmetic considering objects pointed at
by void pointers to be one byte in size. Also replacing spaces with
hard tabs where appropriate.
BRANCH=storm
BUG=chrome-os-partner:34790
TEST=new code still boots fine on Storm with console output present.
Change-Id: I3ded9c338ff241bb1d839994f7296756aad8772d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 10616351704ebbcfcf25793ae974b256bc5bd6b0
Original-Change-Id: Ie15e09f9f3ea10a8566b6845219c2e09fed39218
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240514
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Reviewed-on: http://review.coreboot.org/9793
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To avoid entries with Type-C alternate mode devices disable
compliance mode entry. This needs to be set on both boot
and resume.
BUG=chrome-os-partner:35320
BRANCH=samus
TEST=manual:
1) boot on samus with USB keyboard plugged in -> controller in D0 at boot
2) iotools mmio_read32 0xe12080ec == 0x18010c01
3) suspend and resume
4) iotools mmio_read32 0xe12080ec == 0x18010c01
5) remove USB keyboard -> controller in D3
6) iotools mmio_read32 0xe12080ec == 0xffffffff
7) plug in USB keyboard -> controller in D0
8) iotools mmio_read32 0xe12080ec == 0x18010c01
9) boot with no external USB devices -> controller in D3 at boot
10) iotools mmio_read32 0xe12080ec == 0xffffffff
11) plug in USB keyboard -> controller in D0
12) iotools mmio_read32 0xe12080ec == 0x18010c01
Change-Id: I4d566112b3c188bafdf9a4bbd92944c89500e3e8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db8c8ab8ff25f6a39cd50dcc91b5ba9fd7d05059
Original-Change-Id: I8b68ba75e254a7e236c869f4470207eb5290053d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251361
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9782
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move reset support into the Intel common branch. Prevent breaking of
existing platforms by using a Kconfig value to select use of the common
reset code.
BRANCH=none
BUG=None
TEST=Build and run on Glados
Change-Id: I5ba86ef585dde3ef4ecdcc198ab615b5c056d985
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 85d8a6d9628a66cc8d73176d460cd6c5bf6bd6b2
Original-Change-Id: I5048ccf3eb593d59301ad8e808c4e281b9a0aa98
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/248301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/9505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for applying write protection to the MRC cache
region in SPI flash.
This is only enabled if there is write protect GPIO that is
set, and the flash status register reports that the flash
chip is currently write protected.
Then it will call out to a SOC specific function that will
enable write protection on the RW_MRC_CACHE region of flash.
The implementation is not quite as clean as I would like because
there is not a common flash protect interface across SOCs so
instead it relies on a new Kconfig variable to be set that will
indicate a SOC implements the function to protect a region of
SPI flash.
BUG=chrome-os-partner:28234
BRANCH=broadwell
TEST=build and boot on samus
1) with either WPSW=0 or SRP0=0 the PRR is not applied
2) with both WPSW=1 and SRP0=1 the PRR is applied
Change-Id: If5907b7ddf3f966c546ae32dc99aa815beb27587
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a3e0e71dfd7339aab171a26b67aec465a3f332d6
Original-Change-Id: I94e54e4723b1dcdacbb6a05f047d0c0ebc7d8711
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241170
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Serial port on ITE 8772 SuperIO must be initialized before
console_init is called. So the pre console init callback
is added to let mainboard code do proper initialization.
Change-Id: Iaa3e4b9c6e7ce77a7b9a6b9ecedd8ea54f3141dc
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 71ee2fd470e19fa4854f895678445b05c17761c1
Original-Change-Id: I594e6e4a72f65744deca5cad666eb3b227adeb24
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/227933
Original-Reviewed-by: Kenji Chen <kenji.chen@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change switches all mainboard vendors and mainboards
to be autoincluded by Kconfig, rather than having to be mentioned
explicitly.
This means, vendor and mainboard directories are becoming more
"drop in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.
The long term plan is to enable out of tree mainboards / components
to be built with a given coreboot version (given that the API did
not change)
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib68ce1478a2e12562aeac6297128a21eb174d58a
Reviewed-on: http://review.coreboot.org/9295
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
this is not only for speed but also preventing the cpu from crashing.
the cpu is not happy when cache is cleaned without mmu turned on.
BUG=chrome-os-partner:36691
BRANCH=broadcom-firmware
TEST=boot purin to romstage.
Change-Id: I2445dcc2729798c4fc56fa191cbc8471ef708d08
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9e35c925b75213e1d35bf191f22c39aaf1726eeb
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Icaf8c506df258edb99413949e6e3089a2b1a91af
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199388
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/251306
Reviewed-on: http://review.coreboot.org/9768
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
we also pick no RETURN_FROM_VERSTAGE.
BUG=none
BRANCH=broadcom-firmware
TEST=booted b0 board
Change-Id: Iddd95f233a614187ae6b26f351a289c23f25742f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 243598925333982b40297adad878c461990d7d70
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I6ab96628cecb84e061777cc85d6d572823f6d63c
Original-Reviewed-on: https://chromium-review.googlesource.com/251303
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9767
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This allows us to define the serial console UART on a per-board
basis.
BUG=chrome-os-partner:31438
BRANCH=none
TEST=built and booted on urara w/ follow-up patches
Change-Id: Idbb0d39bf8855df4312f7499c60b8b92826fdd07
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed4cfdd5ed6ccbf87a50f56d3e07f2f1a9d49464
Original-Change-Id: I3faeb92f026062cded390603a610e5b8f7c9bc12
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/243211
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/9777
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch fixes a bug that caused non-x86 boards to use the poor man's
assert() version with a lot more instructions per invocation and
hexadecimal line numbers in __PRE_RAM__ environments. This was really
just an oversight in the ARM port... even x86 uses a proper printk() in
most cases (those with CAR) and there's no reason not to do so on the
generally even more flexible SRAM-based architectures.
Additionally, it adds a new Kconfig option to make failed assertions and
BUG() calls halt again. This seems to have been the original intention,
but was commented out once out of fear that this might prevent
production systems from booting. It is still a useful debugging feature
though (since otherwise assertions can easily just scroll past and get
overlooked), so the user should be able to decide the this based on his
needs.
(Also changed error messages for both to include the word "ERROR", since
grepping for that is the most sophisticated way we currently have to
detect firmware problems. Some automated Chromium OS suspend tests check
for that.)
BRANCH=veyron
BUG=None
TEST=Booted Jerry. Compared binary sizes before and after, new version's
bootblock is some ~600 bytes smaller.
Change-Id: I894da18d77e12bf104e443322e2d58e60564e4b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a5343124719c18a1c969477e3d18bda13c0bf26
Original-Change-Id: I0268cfd67d8c894406b18bb3759a577944bcffb1
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/250661
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9775
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
stmicro flash chips use 2 bytes as a device id: upper byte for memory
type and lower byte for capacity. with this change, we will use all 2
bytes to identify a chip.
BUG=none
BRANCH=broadcom-firmware
TEST=booted purin and verified n25q256a was identified.
Change-Id: I8f382eddc4fa70d3deceb4f9d2e82026a7025629
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12f70a1d4b7e1142afec9ce097c4a21b6225f66e
Original-Change-Id: Id3378a77318fabb74ddb30f1a9549010636872ba
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/199387
Original-Reviewed-by: Corneliu Doban <cdoban@broadcom.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/251305
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Compile in support for the STM flash devices.
BRANCH=storm
BUG=chrome-os-partner:33489
TEST=verified that both spansion and stm flash devices boot as
expected.
Change-Id: Ib616b2b52d29b20b4447c92115181a92c524ac39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 34c0147b45551e9161e3f0e342a753907f27f9ae
Original-Change-Id: I922afb91cc3ac5bf459d9746817d7677986b93cd
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248993
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
That function requirement was added upstream but not in Chromium, so
add an implementation.
Change-Id: Ie384b315adb205586defa730b843c7c8e96f77fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9776
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Bootblock does not allow using malloc, use statically allocated chip
structures instead.
BRANCH=storm
BUG=chrome-os-partner:33489
TEST=both drivers compile when configured in, also booted whirlwind
with an STM compatible SPI NOR flash.
Change-Id: I154c33ce5fc278d594205d8b8e62a56edb4e177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eedbb959a595e0898e7a1dd551fc7c517a02f370
Original-Change-Id: I29b37107ac1d58a293f531f59ee76b3d8c4b3e7c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is necessary to make sure that bootblock uses the default CBFS
header (as it ought to) when multiple CBFS images support is enabled.
BRANCH=storm
BUG=chrome-os-partner:34161, chromium:445938
TEST=with the rest of the patches applied storm boots all the way inot
the Linux prompt
Change-Id: I5e029d95c5cb085794c7bf5f44513b2144661e38
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 75b2c2ef6c8287db7c3e5879cacfd5dcba4391ac
Original-Change-Id: I5c352921b4c9b6a3294f4658d174e0842d2ee365
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/237661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is the intialization code specific to the Winbond
W972GG6JB-25 part using Synopsys DDR uMCTL and DDR Phy.
This is DDR2 initialization code only (currently present
on the bring up board). DDR3 initialization code will follow
for boards having DDR3 memory.
The programming procedure that is executed at power up to bring
up the uMCTL, PHY and memories into a state where reads and
writes to the memory can be performed is the following:
1. uPCTL (Universal DDR protocol controller) initialization
The timining registers TOGCNT1U, TINIT, TOGCNT100N and TRSTH
needed for driving the memory power-up sequence are programmed
as a function of the internal timers clock frequency.
Organization (memory chip specific) values are set
(column/bank/row address width and number of ranks), together
with other static values (latency, timing, power up configuration).
All these values are static, provided by the datasheet,
being determined by the memory type, size and frequency.
2. PHY initialization
The PHY is programmed with datasheet provided values,
specifying the initialization values for it to send to the
external memory (timing parameters).
Also, delay lines (DLL) and strength of drive pads are
calibrated (based on external conditions: temperature,
voltage, noise) and locked. After that, the PHY goes
through a trainig process (also dependent on the
current conditions at boot time) to establish precise
timing configuration between the DDR clock and DQS (data strobe)
and between DQS and DQ (data).
3. Memory power up
4. Switch from configuration state to access state.
BUG=chrome-os-partner:31438, chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
DDR2 is also tested during chip sort.
Corner cases (performace of DDR in different conditions)
will be tested after the chip reaches a stable state.
BRANCH=none
Change-Id: I0093dc175d064aad03052d5281679b008c1bf012
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0bacea0fd5bd3b12008b47e80de8398f447785
Original-Change-Id: I8437db6c84d77c4c51a3ee2b09cd3d14913c0d16
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241424
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9769
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
broadcom cygnus hangs if we clean caches by dcache_clean_invalidate_all
at bootblock entry point. this change makes startup code call
dcache_invalidate_all instead.
other boards theoretically should not be affected as long as maskrom
does not hand off execution to bootblock with dirty cache.
BUG=chrome-os-partner:36648,chrome-os-partner:36691
BRANCH=broadcom-firmware
TEST=boot cygnus b0 board, messages were printed on console:
coreboot-688aae9-dirty bootblock Mon Feb 9 13:21:02 PST 2015
starting...
Exception handlers installed.
Change-Id: I05777ca525c97bb3d7cbb5ea7e872a602dcd5a19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 59de5328df9d0502a3b3f7c624d3e86e038de50e
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I9b8850846b941e7e62712e90cc28ad14a68da393
Original-Reviewed-on: https://chromium-review.googlesource.com/251304
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Storm devices' recovery button is overloaded. Pressing it when the
system is running is supposed to reset the device. To trigger recovery
mode the button must be held pressed for at least 5 seconds after
reset.
Currently interpreting the recovery button state is the responsibility
of the board (vboot gets a consolidated state, which is a combination
of several conditions), so the simplest way to implement this feature
is to make the board follow the recovery button state.
In case the button is not pressed when it is first sampled, its state
is saved immediately and no recovery request is reported. In case the
button is pressed when it is first sampled, the board code keeps
polling it up to 5 seconds and acts accordingly.
BRANCH=storm
BUG=chrome-os-partner:36059
TEST=tried starting a whirlwind with recovery button pressed for
various durations, it entered recovery mode when the button was
pressed longer than 5 seconds.
Change-Id: Icb3250be7c2a76089c070acd68cb521d1399e245
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45e7265bc760944f93dd98903d39d2b30aa96365
Original-Change-Id: Iab3609ebce3a74e3d0270775b83f3cf03a8837ca
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/251711
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/9761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GSBI driver is extended to be able to program the CTRL reg for any given
GSBI block. The NS and MD registers programming is made more readable by
programming the M, N, D and other bits of the registers individually.
Defined configure structs for each QUP block to be able to track the init
status for each qup.
Configured GPIO8 and GPIO9 for I2C fuction.
BRANCH=chromeos-2013.04
BUG=chrome-os-partner:36722
TEST=Booted up storm P0.2, verified that the TPM on GSBI1 still works.
Change-Id: I17906beedef5c80267cf114892080b121902210a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07bc79211770decc1070c3a88874a4e452b8f5bc
Original-Change-Id: I841d0d419f7339f5e5cb3385da98786eb18252ad
Original-Signed-off-by: Sourabh Banerjee <sbanerje@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/250763
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Trybot-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a clock control driver to initialize the clock tree inside the
low-power audio subsystem. Depthcharge builds up on this to enable
audio function on storm.
The clock is hardcoded for 48KHz frame rate, two 16 bit channels.
BRANCH=storm
BUG=chrome-os-partner:35247
TEST=with depthcharge patches applied and Using depthcharge CLI audio
test program verified that the target generates sensible sounds
audio 100 100
audio 1000 5000
Change-Id: I56513fc782657ade99b6e43b2d5d3141d27ecc4e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0d4f408408aa38b2f0ee19b83ed490de39074760
Original-Change-Id: If8ffc326698fcea17e05d536930d927ca553481f
Original-Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/248830
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: http://review.coreboot.org/9758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds the necessary platform glue to allow the use of
software-driven I2C bit banging on the RK3288. This is just a debugging
feature that can be used to reproduce certain I2C failure cases.
Also fix Makefile verstage linking for the feature and add some new
rk3288 IOMUX macros as needed.
BRANCH=None
BUG=None
TEST=Added "CONFIG_SOFTWARE_I2C=y" to configs/config.veyron_jerry,
wrapped Jerry's bootblock and verstage in software_i2c_attach/detach()
calls, confirmed that both PMIC and TPM could be driven correctly with
software I2C driver. Tried out different combinations of
software_i2c_wedge_ack() and software_i2c_wedge_read() on the PMIC and
observed transfer results with the hardware controller after reboot...
the worst that would happen is that the first register read-modify-write
(DCDC_ILMAX) would fail to read, but all later transfers would be fine.
Since that register is written twice (due to current BUCK1 ramp
implementation) and is not terribily important anyway, I think we don't
need to worry about wedging problems.
Change-Id: Iba801ee61d30fb1fd3aef8300612c67fa50c441b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24dfca9bab38a20c40ef0c2dd4c775b8d8f47487
Original-Change-Id: I96777300a57c85471bad20e23a455551e9970222
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/247890
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9757
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This brings brain, danger, and rialto up to parity with other
veyron platforms as far as eventlog functionality is concerned.
BUG=chrome-os-partner:34436
BRANCH=none
TEST="mosys eventlog list" shows events (tested on Brain)
Change-Id: I186c5d18e5351c0eaf08ffecfd87506283c44b19
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1764bc53147718031231a6d125a4a1a96c4c6a8f
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ief09299965f6f21bc5a40cef31cde61344025c2a
Original-Reviewed-on: https://chromium-review.googlesource.com/239979
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9755
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This applies a previous patch ("chromeos: Provide common watchdog
reboot support") to some veyron platforms that were missing it.
BUG=none
BRANCH=none
TEST=built and booted on Brain
Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37
Original-Reviewed-on: https://chromium-review.googlesource.com/245633
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
we will use dvs to adjust the voltage in kernel, if device reset
by watchdog in kernel, the dvs gpio may not reset, and we use the
i2c to adjust rk808 voltage in coreboot, so it may failure. so we
move the reboot_from_watchdog() before the rk808 setting.
BUG=None
TEST=Boot from speedy
BRANCH=None
Change-Id: I809c63153d49680d9c84462aafd7bae09106fa6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 76efb4b0196eecc84664a4c5dce2221152a39c0a
Original-Change-Id: I92b5c6413bbffe30566178de89df1f9683790982
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/244289
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Many ChromeOS devices use a GPIO to reset the system, in order to
guarantee that the TPM cannot be reset without also resetting the CPU.
Often chipset/SoC hardware watchdogs trigger some kind of built-in
CPU reset, bypassing this GPIO and thus leaving the TPM locked. These
ChromeOS devices need to detect that condition in their bootblock and
trigger a second (proper) reboot.
This patch adds some code to generalize this previously
mainboard-specific functionality and uses it on Veyron boards. It also
provides some code to add the proper eventlog entry for a watchdog
reset. Since the second reboot has to happen before firmware
verification and the eventlog is usually only initialized afterwards, we
provide the functionality to place a tombstone in a memlayout-defined
location (which could be SRAM or some MMIO register that is preserved
across reboots).
[pg: Integrates
'mips: Temporarily work around build error caused by <arch/io.h> mismatch]
BRANCH=veyron
BUG=chrome-os-partner:35705
TEST=Run 'mem w 0xff800000 0x9' on a Jerry, watch how a "Hardware
watchdog reset" event appears in the eventlog after the reboot.
Change-Id: I0a33820b236c9328b2f9b20905b69cb934326f2a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fffc484bb89f5129d62739dcb44d08d7f5b30b33
Original-Change-Id: I7ee1d02676e9159794d29e033d71c09fdf4620fd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242404
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Id: c919c72ddc9d2e1e18858c0bf49c0ce79f2bc506
Original-Change-Id: I509c842d3393bd810e89ebdf0dc745275c120c1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242504
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9749
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BUG=chrome-os-partner:34436
BRANCH=none
TEST=Built and booted on pinky w/ depthcharge fmap patch,
used mosys to verify that eventlog entries get populated:
entry="0" timestamp="2015-01-06 13:45:33" type="Log area cleared" bytes="4096"
entry="1" timestamp="2015-01-06 13:45:33" type="System boot" count="0"
entry="2" timestamp="2015-01-06 13:45:33" type="Chrome OS Developer Mode"
Change-Id: I74ba8b271328453c8b91f11e7858754a80806c31
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 197010f057f4835a30ed2e71f47ca51fc181afe4
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I19cb884be5c3e00975599e96e0223e33d32e7c0d
Original-Reviewed-on: https://chromium-review.googlesource.com/238830
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9644
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Turns out there are uses for memlayout regions not specific to vboot2.
Rather than add yet another set of headers for a single region, let's
make the vboot2 one common for chromeos.
BRANCH=veyron
BUG=chrome-os-partner:35705
TEST=Booted Jerry, compiled Blaze, Cosmos, Ryu and Storm.
Change-Id: I228e0ffce1ccc792e7f5f5be6facaaca2650d818
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c6d7aab9f4e6d0cfa12aa0478288e54ec3096d9b
Original-Change-Id: I1dd7d9c4b6ab24de695d42a38913b6d9b952d49b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242630
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9748
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The 4 byte offset value will be stored in SRAM and shared between
different coreboot stages.
BRANCH=storm
BUG=chrome-os-partner:3416, chromium:445938
TEST=with the rest of the patches in, storm successfully boots into
Linux login prompt
Change-Id: Id8df75b0c679e274532660d55410291e59f3b520
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8f2f7cf6263f4c2db70b1c87ec67f6b0308059b3
Original-Change-Id: I1ebfada93e222992300cd695d04669988206d4b1
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/237660
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
This patch introduces a new option (CONFIG_MULTIPLE_CBFS_INSTANCES) to
allow multiple CBFS instances in the bootrom.
When the new option is enabled, the code running on the target
controls which CBFS instance is used. Since all other then header CBFS
structures use relative addressing, the only value which needs
explicit setting is the offset of the CBFS header in the bootrom.
This patch adds a facility to set the CBFS header offset. The offset
value of zero means default. i.e. the CBFS initialization code still
discovers the offset through the value saved at the top of the ROM.
BRANCH=storm
BUG=chrome-os-partner:34161, chromium:445938
TEST=with the rest patches in, storm target successfully boots from RW
section A.
Change-Id: Id8333c9373e61597f0c653c727dcee4ef6a58cd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e57a3a15bba7cdcca4a5d684ed78f8ac6dbbc95e
Original-Change-Id: I4c026389ec4fbaa19bd11b2160202282d2f9283c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/237569
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9747
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Pistachio UART closely matches 8250, the only difference is that its
register file is mapped to a 32 bit bus.
Provide a function to report register with so that the Coreboot table
entry gets correct value.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: Icd72b115b4f339800d6c8b210a6617398232f806
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e1dc4156949b20efafbca2c19ff424436a400087
Original-Change-Id: Icafb014af338e05bbf1044b791683733685ffab3
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240028
Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some SOCs (like pistachio, for instance) provide an 8250 compatible
UART, which has the same register layout, but mapped to a bus of a
different width.
Instead of adding a new driver for these controllers, it is better to
have coreboot report UART register width to libpayload, and have it
adjust the offsets accordingly when accessing the UART.
BRANCH=none
BUG=chrome-os-partner:31438
TEST=with the rest of the patches integrated depthcharge console messages
show up when running on the FPGA board
Change-Id: I30b742146069450941164afb04641b967a214d6d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42
Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240027
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9738
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
we use Kconfig define sdram size before, but there may use
different sdram size in the same overlay, so we must detect
sdram size at runtime now. If we use 4G byte sdram, we can
use[0x00000000:0xff000000], since the [0xff000000:0xffffffff]
is the register space.
BUG=chrome-os-partner:35521
TEST=Boot from mighty
BRANCH=None
Change-Id: I7a167c268483743c3eaed8b71c7ec545a688270c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad4f27dd08c467888eee87e3d9c4ab3077751898
Original-Change-Id: Ib32aed50c9cae6db495ff3bab28266de91f3e73b
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/243139
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I always had that TODO comment in there but I had already forgotten what
I even meant by it. It's really just a simple cleanup... this function
is (currently) veyron-specific and doesn't belong in common code.
BRANCH=veyron
BUG=None
TEST=Booted Jerry.
Change-Id: Iccd6130c90e67b8ee905e188857c99deda966f14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d188398704575ad2fedc2a715e609521da2332b0
Original-Change-Id: I6ce701a15a6542a615d3d81f70aa71662567d4fa
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241190
Reviewed-on: http://review.coreboot.org/9733
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We've traditionally tucked the framebuffer at the end of memory (above
CBMEM) on ARM and declared it reserved through coreboot's resource
allocator. This causes depthcharge to mark this area as reserved in the
kernel's device tree, which may be necessary to avoid display corruption
on handoff but also wastes space that the OS could use instead.
Since rk3288 boards now have proper display shutdown code in
depthcharge, keeping the framebuffer memory reserved across the handoff
(and thus throughout the lifetime of the system) should no longer be
necessary. For now let's just switch the rk3288 implementation to define
it through memlayout instead, which is not communicated through the
coreboot tables and will get treated as normal memory by depthcharge.
Note that this causes it to get wiped in developer/recovery mode, which
should not be a problem because that is done in response to VbInit()
(long before any images are drawn) and 0 is the default value for a
corebootfb anyway (a black pixel).
Eventually, we might want to think about adding more memory types to
coreboot's resource system (e.g. "reserved until kernel handoff", or
something specifically for the frame buffer) to model this situation
better, and maybe merge it with memlayout somehow.
CQ-DEPEND=CL:239470
BRANCH=veyron
BUG=chrome-os-partner:34713
TEST=Booted Jerry, noticed that 'free' now displays 0x7f000 more bytes
than before (curiously not 0x80000 bytes, I guess there's some alignment
waste in the kernel somewhere). Made sure the memory map output from
coreboot looks as expected, there's no visible display corruption in
developer/recovery mode and the 'cbmem' utility still works.
Change-Id: I12b7bfc1b7525f5a08cb7c64f0ff1b174df252d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 10afdba54dd5d680acec9cb3fe5b9234e33ca5a2
Original-Change-Id: I1950407d3b734e2845ef31bcef7bc59b96c2ea03
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/240819
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9732
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Each type of cache might have different cache line size.
Call the proper get_<*>cache_line function for each cache
type.
Fixes problem with get_L2cache_line which previously
targeted L3 cache line in the config register, instead of
L2 cache.
TODO: add support for tertiary caches and have cache
operations be called per CPU, not per architecture.
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; worked as expected;
BRANCH=none
Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4
Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241853
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a function that allows reading of the status register
from the SPI chip. This can be used to determine whether
write protection is enabled on the chip.
BUG=chrome-os-partner:35209
BRANCH=haswell
TEST=build and boot on peppy
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/240702
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c58f17689162b291a7cdb57649a237de21b73545)
Change-Id: Ib7fead2cc4ea4339ece322dd18403362c9c79c7d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9fbdf0d72892eef4a742a418a347ecf650c01ea5
Original-Change-Id: I2541b22c51e43f7b7542ee0f48618cf411976a98
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/241128
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/9730
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A payload may want to run erase operations on SPI NOR flash without
re-probing the device to get its properties. This patch passes up
three properties of flash to achieve that:
- The size of the flash device
- The sector size, i.e., the granularity of erase
- The command used for erase
The patch sends the parameters through coreboot and then libpayload.
The patch also includes a minor refactoring of the flash erase code.
Parameters are sent up for just one flash device. If multiple SPI
flash devices are probed, the second one will "win" and its
parameters will be sent up to the payload.
TEST=Observed parameters to be passed up to depthcharge through
libpayload and be used to correctly initialize flash and do an erase.
TEST=Winbond and Gigadevices spi flash drivers compile with the changes;
others don't, for seemingly unrelated reasons.
BRANCH=none
BUG=chromium:446377
Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126
Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239570
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a 10us delay in between (re-)configuring and reading
GPIOs in gpio_base2_value() to give the values stored some time
to update.
As far as I know this hasn't bitten us since the function was
added, but adding a short delay here seems like the right thing
to do.
BUG=none
BRANCH=none
TEST=built and booted on Brain
Change-Id: I869cf375680435ad87729f93d29a623bdf09dfbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2484900fc9ceba87220a293de8ef20c3b9b20cfd
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I79616a09d8d2ce4e416ffc94e35798dd25a6250d
Original-Reviewed-on: https://chromium-review.googlesource.com/240854
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The AS3277 RTC code seems to closely follow the corresponding Linux
driver. Unfortunately, while coreboot (and even other parts of Linux,
like mktime()) directly follows the standard IBM PC RTC time
representation (except for the BCD part), Linux' struct rtc_time decided
to use 0-based (instead of 1-based) months instead.
This patch removes the faulty month offset that was copied into our
driver so that we will generate correct timestamps again.
BRANCH=nyan
BUG=chrome-os-partner:34108
TEST=firmware_EventLog (pre-release version) gets further than before
(and then craps up on unrelated problems with suspend/resume events).
Change-Id: Ica221a8bcfd7c1c6cd7ba382d760b586d511e3a3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b55c3f5bbecc776a71338256b910aecccac1e04
Original-Change-Id: I163fa4778ec534cd9e6f92a6b6dc55e9871a6a82
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238122
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9723
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change defines a custom romstage entry for bg4cd. the entry code
stalls subcores, sets up the stack, and clears the bss before jumping to main.
BUG=none
BRANCH=tot
TEST=built all current boards. booted cosmos p1
Change-Id: Idde43f94555bec7804a16928c58ce673956a39e5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a35e12eb29b351cc0baaea24344f00d2ba905f6
Original-Change-Id: I9172e873a43847f3ea82cd1d9fd0841f0db83994
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238022
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9722
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
this change defines stage_entry as a weak symbol so that a board
can implement custom stage entry code.
BUG=none
BRANCH=tot
TEST=built all current boards. booted cosmos p1.
Change-Id: If8f6945ecdc5047558bb6359aa997867e36f33b9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 86d5008981d0b01652907baab47a476d784a2ceb
Original-Change-Id: Ib43158c4013e6393d86a9aef37cf444a48b9fc79
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238021
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9721
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current display init code causes Brain to crash when trying
to allocate resources. This just avoids doing display init if a
config variable is set. Once code has been implemented to properly
setup different types of displays we can get rid of this hack.
BUG=none
BRANCH=none
TEST=built and booted (to depthcharge) on Brain, compiled for
pinky with FEATURES=noclean and ensured config variable is 0
Change-Id: I9a7266c6bff5b7a6eb05b2b21fb65797bee392d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 804632ca67eaaf4174ca597d83b8923cb9abd1b7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I04c9e8181c58fa0608fd20776fa8c4798a023474
Original-Reviewed-on: https://chromium-review.googlesource.com/235922
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9720
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch activates the chip driver for Winbond SPI flash (which,
incidentally, looks 99.9% the same as the Gigadevice driver but still
requires some extra 500+ bytes of object code... there's definitely room
for improvement here). Shuffle around rk3288 memlayout to make a little
more room in the bootblock.
BRANCH=veyron
BUG=chrome-os-partner:34176
TEST=Booted Pinky. Checked bootblock and verstage memsz of final binary
and noticed that both only have less than 500 bytes left against their
memlayout boundary. The next piece of code we add will cause some
serious headaches...
Change-Id: I97ea6ac334104e4219e310afc557c164b2ff19d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8769e5a34ad3cd417132646fbb58ff51c29fb640
Original-Change-Id: Id2f1204c30aa28251cf85cb80d7ca44947388dba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236977
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9719
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
we use the delay 200ms to meet the edp power timing request before,
it waste time, so we use the HPD function to detect the edp panel now.
In previous version, the hardware may not support the edp HPD function,
so in the code it will spend 200ms to detect hpd single, if it don't get
the hpd single, it will contiue the edp initialization process, to compatible
all of the hardware version.
BUG=chrome-os-partner:35623
TEST=Boot from Mighty, and display normal
BRANCH=None
Change-Id: I82c6a80e37fa42eef3521e6ebbf190d7e80fcece
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 7a5343eb9af12cae9a15284217762a91ae24bac6
Original-Change-Id: I21c0ef6ce4643e90a192d8b86659264895b5fda9
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242792
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: http://review.coreboot.org/9659
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
backlight timing: LED_VCC->LED_PWM->LED_EN, we modify the
code to meet the timing.
BUG=chrome-os-partner:36201
TEST=Boot from jerry, and scope the backlight timing
BRANCH=None
Change-Id: I6bfa6af176400086e4af0112a63127c1152ca70e
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 52ac0b2944cea7dc860bfea12fe44851436bb7f7
Original-Change-Id: I6c53a822410ad706383c6d9fa2b5f0437775f710
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/244639
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The recovery button on Rialto should be GPIO 255, the LED Push Key.
Note we want to keep the recovery button on servo functional because
many protos are not assembled and developers can't "push" the push key.
The GPIO passed to payloads (and kernel) is only mapped to Push Key.
BUG=none
TEST=emerge-veyron_rialto coreboot chromeos-bootimage
BRANCH=veyron_rialto
Change-Id: I66f94cf232caa53a3b28db517620e4b6e9b9af0e
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 66ee55f6312efaeb337eb2881cd5eff5365b4105
Original-Change-Id: I0a7ebeed6506fbd938084c9a078a7cf1c7b914b9
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/244515
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The FMAP for Rialto has no ecrwhash and would cause verstage to
incorrectly load ramstage (instead of romstage) when looking for
subsection inside RW blob.
We have to override the index of stages to boot correctly.
BRANCH=veyron_rialto
BUG=none
TEST=emerge-veyron_rialto coreboot chromeos-bootimage
Boots successfully on Rialto boards.
Change-Id: I031703d97a68e42dc17630ab5df85f8cba47e5e5
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 24ba4b16b4a2fe5469296f8d40286ed926cefc3c
Original-Change-Id: I637ea23e1e8265781e52367d1306dbf854c2ccad
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/244577
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Our use of the bucks may exceed their default maximum inductor current.
Just set it to the highest possible value for every buck we configure to
avoid problems... the kernel can later fine-tune the values further if
needed. (Also some slight grammar updates while I'm in there.)
BRANCH=veyron
TEST=Build and Boot on Jerry
BUG=None
Change-Id: If8258cf4feefe191604365405bff1f20c8ab8746
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 065a163bb902b8c96d05bfef6ed4885aa20f31cc
Original-Change-Id: I3801cabeb93d7bf7ecc02db0e69d4932c9394db9
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/242785
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: http://review.coreboot.org/9655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
tMRD request 10nCK in LPDDR3, we set the DDR_PCTL_TMRD BIT0~BIT2 to generate
this signal, but the max value we can set is 7, so the standard can not be met.
So, now we send the Mode Register Set command manually, and hence we can add
the delay manually.
BUG=chrome-os-partner:34608
TEST=loop reboot
BRANCH=veyron
Change-Id: Id974ab935c2df6ea35dcdd240378ffc68de0204d
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: b60a4de6ff3ad3720c2c06ed7de03ed942360e6c
Original-Change-Id: I0d29ea9cd82ef018e835ae53090a47d0299ef61d
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242176
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9654
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We want a reset signal to last 200us. The length of a reset signal is
represented by BIT0~BIT16 in DDR_PUBL_PTR2. When DDR memory runs at
667MHz, the calculated value for the reset signal is 0x20850, which is
bigger than the maximum value that can be described with 17 bits
(0x1ffff). As a result, the memory controller only sees 0x850, which
generates a 3.5us reset cycle instead, which violates the standard and
negatively impacts memory stability.
So instead, we now set it to the maximum value (0x1ffff) to prevent this
overflow, resulting in a reset signal of 196us for 667MHz DDR memory.
BUG=chrome-os-partner:34875
TEST=loop reboot
BRANCH=veyron
Change-Id: Ia01f8a0414b49fa3ecf4d543cfa1822e29ee4cc4
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 767a4a3cb8dff47cb15064d335b78ffa5815914d
Original-Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/242175
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
K4B4G1646Q-HYK0 is a variant of K4B4G1646D-BYK0 with
a different physical package and the same config parameters.
BRANCH=none
BUG=chrome-os-partner:34940
TEST=boot on Jerry board with K4B4G1646Q-HYK0
Change-Id: I485eede309850ef6b3a52e2a548b6b032d281293
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: e925d784e1ebe444f5a5bcab47c8a661b0c6c527
Original-Change-Id: I31bcb348a45ff76e8e08127063bd0d04443ccb79
Original-Signed-off-by: Paul Ma <magf@bitland.com.cn>
Original-Reviewed-on: https://chromium-review.googlesource.com/241787
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Trybot-Ready: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9650
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
BRANCH=None
TEST=Boot and run jerry rev2 board
BUG=None
Change-Id: I95ec99e444c9cff3008bac5d1e6c3365fc2229a0
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: f9075e6172d1ae503dc26bac8f1057455dc93c39
Original-Change-Id: Ice60a4576c9eb386599a545c1b8d470e8a2eed68
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/236500
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Paul Ma <magf@bitland.com.cn>
Original-Tested-by: Paul Ma <magf@bitland.com.cn>
Reviewed-on: http://review.coreboot.org/9635
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Derived from of veyron_brain with new memory configuration.
BUG=chrome-os-partner:35072
TEST=built and boot on rialto-rev0 boards.
BRANCH=veyron
Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040
Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/238946
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Trybot-Ready: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch finds the RPM image in the CBFS, loads it as defined by the
MBN header and signals to the RPM processor where the image is
located and waits for confirmation of the RPM starting.
The interactions with the RPM processor are copied as is from the
vendor provided sample code.
Debug messages added to help identify problems with loading the blobs,
should they ever happen.
BRANCH=storm
BUG=chrome-os-partner:34161
TEST=ramstage reports both TZBSP and RPM starting.
Change-Id: I81e86684f9d1b614f2059ee82c6561f9484605de
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbf2eda04a6e72b4f7b780f493b5a1cea0abfeb7
Original-Change-Id: Ic10af0744574c0eca9b5ab7567808c1b8d7fe0c2
Original-Signed-off-by: Vikas Das <vdas@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236661
Original-Reviewed-by: Varadarajan Narayanan <varada@qti.qualcomm.com>
Reviewed-on: http://review.coreboot.org/9692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the apps processor watchdog reset to do a hard reset.
The watchdog reset drives the RESETOUT on the chip.
Modify register address definitions to be able to use pointers and
pointer arithmetics.
BRANCH=storm
BUG=chrome-os-partner:34334
TEST=the chip resets and the control returns to start of SBL.
Change-Id: Ib5772ab152b27058fde1be9de2d2ac26bfe00ca4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d50413cb614ef05ada93be1252fe5ef617a94d91
Original-Change-Id: I9b249d057b473429335587f7241ca462b4a6a8b7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236141
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
Reviewed-on: http://review.coreboot.org/9691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Read the TZBSP blob from CBFS and run it. A side effect of the blob
execution is switching the processor into User mode.
Starting TZBSP requires processor running in Supervisor mode, TZBSP
code is compiled for ARM. Coreboot is executing in System mode and is
compiled for Thumb. An assembler wrapper switches the execution mode
and interfaces between Thumb and ARM modes.
BUG=chrome-os-partner:34161
BRANCH=Storm
TEST=manual
With the preceeding patches the system successfully loads to
depthcharge in recovery mode.
Change-Id: I812b5cef95ba5562a005e005162d6391e502ecf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7065cf3d17964a1d9038ec8906b469a08a79c6e2
Original-Change-Id: Ib14dbcbcbe489b595f4247d489d50f76a0e65948
Original-Signed-off-by: Varadarajan Narayanan <varada@qti.qualcomm.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/229026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9690
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Booting depthcharge requires much larger CBFS cache, but by the time
depthcharge is being booted DRAM is already initialized. Use different
memory spaces for CBFS cache before and after DRAM is available.
Also, make sure that CBMEM uses memory below CBFS cache in DRAM.
BRANCH=storm
BUG=chrome-os-partner:34161
TEST=with this change on Storm ramstage finds and boots depthcharge in
recovery mode
Change-Id: Icd1bbf4bcc5f9d92b2653b5a8891409105a25353
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e1e0b029b7fb09b84784373150cc4ce9eea7b3f5
Original-Change-Id: I33fd97806b2db6fab2adc44b67e5f54258642967
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234543
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9688
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Read two blobs from CBFS: cdt.mbn (memory configuration descriptor)
and ddr.mbn (actual memory initialization code).
Pointer to CDT which starts right above the MBN header is passed to
the memory initialization routine. Zero return value means memory
initialization succeeded.
BRANCH=storm
BUG=chrome-os-partner:34161
TEST=with upcoming patches memory initialization succeeds.
Change-Id: Ia0903dc4446c03f7f0dc3f4cc3a34e90a8064afc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1d79dadd7d47dd6d01e031bc77810c9e85dd854b
Original-Change-Id: Ib5a7e4fe0eb24a7bd090ec3553c57cd1b7e41512
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234644
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9686
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Julius Werner