This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.
Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
I originally put up this document for discussion in 2015
(mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX4V2OSXAQC4B2VUENSFZEWRPPOVRH2/)
(doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeIc7Vo/edit)
It may be time to revisit the way we define our image layouts now that
there are new fmap schemes for new vboot uses. The approach outlined in
this document may or may not be the right one, but it's something we
have, so let's discuss.
Compared to the doc, this will
* be updated (things changed in the last 3.5 yearws)
* integrate feedback to the doc and on the mailing list back then
Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It is similar to X200s, with U-series CPU, slightly different gpio
setup, no docking support, and no superio chip.
Tested:
- CPU Core 2 Duo U9400
- Slotted DIMM 4GiB*2 from samsung
- Camera
- pci-e slots
- sata and usb2
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
Linux payload (Heads) and Seabios.
TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in
CB:4294 ) for h8-using devices without a dock.
Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.
TEST=the patch was ran on affected HW and success was reported
Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.
To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.
Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.
Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.
Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The port is based on the x201 / t410s.
2537-vg5 / i5, no discrete gpu
Tested and working:
* Native raminit
* Native gfxinit
* Booting Seabios 1.12.1
* Booting from EHCI
* Running GNU/Linux 5.0.0
* No errors in dmesg
* EHCI debug on the devices left side, bottom-right
* Keyboard
* Fn keys (Mute, Volume, Mic)
* Touchpad
* TPM
* Wifi
* Sound
* USB
* Ethernet
* S3 resume
* VBOOT
Testing in progress.
Untested:
* VGA
* Displayport
* Docking station
Bugs:
* AC adapter can't be read from ACPI
* TPM not working with VBOOT and C_ENV BB
Details for flashing externally:
1. Disconnect all power
2. Connect the external flasher
3. Connect the power cord (This fixes internal power control)
4. Remove the power cord
Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Also get rid of some manual hyphenation.
Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The format was retired 10 years ago when we moved to the new build
system, kconfig and sconfig. Retire the doc as well.
Change-Id: Ica1c353a80d411845b92038521d85ad5f3d359bc
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Fixes an issue with amd/index.md not being part of a toctree
Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This splits the x11-lga1151-series' documentation into a generic and a
board specific section as a preparation for CB:35427.
Additionally this adds some more information on the x11ssh board.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.
BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
run 'ifdtool -t' with a bad bios image and verify expected issues
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Create documentation on padmelon, including how to program the SPI. Also
include an index.md pointing to the documentation, as currently there's no
maiboard documentation folder for AMD.
BUG=none.
TEST=none.
Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Eltan is missing in the vendor index.
Documentation of the eltan vendorcode is availlabe already.
Add eltan to vendor index.
BUG=N/A
TEST=N/A
Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Remove duplicate headings, move vendor sections that were placed
amidst other vendor hierarchies, and while we are at it, sort it
alphabetically.
Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We generally try to stay away from ascribing attributes to (future)
devs. "Rookie guide" refers to the reader, while "tutorial" refers
to the material.
In the same spirit, move from "lessons" to "parts". It's not school :-)
Change-Id: I11a69a2a05ba9a0bc48f8bf62463d9585da043ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.
It generates a device HID based on the decoded I/O range.
Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.
Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
resource settings on specific LDNs
Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Line length limit was bumped to 96 characters, but the coding style did
not reflect such a change.
Change-Id: Ifdbb8bc04e49e1fbe9b0c8a642ae814d5a60004a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled
The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.
Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add support for the X11SSH-TF which is based on Intel KBL.
Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init
Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common
For more details have a look at the documentation.
Please apply those patches as well for good user experience:
Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.
Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.
BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.
Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested on qemu-riscv.
Depends on OpenSBI integration and proper memory detection in qemu.
Boots into Linux until initrd should be loaded.
Tested on SiFive/unleashed:
Boots into Linux until earlycon terminates.
Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.
To execute:
$ qemu-system-aarch64 -M virt,secure=on,virtualization=on \
-cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic
Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
John Lewis has updated his homepage to indicate he is no longer
producing coreboot images, nor supporting existing ones, so
remove the entry from the list.
Change-Id: I9b07cc4cb4adeb36eff1f904b23fb25da2c89c68
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We keep a mirror in case any of the originals disappear, but we also
have to remember to update it.
Change-Id: Ib4be91d1d508d3d5dba7ace1d167d8e528d58b3d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We plan to retire that symbol after 4.11 as well, with relocatable
ramstage becoming the normal mode of operation.
Change-Id: I36029215e5c8726f7dcc268bddc0d2b0161e3c40
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Marc found more interesting things to do (yay, Marc!) and Martin
offered to volunteer on the arbitration board in his place.
Change-Id: Ic5bf00735afdf8942e543043238890011a82c890
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The paragraph starts talking about community organizers. By making
their definition a separate paragraph it's hopefully easier to find
what this means.
Change-Id: Icb9abbbd05b59bd4ee741d10f4c9c1a8c321b430
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make it a separate section, emphasize that people should get support
early, note that personal interaction and email are the two best
ways to seek help.
Change-Id: I8cb613fefe1a7b4db1ee948fb9927a38f0421011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
"Always assume" is rather final and (in some readings) invalidates the
need for the rest of the text.
Change-Id: Ibf6f776494367d012ce69a64fa928c1dd4206c0e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Make the title for lesson 1 match the format used for lesson 2 and the
lessons index, for consistency purposes.
Change-Id: I133d758ddf4974096cbf9f10ae96c148fc859efc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
As Intel doesn't even document known bugs add a list of
FSP bugs here.
Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.
Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.
Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.
Required for clearing all system memory as part of security API.
Tested on wedge100s:
Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
Takes less than 1 second to clear 4GiB of DRAM.
Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add files to introduce a memory clearing framework.
Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by
platforms, that are able to clear all DRAM.
Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user
selectable to always clear DRAM on non S3 boot.
The function security_clear_dram_request tells the calling platform when
to wipe all DRAM. Will be extended by TEE frameworks.
Add Documentation for the new security API.
Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Describe how to run coreboot on the PC Engines apu2 mainboard.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Describe how to run coreboot on the PC Engines apu1 mainboard.
Change-Id: If79693e893c4afe52bf1c9aa8017ac6f650a96e4
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* Add chips ops for IPMI KCS.
* Get IPMI version over KCS.
* Generates ACPI SPMI table for IPMI KCS.
* Generates SMBIOS type 38 for IPMI KCS.
* Generates ACPI SPMI device for IPMI KCS on LPC device.
* Add documentation
To use this driver on BMC that support KCS on I/O:
1. Add an entry to the devicetree.cb:
chip drivers/ipmi
device pnp ca2.0 on end # IPMI KCS
end
2. Select IPMI_KCS in Kconfig.
3. (Optional) enable LPC I/O decode for the given address.
Tested on Wedge100s.
Change-Id: I73cbd2058ccdc5395baf244f31345a85eb0047d7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch adds documentation about the UP² mainboard
and the IFWI used by Apollolake platform.
Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Begin a directory for AMD soc devices and add an explanation of
how Family 17h works. Newer AMD systems use a unique paradign
for initializing the x86 processors.
Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Add initial board commit based on HP8200 SFF.
* Add documentation.
* Serial and PCIe slot are working.
Tested on HP Z220.
Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.
Configure 'Onboard memory manufacturer' which must match HW.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701
Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
We keep its definition in libpayload, though, to maintain compatibility
with existing payload code. For now.
Change-Id: I8fc0d0136ba2316ef393c5c17f2b3ac3a9c6328d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch contains the general files for the vendorcode/eltan that has
been uploaded recently:
- Add eltan directory to vendorcode.
- Add documentation about the support in the vendorcode directories.
- Add the Makefile.inc and Kconfig for the vendorcode/eltan and
vendorcode/eltan/security.
BUG=N/A
TEST=Created verified binary and verify logging on Portwell PQ-M107
Change-Id: Ic1d5a21d40b6a31886777e8e9fe7b28c860f1a80
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Document known issues with 'disabled' ME.
Change-Id: I364f3ed49341523c781eb2f3b41e866f33632a7e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32889
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also add the HP EliteBook document from wiki.
Change-Id: I189db9c279705af53d82af66d0c2e8afb6f84d73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30950
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon
initialization returns an error when graphics was also initialized.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails
to locate or validate a vendor supplied binary.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a new post code POST_INVALID_CBFS, used when coreboot fails to
locate or validate a resource that is stored in CBFS.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: If1c8b92889040f9acd6250f847db02626809a987
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a new post code, POST_INVALID_ROM, used when coreboot fails to
locate or validate a resource that is stored in ROM.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: Ie6de6590595d8fcdc57ad156237fffa03d5ead38
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Works:
- bootblock, romstage, ramstage
- Serial console UART0, UART1
- SPI flash console
- iGPU init with libgfxinit
- LAN1, LAN2
- USB2, USB3
- HDMI, DisplayPort
- eMMC
- flashing with flashrom externally
WIP:
- Documentation
- VGA
For some reason Seabios can not find the CBFS region
and therefore it can't load seavgabios, but generally
it is working as soon as Linux is booted.
- ACPI
Works not:
- Devices needs proper configuration
- Seabios can't find CBFS region
Untested:
- GPIO pin header
- 60 pin EXHAT
- Camera interface
- MIPI-CSI2 2-lane (2MP)
- MIPI-CSI2 4-lane (8MP)
- SATA3
- USB3 OTG
- embedded DisplayPort
- M.2 slot
- mini PCIe
- flashing with flashrom internally using Linux
Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add information about flash and programming header.
Change-Id: If34016e20dd580f92695bef5b67dd0c282b0b421
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
- The link to create an account is now "Sign in" and not "Register"
- Use monospace formatting for terminal commands and file names
- Properly escape less-than and greater-than
- Correct the 'make lint' example command
- Reformat example commit messages
- Add formatting for website links
- Other whitespace fixes
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I9931bef8c30387d1c08b59973d6de9b5c0419814
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If username is not set, then the ssh option is not available.
This was initially confusing for me.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I731c29a1daa9f8c298710471c7d1fe758b059d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Convert the HTML document to markdown and place it under security section.
Change-Id: I212c6d0c977fd6772371ff6676478d48cc215d6e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32610
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).
BUG=None
TEST=None (only documentation)
Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use rst parser to convert the csv to markdown tables.
Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Allow the use of CSV files if properly referenced from markdown.
Sphinx will parse the file and create a human readable table,
allowing easy integration of autogenerated files.
Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Describe the coreboot stages, given a short introduction what is done
and add a chart for coreboot's vs EDK II bootflow as well as the source
for the SVG.
TODO: Describe stages in detail in a separate commit.
Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
- Now there is no need to additionally configure the FSP
before building;
- PEG works with high link speed 8 GT/s (Gen 3);
- external GPU supported, but dynamic switching between iGPU and PEG
is not yet supported.
Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Michael Niewöhner