Commit Graph

63 Commits

Author SHA1 Message Date
Patrick Georgi c8feeddf34 Unify Local APIC address definitions
We used several names for that same value, and hardcoded the value
at some more places.

They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).

Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-08 15:39:05 +01:00
Patrick Georgi b0a9c5ccf3 mptable: Refactor mptable generation some more
The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.

Coccinelle script:
  @@
  identifier mc;
  @@
  (
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  |
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  )

Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:11:08 +02:00
Patrick Georgi c75c79bd02 mptable: Get rid of fixup_virtual_wire
As stated in some code files, fixup_virtual_wire was established
to avoid touching 200 invocations of the mptable code.

Let Coccinelle do it:
  @@
  type T;
  identifier v;
  @@
  -void fixup_virtual_wire(T v)
  -{ ... }

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A);
  +v = smp_write_floating_table(A, 0);

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A, 0);
  -fixup_virtual_wire(v);
  +v = smp_write_floating_table(A, 1);

Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/245
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:44 +02:00
Patrick Georgi 6eb7a53169 mptable: Refactor lintsrc generation
We copied pretty much the same code for generating mptable entries for
local interrupts (with some notable exceptions).
This change moves these lines into a generic function "mptable_lintsrc"
and makes use of it in many places.

The remaining uses of smp_write_lintsrc should be reviewed and replaced
by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.

This patch was generated using Coccinelle:
  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @@
  expression mc;
  expression isa_bus;
  @@
  -smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
  -smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, isa_bus);

  @m@
  identifier mc;
  expression BUS;
  @@
  -#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
  ...
  -IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
  -IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
  +mptable_lintsrc(mc, BUS);

Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/244
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:31 +02:00
Stefan Reinauer 42fa7fe28b run uart_init() from console_init, just like the other console initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20 20:54:07 +00:00
Uwe Hermann c36d506a05 Get mptable OEM/product ID from kconfig variables.
We currently use "COREBOOT" unconditionally as the "OEM ID" in our
mptable.c files, and hardcode the mainboard name in mptable.c like this:

  mptable_init(mc, "DK8-HTX     ", LAPIC_ADDR);

However, the spec says

  "OEM ID: A string that identifies the manufacturer of the system hardware."
  (Table 4-2, page 42)

so "COREBOOT" doesn't match the spec, we should use the hardware vendor name.

Thus, use CONFIG_MAINBOARD_VENDOR which we have already as the "OEM ID"
(truncate/fill it to 8 characters as per spec).

Also, use CONFIG_MAINBOARD_PART_NUMBER (the board name) as "product ID",
and truncate/fill it to 12 characters as per spec, if needed.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6183 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-16 19:51:38 +00:00
stepan 8301d8348a second round name simplification. drop the <component>_ prefix.
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 07:07:33 +00:00
Uwe Hermann 4028ce7b76 Get rid of some unneeded function prototypes in romstage.c files.
Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07 19:16:07 +00:00
Uwe Hermann da22d2190d Mptable related fixes for ASUS P2B-DS.
- Add "select IOAPIC" in the board's Kconfig file.

 - Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
   CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
   didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).

 - Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
   that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
   are set.

 - Rework ASUS P2B-DS mptable.c to fix a number of things:

   - Convert it to use mptable_write_buses() as all mptable.c files should do.

   - Fix incorrect IOAPICID (it's 0x11 for the external 82093AA IOAPIC).

   - Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-30 21:27:13 +00:00
Tobias Diedrich b907d321a5 We need to call smp_write_lintsrc() instead of smp_write_intsrc() for
local ints. This is wrong in most coreboot mptables, probably all
generated by util/mptable/mptable.c.

After fixing this now XP can boot in MPS mode on my M2V.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 22:40:16 +00:00
Uwe Hermann 55dc223ccd Factor out common mptable code to mptable_init().
- Drop sig[], oem[], and productid[] fields in all mptable.c files, no
   longer needed. The sig[] is always the same ("PCMP"), the oem[] is
   currently also always the same ("COREBOOT"), and productid is being
   passed into mptable_init() directly as string now.

 - LAPIC_ADDR is passed in as parameter, too. While at the moment it's
   always the same value that is passed in, the LAPIC base address could
   also be relocated theoretically, so keep it as parameter for now.

 - Fix a few productid entries, they were (partially) incorrect:

   - DK8S2 (was "DK8X", copypaste)
   - 939A785GMH (was "MAHOGANY", copypaste)
   - X6DHE-G (was "X6DHE", incomplete board name)
   - H8DME-2 (was "H8DMR", copypaste)
   - H8QME-2+ (was "H8QME", incomplete board name)
   - X6DHE-G2 (was "X6DHE", incomplete board name)
   - X6DHR-iG2 (was "X6DHR-iG", incomplete board name)
   - GA-M57SLI-S4 (was "M57SLI", incomplete board name)
   - KINO-780AM2 (was "KINO", incomplete board name)
   - DL145 G1 (was "DL145G1", small fix as per vendor website)
   - DL145 G3 (was "TREX", wrong board name)
   - DL165 G6 (was "HP DL165 G6", drop vendor)
   - S2912 (was "S2895", copypaste)
   - VT8454c (was "VIA VT8454C", drop vendor, lower-case "c")
   - EPIA-N (was "P4DPE", copypaste)
   - pc2500e (was "PC2500", incorrect name)
   - S1850 (was "S2850", copy-paste)
   - MS-7135 (was "MS7135")
   - MS-9282 (was "MS9282")
   - MS-9185 (was "MS9185")
   - MS-9652 (was "K9ND MS-9652")
   - Ultra 40 (was "ultra40")
   - E326 (was "E325", copypaste)
   - M4A785-M (was "TILAPIA", copypaste)
   - P2B-D (was "ASUS P2B-D", drop vendor)
   - P2B-DS (was "ASUS P2B-DS", drop vendor)

 - Adapt the mptable utility to use mptable_init() too.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-25 15:32:07 +00:00
Uwe Hermann 74d1a6e8a1 We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 17:34:08 +00:00
Uwe Hermann 115c5b9824 Remove various .c #includes from Intel 440BX/82371EB boards.
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
   into distinct compilation units, and don't #include the files anymore
   in romstage.c files.

 - Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
   northbridge/intel/i440bx/debug.c.

 - Add various header files which are now needed.

 - Make functions that need to be visible non-static.

 - Drop a remaining "select ROMCC" from a 4440BX board.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 17:00:18 +00:00
Uwe Hermann 6798b47802 Convert all Intel 82371AB/EB/MB based boards to TINY_BOOTBLOCK.
Also:

Unfortunately Intel 440BX + 82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.

Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.

As an additional benefit this patch also gets rid of one .c file include
in romstage.c.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 16:24:28 +00:00
Uwe Hermann 6f2d20ec49 Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.

 - Add the following in src/cpu/intel/slot_1/Makefile.inc:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Remove "select ROMCC" from all 440BX board Kconfig files.

 - Drop all early_mtrr_init() calls, that's done by CAR code now.

Various small fixes were needed to make it build:

 - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
   those were never called anyways.

 - Remove the "static" from the main() functions in romstage.c files.

 - Always call dump_spd_registers() from the 440BX debug.c, but use
   "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
   is enabled in menuconfig.

 - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
   commented out) from romstage.c's, as we've done for most other boards.

 - Add missing #includes or prototypes. Some of the prototypes will be
   removed later when we get rid of the #include'd .c files.

Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-06 19:32:39 +00:00
Uwe Hermann 8fa90ec274 Cut the crap.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 21:16:27 +00:00
Jens Rottmann 9a684fcb0f Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block.  This makes it possible to
define user visible board specific options.  Moved all vendor names and PCI
ids to the vendors' Kconfigs.  Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if".  Sorted boards
(sort -d), cleaned whitespace.

This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used.  It it simply needed to have something to attach
the boards' "select" statements to.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:36:51 +00:00
Edwin Beasant eb50c7d922 Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06 21:05:04 +00:00
Patrick Georgi c5b87c8f89 Move generation of mptable entries for ISA to generic code.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-20 15:28:19 +00:00
Nils Jacobs dd6ad3447b license header fixes
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:48:05 +00:00
Patrick Georgi bf9e5384d7 Remove pc80/serial.c includes in ROMCC boards and include
it centrally in console/console.h instead.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 21:09:58 +00:00
Patrick Georgi 12584e2bd2 Drop console/console.c and pc80/serial.c from mainboards'
romstage.c.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 09:14:51 +00:00
Patrick Georgi 8d313685b0 Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"
in device trees. Adapt sconfig as necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-05 13:12:42 +00:00
Stefan Reinauer 5a1f597085 This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.

While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
  from romcc)

Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code 
		in cache_as_ram.inc)

Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31 14:34:40 +00:00
Stefan Reinauer 798ef2893c This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run 
    awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
    mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c 
cut some holes into the source.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29 22:08:01 +00:00
Stefan Reinauer 5e32823a68 __PRE_RAM__ is now correctly specified in the Makefile. No need to hack it into
romstage.c anymore

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29 19:19:16 +00:00
Myles Watson 08e0fb8810 Fix all the format string warnings.
Some other random warnings.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22 16:33:25 +00:00
Stefan Reinauer c02b4fc9db printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22 11:42:32 +00:00
Uwe Hermann 53c7276bd1 Use CPU_INTEL_SLOT_1 for Slot 1 boards (trivial).
This fixes a longstanding TODO item.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5205 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-13 20:36:11 +00:00
Keith Hui 9c1e1f0d3a Add SDRAMPWR_4DIMM Kconfig option (not user-visible in menuconfig).
Each Intel 440BX board should select this option if it has 4 DIMM
slots on the PCB, and _not_ select it (it defaults to 'n') if it
has 3 DIMMs on the PCB.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-13 20:16:48 +00:00
Patrick Georgi 37bdb87fab - make HAVE_HARD_RESET match what newconfig did
- introduce BOARD_HAS_HARD_RESET and use it if a board provides
hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component
- move a couple of rules out of the mainboards' Makefiles into
src/arch/i386/Makefile.inc:
	initobj-y += crt0.o
	obj-y += mainboard.o
	obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
	obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
	obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o
- remove Makefile.incs that are empty (or comment-only) after these
changes, incl. Makefile.romccboard.inc (and references to it)
- Make include not fail if Makefile.inc doesn't exist.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-27 08:39:04 +00:00
Patrick Georgi 2063197a4f Move all the copies of the romstage.inc rule to
src/arch/i386/Makefile.inc

For that to work, I had to:
- Add a CONFIG_ROMCC variable
- Set that variable on all ROMCC boards
- conditionally choose romcc or gcc rule based on that variable
- remove those two rules from all the boards' Makefiles
- switch a couple of boards to HAVE_OPTION_TABLE, as they actually have.

Also remove the duplication of rules with the sole difference of if
they depend on option_table.h or not.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09 12:21:10 +00:00
Stefan Reinauer 38f147ed3d janitor task: unify and cleanup naming.
cache_as_ram_auto.c and auto.c are both called "romstage.c" now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 12:20:50 +00:00
Patrick Georgi abf2ad716d newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 21:43:48 +00:00
Patrick Georgi 29647d97c5 Align several kconfig options to match newconfig:
HT_CHAIN_UNITID_BASE
HT_CHAIN_END_UNITID_BASE
SB_HT_CHAIN_ON_BUS0
SB_HT_CHAIN_UNITID_OFFSET_ONLY
MAX_CPUS
MAX_PHYSICAL_CPUS
ROM_SIZE
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2

Also hook up asus/p2b-ds

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 07:56:01 +00:00
Patrick Georgi d5663bac2c Move all IOAPIC selection to southbridges, and remove them
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.

Fix intel/d945gclf build, which was missing some ACPI component.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 17:30:36 +00:00
Stefan Reinauer a0c68f864e * Explicitly add __PRE_RAM__ where it should be added.
* Don't implicitly add __PRE_RAM__ in romcc. 

Fixes intel/xe7501devkit

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05 13:03:02 +00:00
Peter Stuge d08be7eecd Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 15:01:00 +00:00
Peter Stuge 777e069c5a Drop enable_mmx.inc. It reads (only) "Enabling mmx registers is a noop"
abuild tested

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 17:43:46 +00:00
Uwe Hermann d65509de14 Set default ROM sizes per-board to match the ROM chip that came
with the respective board.

Of course, the user can still override the size in menuconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 17:37:20 +00:00
Myles Watson b8e2027be8 Add CONFIG_GENERATE_* for tables so that the user can select which tables not
to build, but by default all the tables that are available are built.

Make PIRQ table build for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 13:35:47 +00:00
Uwe Hermann 95313d824d Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boards
and PIRQ tables were actually wrong, I cannot imagine they ever
worked properly.

 - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
   hard-coded numbers.

 - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.

 - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
   in the irq_tables.c file.

 - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
   boards where they were set to 0 (in order to be overridden in
   the respective targets/.../Config.lb).

   This is mainly done to aid Patrick's scripts for kconfig conversion.

 - Fix a number of comments in irq_tables.c files.

 - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
    - tyan/s1846
    - asus/a8v-e_se
    - asus/m2v-mx_se

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 21:51:33 +00:00
Uwe Hermann 99950c2192 Use
select UDELAY_TSC
  select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
for all 440BX and i810 boards as per Options.lb.

The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked
and improved later when the kconfig transition is done. For now
we keep the same values as in Options.lb.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 22:25:21 +00:00
Uwe Hermann b24e276503 PCI_ROM_RUN and CONSOLE_VGA are global options in Kconfig and
should not be set in per-mainboard Kconfigs.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-05 00:07:12 +00:00
Uwe Hermann 90950925c7 The new CBFS based build system requires the whole ROM to be accessible
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:

  Uncompressing coreboot to RAM.
  Jumping to image.
  Check CBFS header at fffedfe0
  magic is ffffffff
  ERROR: No valid CBFS header found!
  CBFS:  Could not find file fallback/coreboot_ram
  Jumping to image.

This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).

Build-tested and runtime-tested on ASUS P2B-F.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 23:50:06 +00:00
Patrick Georgi 24796fd364 This does away with CONFIG_ROM_PAYLOAD_START and CONFIG_PAYLOAD_SIZE.
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.

Various calculations in {no,}failovercalculation.lb are adapted
accordingly.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-04 18:55:40 +00:00
Patrick Georgi 6768f39a4b Remove:
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)

After this commit, there is no way to build an image that is not using
CBFS anymore.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 16:24:58 +00:00
Uwe Hermann 8f3ec7b1a3 Remove duplicate and not too useful Kconfig board comments as
per discussion on the mailing list.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-03 15:34:08 +00:00
Stefan Reinauer c13093b148 simplify source tree hierarchy: move files from sdram/ and ram/ to lib/
It's only three files. Also fix up all the paths (Gotta love included C files)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-23 18:51:03 +00:00
Uwe Hermann bca3b92df2 Add kconfig support for all missing Intel 440BX based boards.
This includes:

soyo/sy-6ba-plus-iii
a-trend/atc-6240
a-trend/atc-6220
gigabyte/ga-6bxc
biostar/m6tba
azza/pt-6ibd
tyan/s1846
abit/be6-ii_v2_0
compaq/deskpro_en_sff_p600msi/ms6119
msi/ms6147
asus/p2b
asus/p2b-d
asus/p2b-ds
asus/p3b-f

The Makefile.inc for all of them are _exactly_ the same, so I made a common
src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect
that many other romcc-based boards will be able to re-use this Makefile.inc.

Apart from the board name, most boards only differ in the Super I/O that's
being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different
as it doesn't have an irq_tables.c.

I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a
proper config in another patch.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-26 17:10:00 +00:00