Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.
Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print an error message and die if the PCI device cannot be found.
Change-Id: I10c58502658ebf12d1a8fe826ee7d47a618fd1c8
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1403000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 136538{8,9}, 140134{1,4}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33135
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: If394f14c4a39d6787ae31868241229646c26be7a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1365730, 14013{38,39,40,42,43}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It probably doesn't make sense to continue if the CK804 isn't found, and
doing so would perform uninitialized reads of the busn and io_base
arrays anyway, so let's return early.
Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1370586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Level trigger is recommended setting for touchscreen interrupt of
kohaku, so we would change it as the recommedation.
BUG=b:139179200
BRANCH=none
TEST=Verified touchscreen works on kohaku
Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is based on the hatch variant
BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/
Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disable SATA controller and SATA port 1 for eMMC SKUs
BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Change-Id: I6d95ff94b079a564f74c19739370101899843f00
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Disable eMMC controller for new SKU ID 23 and 24
2. Disable HS400 mode
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24
Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The src/lib/edid now supports reporting manufacturer name so we should
define that in MIPI panels and print out in initialization.
BUG=None
TEST=emerge-kukui coreboot; boots properly
Change-Id: If844da84ecca31307127b14c66bbe17c408699f3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The fixed size of init command in lcm_init_table is wasting lots of
space and we should change to packed array since the command buffer
already provides length information.
With this change, BOE panel init commands have been reduced from 4848
bytes to 1309 bytes.
BUG=b:80501386,b:117254947
TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly
Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Kukui variants may have eDP panels connected via a PS8640 MIPI bridge
which we may retrieve EDID dynamically.
BUG=b🅱️137517228
TEST=emerge-jacuzzi coreboot chromeos-bootimage; boots and see display.
Change-Id: I85aac5255e6a3e6019299670486214ecffbf9801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34516
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Declare the following panel for Kodama:
- BOE TV101WUM-N53
BUG=b:138156559
TEST=builds Kodama image and working properly
Change-Id: I129cb6bf084b76da3ad33b7a19e38e884442b1aa
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34505
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support Kukui rev 2 panel (via SSD2858).
BUG=b:129299873
BRANCH=none
TEST=Build as Kukui and boots on Rev 2 unit.
Change-Id: Icc16c4297eb3c6b6a4770a36661a2e3cab418048
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Declare the following panels for Krane:
- BOE TV101WUM-NL6
- AUO KD101N80-45NA
The edid info and init command are from:
https://crrev.com/c/1565758
BUG=b:129299873
BRANCH=none
TEST=Builds krane image and boots properly.
Change-Id: Id19c6c2b4c1c728c39aa26301adf7d6fb5046403
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Many devices in Kukui family will be using MIPI panels, which needs
hard-coded EDID and initialization commands. And because each device may
have its own layout and ID, there should be very few devices sharing
same panel configuration. As a result, we want to put panel data (EDID
and init commands) into board-specific modules, provided by
`get_panel_description` function.
The panel numeric ID is identified by ADC 2, and is currently available
as higher 4 bits of sku_id(). After ID is retrieved, the
get_panel_description should return a reference to the EDID and table of
init commands. The default implementation is to simply return NULL, and
the data for real devices should be provided by panel_*.c in further commits.
BUG=b:80501386,b:117254947
BRANCH=none
TEST=boot correctly on Kukui
Change-Id: I19213aee1ac0f69f42e73be9e5ab72394f412a01
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For systems with real MIPI panels (8173/oak was using PS8640 eDP
bridge), we have to send DCS commands to initialize panel.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the Atmel touchscreen ACPI node to use PRP0001 as
_HID to allow OF-style compatible string matching for enumeration.
Reason for this change: Atmel touchscreen driver in Linux kernel looks
for "compatible" property to decide if it is okay to attach to the
device. This check seems to be a protection against old firmware in
the field that do not have the right properties.
BUG=b:129162037
TEST=Verified that touchscreen works on Kohaku.
Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The default is DMIC0 on, but Kohaku is also using DMIC1
BUG=b:133282247
BRANCH=None
TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav
make sure 4 channels recording work
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SiFive's ZSBL has initialized flash, but only 16MB of space is available.
1. add code for spi
2. add code to map flash to memory spaces
Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Almost all platforms force it on. Make it enabled by
default but under user control to optionally disable it.
Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The Kohaku V24 schematic adds two additional temperature sensors
to the EC. Add these to the DPTF tables.
Cq-Depend: chromium:1742914
BRANCH=none
BUG=b:138578073
TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel.
1. Build EC
``cd ~/trunk/src/platform/ec``
``make -j BOARD=kohaku``
2. Program EC
``./util/flash_ec --board=kohaku``
3. Reboot device
4. Rebuild BIOS
``cd ~/trunk/src/third_party/coreboot``
``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge
vboot_reference libpayload coreboot-private-files intel-cmlfsp
coreboot-private-files-hatch coreboot chromeos-bootimage``
5. Use flashrom to program the BIOS
6. Reboot device
7. Log into the root console (ctrl-alt-F2 or servo)
8. Example thermal sensor information
``grep . /sys/class/thermal/t*/type``
Look for "TSR0" through "TSR3" in the output.
Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Oops, I missed this in the last CL.
The pin needs to be configured as owned by GPIO, so that the kernel
driver can bind it with an IRQ.
BUG=b:139165490
TEST=Ensure kernel nastygram about inability to claim the IRQ is gone
Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
HDA is not configured.
Enable SOC_INTEL_COMMON_BLOCK_HDA_VERB to configure the HDA using
cim_verb_data[] table.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: I9bb542091ad200833894431f5b840f48dd388173
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34655
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One case slipped past the review and rebase of 733c28fa42
(soc/intel/{cnl,icl}: Use new power-failure-state API).
Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pmc_soc_restore_power_failure() is only called from SMM, so add
`pmc.c` to the `smm` class. Once all platforms moved to the new
API, it can be implemented in a central place, avoiding the weak-
function trap.
Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'dual DSI mode' was never used by any real boards running coreboot
and is introducing lots of complexity when it comes to refactoring.
In order to create a common display stack for MTK SOCs, we want to first
drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more
similar to each other.
BUG=b:80501386,b:117254947
TEST=emerge-oak coreboot
Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Arcada.
Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There was the potential for misuse of the override early GPIO table,
because if the override early GPIO table did not have a corresponding
entry in the base table, it would not get overridden, and there was
no way to know except manual inspection (this has already happened
here), so now all hatch mainboards are required to explicitly list out
all of their required early GPIOs.
TEST=booted several hatch boards, verified that they can communicate
with TPM and successfully train memory
Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.
To execute:
$ qemu-system-aarch64 -M virt,secure=on,virtualization=on \
-cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic
Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The pinctrl driver in the linux kernel automatically turns off SCI
routing for all GPIOs exported via ACPI, so this patch sets up
dual-routing of the EMR_GARAGE_DET signal so that one can be used
for IRQs and one for the SCI wake.
Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touchscreen controller was never added to the device tree, and the
next board rev will have this IC connected. Set it up in the device tree
with conservative power resource timings from the datasheet.
BUG=b:138869702
BRANCH=none
TEST=compiles; current board rev does not have touch IC
Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enabling stylus pen device and pen_eject event.
- Adding enable_gpio for power sequencing
- Configuring GPP_H4 and GPP_H5 as native function
- Adding PENH device node for pen ejection event
BUG=b:137326841
BRANCH=none
TEST=Verified pen input operation and pen_eject event (pop-up and wake
from s0ix on pen ejection)
Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
FSP1.0 has low memory corruptions below CONFIG_RAMTOP
on S3 resume path, as romstage ram stack will be utilised
before there is a chance to make the necessary backup
to CBMEM.
Previously done for intel/minnowmax in commit b6fc727.
Change-Id: I2e128079b180f9978e8519b190648d516aaee0dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Vortininja needs different SAR values than meep. Use sku-id to load SAR values.
BUG=b:138261454
BRANCH=octopus
TEST=build and verified SAR values by sku id
Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add support for the integrated TPM in Kconfig and update device tree.
Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch makes SPKR_PA_EN PIN output and high for boot beep
to work in pre-os environment.
BUG=b:135104721
BRANCH=NONE
TEST=Boot Beep is working with required ALC1011 depthcharge code
changes.
Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen
T4 specification and resolve re-bind hid over i2c driver failed after
touchscreen firmware auto update.
BUG=b:132211627
TEST=Stress touchscreen firmware auto update 200 times and not found
re-bind driver failed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Allwinner code was never completed and lacks a driver to load
romstage from the bootblock.
Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values.
BUG=b:138091179
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on qemu-riscv:
Boots into Linux until initrd should be loaded.
Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
BRANCH=none
BUG=b:138152075
TEST=Build for cometlake board with the PmTimerDisabled policy in
devicetree set to 1.
With PmTimerDisabled = 0
>> iotools mmio_read8 0xfe0018fc
0x00
With PmTimerDisabled = 1
>> iotools mmio_read8 0xfe0018fc
0x02
Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines
whether the ACPI Timer is enabled to run.
- 0: ACPI Timer is enabled
- 1: ACPI Timer is disabled
Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Add rise time / fall time to I2C config in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
BUG=b:138258384
BRANCH=none
TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run
at 395-399 kHz.
Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Moving these to bootblock as we are seeing some instances where
devices are rebooting into the recovery broken screen with the 0x5a error (no
bootable storage device in system). This needed to be done for KBL
platforms and never got transferred to hatch.
Please reference https://review.coreboot.org/c/coreboot/+/23647
BUG=b:137681648
BRANCH=None
TEST=Run autotest faft_bios and faft_ec suites
Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=133345634
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Hatch.
Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a user selectable option to enable all WiFi SAR
configs that apply to hatch.
BUG=b:138177048
Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The virt machine is special as it doesn't emulate flash and it puts
the coreboot.rom at start of DRAM. The payload loader doesn't know
about CBFS in DRAM and overwrites the CBFS while decompressing
payloads, resulting in undefined behaviour.
Mark the region as SRAM to make sure the payload won't
overwrite the CBFS while decompressing.
As payload is always decompressed to DRAM, it wouldn't touch
SRAM memory regions.
Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Fix regression introduced in bd4bcab
"lib: Rewrite qemu-armv7 ramdetect".
The detected DRAM size is in MiB, thus needs to adjusted accordingly
before passed to ram_resource.
Wasn't seen earlier as everything works, except payload loading.
Change-Id: I4931372f530e7b4e453a01e5595d15d95a544803
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The build directory might not exist in the src dir.
BUG=b:112267918
TEST=make what-jenkins-does
Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv
Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.
Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add VBT 8.0.1038 binary.
Panel #10 is modified to support the 1200x1920 LCD panel.
This panel is configured as default.
LCD and HDMI are working fine.
BUG=N/A
TEST=booting Facebook FBG1701
Change-Id: If327e4e071df61b02fcec45213c2b700320ef269
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Also don't define the default as this result in spurious lines in the
.config.
This also cleans up an unused Kconfig file.
In the generated config.h CPU_QEMU_POWER8 is gone as expected and
ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same.
Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on updated schematics, change polarity of USI_INT, and add
the reset and enable GPIOs to the touchscreen ACPI node. The stop
GPIO can't be used with the current implementation of _ON, as the
way it's wired will cause power sequencing to fail.
BUG=b:137133194, b:138240502
BRANCH=none
TEST=Compiles, don't have next board rev to test with
Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Remove old hda_verb.c code copied from intel/kblrvp7, as it's
been superseded by the common block HDA implementation.
Fixes a null pointer error preventing the HDA codecs from being
initialized, as found in Coverity CID 1403651.
Test: build/boot Librem 13v2, verify functional audio
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable I2C0 in fleex then verify EMR function successfully
BUG=b:135968368
BRANCH=octopus
TEST=EMR function working normally with I2C0 in Grob360S.
Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The 'Jacuzzi' is a different base board that will share most of Kukui
design. For AP firmware, there will be only a few changes expected,
mostly in display (for MIPI bridge) and EC/keyboard so we want to create
it as variants inside Kukui folder, not forking a new directory.
BUG=b:137517228
TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build.
Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is based on the grunt variant.
BUG=b:135551210
BRANCH=none
TEST=emerge-grunt coreboot chromeos-bootimage
Ensure that image-treeya.*.bin are created
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change provides an implementation of variant_devtree_update() for
kindred that disable eMMC controller when SKU ID = 1 or 3
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1 or 3
Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We would like to wake eve up in suspend from an MKBP event. This commit
simply enables MKBP events to wake the system in suspend using the
existing host event interface. There is an accompanying series of
patches in the EC firmware for eve that will allow a MKBP wake mask to
be configured.
BUG=chromium:786721
BRANCH=firmware-eve-9584.B
TEST=Build and flash eve, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC ID of the ECDT needs to be null-terminated (see ACPI specification,
section 5.2.15), which currently isn't being done due to an off-by-one
error. strncpy() is bug-prone exactly because of issues like this, so just
skip it entirely and use memcpy() instead.
Change-Id: I0b62e1f32177c9768fa978053ab26bca93d7248d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Disable unused USB devices in the device tree so that the concerned ACPI
objects do not get exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based
on port status and the concerned ACPI objects are not exported.
Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add devicetree configuration for USB devices so that USB Port
Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects
can be exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are
exported for the configured USB devices in the SSDT table.
Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We would like to wake nocturne up in suspend from an MKBP event. On
Nocturne, MKBP events are notified to the host via a GPIO from the EC,
EC_INT_L. However, the AP cannot wake from suspend from this GPIO.
Therefore, we'll use the host event interface to wake the system
instead.
This commit simply enables MKBP events to wake the system in suspend.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
