Commit Graph

924 Commits

Author SHA1 Message Date
Tim Wawrzynczak fb1858539f Revert "src/mainboard: Add Star Labs labtop series"
This reverts commit 2e665eb8da.

Reason for revert: Was submitted too early and out-of-order.

Change-Id: I119b7a81b849bbe3424d73d5fdf9b55481444686
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-04 18:52:32 +00:00
Sean Rhodes 2e665eb8da src/mainboard: Add Star Labs labtop series
Add support for LabTop Mk III (kblr) and LabTop Mk IV (cml)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iffa6061b0e600880b0c93746f35b1731e4841e31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-04 17:21:21 +00:00
Arthur Heymans 098f1fa802 Documentation/community: Add link to the OSF Slack
We are also present on Slack so advertise that.

Change-Id: I7d9887e524e47e6f42a5013e9f696881ef54a631
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-06-01 06:05:08 +00:00
Patrick Georgi a539817b1d Documentation/community: Add Discord to forums
Change-Id: Ib1d866ecf041ddc4aaf508d290a3e31b9a108cf2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-06-01 06:04:57 +00:00
Patrick Georgi 71099258cc Documentation: Fix up toctree
Some files weren't properly hooked up, making Sphinx complain.

Change-Id: If959fa63d4ddbc3916c49c5ad6602e76b12a7e60
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55020
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28 17:58:06 +00:00
Patrick Georgi 5a45c41782 Documentation: Fix named link
The syntax requires two bracketed fields.

Change-Id: I98ebe714e57f50017755eed7888f0dd2637a3066
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-28 17:58:01 +00:00
Patrick Georgi 34d5f9130e Documentation: Update real time chat options
Change-Id: I3035266c5e035b954c0d709bd2c09069128c3340
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55010
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-28 11:44:34 +00:00
Angel Pons 9bc780fc9f option: Allow mainboards to implement the API
Some mainboards need a mainboard-specific mechanism to access option
values. Allow mainboards to implement the option API. Also, add some
documentation about the current option API, and describe when should
one reimplement the option API in mainboard code: only when the code
is mainboard-specific to comply with externally-imposed constraints.

Change-Id: Idccdb9a008b1ebb89821961659f27b1c0b17d29c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-28 11:37:25 +00:00
Angel Pons 76619b01c8 Doc/releases: Mention that Asus H61 boards got squashed
Not physically squashed, the coreboot code got turned into a variant
setup with override devicetrees to drop redundant boilerplate.

Change-Id: I7ae5530d2603d6d108ef3829004de7e1cad130f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-05-20 21:11:14 +00:00
Paul Fagerburg de6cbac3c4 tests: improve code coverage support
Fix the exclusion path for lcov; it should exclude the directory
with source code, not object files.

Use the COV environment variable to
* control whether we build for coverage or not
* select the output directory

Add a separate target for generating the report, so we can get a
report for all of the tests together or just a single test.

Add documentation.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I2bd2bfdedfab291aabeaa968c10b17e9b61c9c0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2021-05-19 19:56:02 +00:00
Patrick Georgi 69f0df2c54 Documentation/gerrit: Describe core developer responsibilities
Change-Id: I8885e9fb401838229ead72b97394f3e2343aabed
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-05-17 22:20:44 +00:00
Paul Menzel 1e66479e93 Documentation/distributions: List System76
Copy the text from the [Web site](https://coreboot.org/users.html).

Change-Id: I805f558514eb50580b5bd79bd4f964e66a15158d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-16 21:56:15 +00:00
Paul Menzel 1b242b6618 Documentation/distributions: Order vendor list lexicographically
Change-Id: Id1f27d68124de745ff0eaad669ee86ce0b57ec09
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-05-14 10:16:48 +00:00
Paul Menzel 6415d9bffc Documentation/distributions: Separate all vendors by exactly one blank line
Change-Id: Ib1718dfa174e2a4e9c2c4b5564e196e8483a8f3c
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-14 10:16:45 +00:00
Paul Menzel 6cb9188683 Documentation/distributions: Separate parenthesis by dashes
Change-Id: I5d6095c6d8423e3a67f027f23d4c00dcb34a50cb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-14 10:16:39 +00:00
Matt DeVillier d3b49b4cda payloads/Tianocore: Update default build target, simplify build options
Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
option since it applied only to CorebootPayloadPkg. Clean up the Makefile now
that we're only building from a single Tianocore package/target.

Test: build/boot qemu Q35 target with both UefiPayload and Upstream options.

Change-Id: If545fbd0c30be6dcc6ff43107b80980fa23a527e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54019
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-13 08:30:57 +00:00
Angel Pons 918e5352b7 Doc/nb/intel/sandybridge: Fix up some typos and cosmetics
Change-Id: I23b0c94ec9881aef8e39a14bc048856a65a6286d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-05-12 08:01:00 +00:00
Patrick Georgi 5d24231427 Documentation/releases: Add more details about release notes
There are some steps when updating the release notes that are easily
missed (see: I missed them for 4.14), so document them.

Change-Id: Icdb69eb74f8dd3a7189eb8803b0259c4e6a31f96
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:41:03 +00:00
Patrick Georgi 6aa3238dc1 Documentation/releases: Add 4.15 release notes template
Change-Id: I52bd1ee6b297ba08e335f5c65941b09f14689a00
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:34 +00:00
Patrick Georgi 970ebd67a5 Documentation/releases: Update checklist
Since we want commits to go through 24 hours of review, move the
vboot list update a week earlier. Also point more directly at the
right script to execute.

Change-Id: I49e6dfe22894402d5a0526588f8a04595ac88862
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:20 +00:00
Patrick Georgi 67a5b4573c Documentation: Update vboot support list
Created by util/vboot_list/vboot_list.sh

Change-Id: I49536c26540c0fd1940a32f588fa49afb55b108a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-12 07:40:14 +00:00
Michael Niewöhner 2765275467 docs: add recommendation for gpios regarding soft straps
Soft straps, that can be configured by the vendor in the Intel Flash
Image Tool (FIT), can influence some pads' default state. It is possible
to select either a native function or GPIO mode for some pads on
non-server SoCs, while on server SoCs most pads can be controlled.

Thus, add a recommendation to always configure all pads for a board to
guarantee integrity between different board or vendor firmware revisions
where the soft straps might have been changed.

Change-Id: I33063a3f6a1c9cd5267d85f7da84deb554489a26
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-11 17:28:07 +00:00
Michael Niewöhner 6d2fbba0ed docs: correct and rewrite documentation regarding n/c / unused pads
Intel PDGs starting from Skylake / Sunrise Point state that, different
from the general recommendation in digital electronics, unconnected
GPIOs defaulting to GPIO mode do explicitly not require termination.

The reason for this is, that these GPIOs have the `GPIORXDIS` bit set,
which effectively disconnects the pad from the internal logic by
disabling the input buffer.

This bit - besides `GPIOTXDIS` - can also be set explicitly by using
the gpio macro `PAD_NC(pad, NONE)`.

In some cases, a pull resistor may be required due to bad board design
or when a vendor sets the RX/TX disable bits together with a pull
resistor and schematics are not available to check if the pad is really
unconnected or just unused. In this case the pull resistor should be
kept.

Pads defaulting to native functions usually don't need special handling.
However, when pads requiring external pull-ups are missing these due to
bad board design, they should be configured with `PAD_NC` to disconnect
them internally.

Rewrite the documentation to reflect these new findings.

Also clarify the comment in soc/intel gpio code accordingly.

Change-Id: Id01b197ebe8f2b8bb4ecf3d119ec2298b26d9be0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52139
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-11 13:14:53 +00:00
Patrick Georgi a0aee78c82 Documentation/releases: Fill in coreboot 4.14 release notes
Change-Id: I79530c91424112247e485a5a41debc666e0072d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10 20:32:07 +00:00
Jonathan Zhang 206dfbf173 doc/relnotes/4.14: add Intel Xeon-SP support status change
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ibead1c75bb4e41fedc2799366b5b006d76fc8f4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52735
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-10 20:31:19 +00:00
Kyösti Mälkki 8618cf1edc doc/releases/coreboot-4.14: Add x86 bootblock and ACPI GNVS changes
Change-Id: Ifa58a9ac7c6dcc391cd9942295319a8677cd4492
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-05-10 19:56:58 +00:00
Patrick Georgi 9b330fafeb Documentation/gerrit: Document our Gerrit user roles and procedures
Document the roles we have on review.coreboot.org, the expectations
associated with them, and how to become part of any of these groups.

Change-Id: Ib31083f5a07bd89efd13ecd6aaf34a69d438d59d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52265
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-09 16:23:43 +00:00
Felix Held 07eb01bc02 doc/releases/coreboot-4.14: add AMD SoC cleanup and Cezanne addition
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I72a9056edfddb4e2cd2e6412cb5ea72cf965f9c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53924
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-08 19:35:40 +00:00
Tony Huang 1282b007be drivers/i2c/generic: Set S0W to D3hot for wake device
If device is supported as a wake source, _S0W should be set to D3hot.
This ensures that the device is put into D3hot by the OSPM.

Power resource(PRIC) for the device is listed in both _PR0 and _PR3. Thus, it ensures that the OSPM does not turn off power resource when device is put into D0 and D3hot. Hence, it is capable of waking the system from D3hot state. However, if it is put into D3cold, then the power resource is turned off by the OSPM.

The devices we are currently looking at for touchscreen/touchpad
do not really support auxiliary power and so do not support wake from D3cold.

BUG=b:186070097
TEST=build and check device wake state _S0W set to 3 in ssdt table.

Change-Id: I34e4b2350875530d3337be700276bcc4fb1f810a
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-05 01:16:29 +00:00
Tim Wawrzynczak 13e240c602 util/sconfig: Add support for discontiguous FW_CONFIG fields
Sooner or later, some board was going to need extra FW_CONFIG bits for
a field that was already in production, so this patch adds support for
adding extra (unused) bits to a field.

The extra are appended via a syntax like:
`field FIELD_NAME START0 END0 | START1 END1 | START2 END2 ...`
and the suffixed bits are all treated as if they are contiguous when
defining option values.

BUG=b:185190978
TEST=Modified volteer fw_config to the following:
field AUDIO 8 10 | 29 29 | 31 31
        option NONE 0
	option MAX98357_ALC5682I_I2S 1
        option MAX98373_ALC5682I_I2S 2
	option MAX98373_ALC5682_SNDW 3
        option MAX98373_ALC5682I_I2S_UP4 4
        option MAX98360_ALC5682I_I2S 5
        option RT1011_ALC5682I_I2S 6
        option AUDIO_FOO 7
	option AUDIO_BAR 8
        option AUDIO_QUUX 9
        option AUDIO_BLAH1 10
        option AUDIO_BLAH2 15
        option AUDIO_BLAH3 16
        option AUDIO_BLAH4 31
end

which yielded (in static_fw_config.h):
 FW_CONFIG_FIELD_AUDIO_MASK 0xa0000700
 FW_CONFIG_FIELD_AUDIO_OPTION_NONE_VALUE 0x0
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98357_ALC5682I_I2S_VALUE 0x100
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_VALUE 0x200
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682_SNDW_VALUE 0x300
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98373_ALC5682I_I2S_UP4_VALUE 0x400
 FW_CONFIG_FIELD_AUDIO_OPTION_MAX98360_ALC5682I_I2S_VALUE 0x500
 FW_CONFIG_FIELD_AUDIO_OPTION_RT1011_ALC5682I_I2S_VALUE 0x600
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE 0x700
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE 0x20000000
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_QUUX_VALUE 0x20000100
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH1_VALUE 0x20000200
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH2_VALUE 0x20000700
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH3_VALUE 0x80000000
 FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH4_VALUE 0xa0000700

Change-Id: I5ed76706347ee9642198efc77139abdc3af1b8a6
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52747
Reviewed-by: Duncan Laurie <duncan@iceblink.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:40:57 +00:00
Michael Niewöhner f3e82459a8 docs/mb/supermicro/x11ssm-f: rework flashing section
The board can be flashed without adding a diode by just leaving VCC
unconnected. Rework the flashing section to describes that.

Change-Id: I37d55ffdbcfba4f3a1113a82f16ec8766bbb6e6c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-29 05:23:38 +00:00
Stefan Ott dc77bc0546 mb/asus/p5q: Document working fan control and FireWire port
Fan control and FireWire work fine on my board.

Signed-off-by: Stefan Ott <stefan@ott.net>
Change-Id: Idc69e902370c4094daef93e843abc6ae564625f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-28 09:56:06 +00:00
Tim Crawford 109c4d05d6 mb/system76/oryp6: Add System76 Oryx Pro 6
https://tech-docs.system76.com/models/oryp6/README.html

Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe
- M.2 SATA
- MicroSD card slot
- All USB ports
- Integrated graphics using Intel GOP driver
- Webcam
- Ethernet
- Internal microphone
- Combined headphone + mic 3.5mm jack
- Combined microphone + S/PDIF 3.5mm jack
- Booting to Ubuntu Linux 20.10 and Windows 10
- Flashing with flashrom

Not working:

- S3 suspend/resume: System hangs on wake from S3
- Discrete/Hybrid graphics: Requires a new driver
- Internal speakers: Enabled in separate patch

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 20:45:50 +00:00
Furquan Shaikh 66ab5eb521 [RFC] Address the leftover TODO in soc/intel/cannonlake
Change-Id: I4c989de4d2af3e810fb0e4803d0fa2396917d93e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50829
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16 17:42:12 +00:00
Patrick Georgi 69cb494749 Documentation: List the leadership meeting as one of our forums
Change-Id: I00822cc631c5451862bd94683ff45289ecc75679
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Dabros <jsd@semihalf.com>
2021-04-15 19:11:01 +00:00
Ravi Kumar Bokka 0c9eb31533 sc7280: Provide initial SoC support
BUG=b:182963902
TEST=Validated on qualcomm sc7280 developement board

Change-Id: I1fc841b3113f2bf79b8376cd1ccdb671c53c2084
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-04-15 19:07:26 +00:00
Jonathan Zhang e73bae7b0a Documentation/mb/ocp: Update Delta Lake documentation
Update OCP Delta Lake documentation following OSF (Open System Firmware)
solution reaching DVT exit parity. This alternative host firmware
solution uses FSP/coreboot/Linuxboot stack.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd6ab251cd7806cf8cd3f984ad88c091f85035cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-04-15 07:37:46 +00:00
Piotr Szymaniak 5b5b8afdf1 Docs/mb/lenovo/t420: List working, tested and non-working features
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: I6fb4a8da44125b4280d37d0cf7c372f8024fb2d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-06 06:47:29 +00:00
Michael Niewöhner 0887fc4dbc docs/mb/supermicro: add SUM tool for flashing with disabled ME
Change-Id: I08543c0908a6cb4ef9fb46d0eb3a7aa481fb95d9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49887
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-03 20:25:44 +00:00
Matt DeVillier fcb68f31b6 mb/purism/librem_14: Move/fix touchpad interrupt GPIO
On production boards, the touchpad interrupt line was moved
from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry,
and update documentation to remove touchpad config issue.

Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:05:57 +00:00
Matt DeVillier 385667f679 documentation: Add documentation for Purism Librem 14
Change-Id: Ic68a3d17534f78dae8c432253982e8d10a6427f0
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:05:51 +00:00
Julius Werner 4dd857723b Documentation/coding_style: Issues not mentioned and cleanup patches
This patch adds a bit of a "preamble" to the coding style to provide
guideance on how it should be applied and how style questions that
aren't mentioned should be handled.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I88efd5f1006bd1fd82cea14ea65422d9958dc197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-26 05:09:40 +00:00
Tim Crawford 427487b173 mb/system76/gaze15: Add System76 Gazelle 15
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10

Not working:

- Discrete/Hybrid graphics

This requires a new driver to work correctly, which will be added and
enabled later.

Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 07:53:40 +00:00
Julius Werner 698b05fdd5 Documentation/coding_style: Add more details on include-ordering
This patch is trying to address some of the concerns raised in CB:50247
after the patch had landed. The preference for alphabetized headers was
just supposed to discourage leaving headers completely unordered, and
wasn't intended to disallow other intentional include orderings such as
grouping local includes after system ones or specific ordering
constraints that exist for technical reasons. This patch adds a few more
sentences to try to clarify that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6825f4a57613fabb88a00ae46679b4774ef7110b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-22 11:30:13 +00:00
Jakub Czapiga 61fcb7e965 acpi/acpigen.h: Add more intuitive AML package closing functions
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22 11:21:55 +00:00
Kevin Chiu 4490689d88 google/trogdor: Add new variant Marzipan
This patch adds a new variant called Marzipan that is identical to Lazor
for now.

BUG=b:182181519,b:182018606
BRANCH=master
TEST=make

Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:31:06 +00:00
Angel Pons da12ca98c9 doc/mb/lenovo/montevina: Update link within page
Commit c4aa24fc12 (doc/mb/lenovo/montevina: Clarify use of bincfg)
renamed a section, and the link referencing it by its old title no
longer works. Update the link, and remove the `a completely new one`
part from it as well, for consistency with the aforementioned commit.

Change-Id: I22e8b3237dafb3397bc901804a57e905f806839d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-19 12:46:06 +00:00
Patrick Georgi ce9b26cdd5 Documentation/releases: Add note about CBFS stage format change
Change-Id: I2e4f1d1551141c6225e762631e52d71357112425
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-18 08:21:02 +00:00
Patrick Georgi a763e8f92b Documentation: Describe the site-local hook in our config/build system
Change-Id: Ia682b784540fa82e1f216f76d87d59a4f0b94486
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51546
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17 23:07:07 +00:00
Furquan Shaikh 82dcd5b9ba Documentation: Add deprecation notice for SAR support in VPD
This change updates the release notes for coreboot-4.14 to add
deprecation notice for SAR support in VPD for Chrome OS platforms.

BUG=b:173465272

Change-Id: If6d511a22a3a2a31671dac91e57e801134d4ecf8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51486
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17 07:56:39 +00:00
Alexander Couzens 1295fa218f mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-F
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15 09:45:23 +00:00
Nico Huber 3b14a5f92a doc/mb/lenovo/montevina: Fix constants for 16MiB flash
The current values are actually for 32MiB and result in a brick if used
with a 16MiB chip because of the invalid bios region.

Change-Id: I08337394ce0d6e31e5c03cda2bfb3b9f0282f2c3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51322
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14 16:35:37 +00:00
Dmitry Torokhov 39c1b4f951 Documentation/acpi: switch example from edge to level interrupts
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.

Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.

Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-11 22:38:52 +00:00
Nico Huber c4aa24fc12 doc/mb/lenovo/montevina: Clarify use of bincfg
`bincfg` is not creating anything new, it just converts
from text to binary.

Change-Id: I14e67ee8bc449d171a951f6edeaa9f9d0c04dbe1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51319
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-07 13:59:23 +00:00
xuxinxiong 9a446bdf07 mb/google/trogdor: Add new configs homestar
New boards introduced to trogodor family.

BUG=b:180668002
BRANCH=none
TEST=make

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: If0f9b6c89198a882acae7191d08b166eb8c1dd71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-02-26 01:37:40 +00:00
Johnny Lin aed1952f05 doc/mb/ocp: Update DeltaLake for VPD variables used in LinuxBoot
u-root commits:
bmc_bootorder_override
https://github.com/u-root/u-root/pull/1902
systemboot_log_level:
https://github.com/u-root/u-root/pull/1922

Change-Id: I3da7291188ee06c50008aa3fc7142210215044d4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-02-24 11:27:43 +00:00
Angel Pons 83e6c15b0e Doc/releases/checklist.md: Clarify tag push command
Change-Id: I0a6d1ed014c6454c4bde390283351c19fe097201
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-23 17:25:59 +00:00
Alexey Vazhnov 63b87e985c Document Gigabyte GA-G41M-ES2L
To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l

+ configs/config.gigabyte_ga-g41m-es2l
+ lshw output examples
+ memory modules compatibility

Tested in Devuan 4 Chimaera.
Tested from exact steps from this documentation.

Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2021-02-22 07:21:30 +00:00
Alexey Vazhnov f595984043 Documentation: move `coding_style.md` inside contributing/
Keep less files in the root directory.

Change-Id: I9eebd0b0826181340ead41af5284362d1cca09d7
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-02-22 07:20:59 +00:00
Martin Roth 5c7341331d treewide: Remove trailing whitespace
Remove trailing whitespace in files that aren't typically checked.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I8dfffbdeaadfa694fef0404719643803df601065
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-17 17:30:05 +00:00
Paul Menzel c4062c78a9 device: Add unit to Kconfig option name: `PRE_GRAPHICS_DELAY_MS`
It’s good practice to put the unit into the name.

Change-Id: I1493f61d4e495c22f09abf1829bb2eab9b1fd2b6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-02-15 17:05:18 +00:00
Evgeny Zinoviev b08543a640 Doc/mb/lenovo/montevina_series: Use Makefile to generate IFD
util/bincfg's Makefile already has target that generates flash
descriptor. Use it instead.

Change-Id: I1756514e1ab7b64de23a98314d8a32e9258e648c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-09 07:48:13 +00:00
Evgeny Zinoviev d2b3961fdc Documentation: Use correct KiB/MiB units instead of KB/MB
Fix a common mistake of using KB/MB where KiB/MiB is what actually is meant.

1 MB = (10^3)^2 = 1000000
1 MiB = (2^10)^2 = 1048576

Change-Id: I78327652b6c6526318071a9d4bafd7ec279ea614
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-09 07:47:41 +00:00
Julius Werner ca935d1107 Documentation: Codify some guidelines for headers and chain-including
There has been some repeated discussion about how header includes should
be formatted, specifically on the topic of chain-including. The coding
style currently doesn't say anything about the topic but clearly people
have some basic assumptions. This patch tries to codify some common
ground rules that are supposed to reflect the existing practice.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ibbcde306a814f52b3a41b58c7a33bdd99b0187e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-06 09:08:04 +00:00
Martin Roth 064b250fac Update util.md documentation
This is the new output of the util_readme.sh script.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia46924474f75692192ef4b52aab714f5071f9534
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48966
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-28 20:17:11 +00:00
Tim Crawford fdc8fd3602 mb/system76/oryp5: Add System76 Oryx Pro 5
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics
- Internal microphone
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux and Windows

Not working:

- Discrete/Hybrid graphics
- Internal speakers

These two require new drivers to work correctly, which will be added and
enabled later.

Change-Id: Iae6e530dcd52df3642cdfe74b65bfff5aa0dd402
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-28 09:15:00 +00:00
Martin Roth 2cee2ff256 Documentation: Add documentation on jenkins builders
Put this in a new directory called 'infrastructure' and make a link
and an index.md file for the directory.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I54a0204e7525a25f2fd717a73007b304aac67396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-25 08:56:27 +00:00
Angel Pons 0ec903a73b Doc/mb/lenovo/Sandy_Bridge_series.md: Clarify installation
Unlike Ivy Bridge series, there isn't a method to flash coreboot
internally when running vendor firmware (yet). Until someone finds a way
to bypass flash protections, the first flash has to be done externally.

Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-24 23:21:23 +00:00
Angel Pons 76943a3443 Doc/mb/lenovo: Correct typo
Change-Id: If31c59f21c5533d8b5b015c9e60edd6e4e7072e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-24 23:21:17 +00:00
Michael Niewöhner d509ee55b6 soc/intel/apl: drop LPC pad configuration code
Drop LPC pad configuration code since all boards now do pad
configuration on their own. The comment about LPC_CLKRUNB when using
eSPI is moved to `Documentation/getting_started/gpio.md`.

Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23 09:23:23 +00:00
Patrick Rudolph 6279cabb5b Documentation: Fix toctree and remove dead links
Change-Id: Ie3c7c33096f60a5aa476ff55c538fe68ffadc068
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:36 +00:00
Patrick Rudolph fc1d50a365 Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.

The bugs are so strange that no root cause could be found yet.

Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-12 13:36:30 +00:00
Sam Lewis 1c18f8679f Documentation: Add Beaglebone Black documentation
Change-Id: If1a9808d1f20ee61048182d416f25e9a81c631af
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-24 08:30:28 +00:00
Angel Pons 9223b71a4c Doc/mb/lenovo: Explain simpler GM45 flash method first
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.

Also, reword a sentence on the simple flashing procedure for clarity.

Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:33 +00:00
Angel Pons d0fd7b0693 Doc/mainboard: Sort Lenovo laptop generation groups
GM45 is older than Arrandale, so swap their order.

Change-Id: I5b94d940c0378dd561535257d3352700fd482527
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
2020-12-14 08:17:27 +00:00
Furquan Shaikh 339269d587 Docs/cbfstool: Add details about memory mapped window handling
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.

BUG=b:171534504

Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-11 01:11:16 +00:00
Jonathan Zhang 36854a831e Documentation/mainboard/ocp: Update DeltaLake
DeltaLake Open System Firmware stack (FSP/coreboot/Linuxboot) has
reached EVT exit parity. Update the documentation accordingly.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I7cce855d207a53b1d3cd497b74cdc0b00027a3ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-05 09:47:00 +00:00
Michael Niewöhner 43dd2e458f docs/mb/supermicro/x11-lga-series: Update documentation
- Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726
- Add missing reference to X11SSH-F
- Drop TODO reference; there are no TODOs left

Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-27 20:49:16 +00:00
Michael Niewöhner 4c56d79ba6 {docs/,}mb/supermicro/x11ssh-tf: drop TODO section
Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.

Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:49:04 +00:00
Michael Niewöhner ce04a42db9 docs/mb/supermicro/x11ssm-f: Update board documentation
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
  function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
  whole paragraph. Also add a note about flashing via the BMC web
  interface.

Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-11-27 20:48:55 +00:00
Paul Menzel 9226fe9aee Documentation: Mention newer Intel μ-code updates in 4.13 release notes
Start a new section *Notes* for these kind of information.

Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:21:29 +00:00
Angel Pons c930c87998 Doc/releases/checklist.md: Fix up URLs
Use angle brackets so that they appear as links, and update a link to a
Gerrit change to use the current format.

Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:58 +00:00
Angel Pons 5ea7bb74bd Doc/releases/checklist.md: Add reminder to unpack relnotes
Explicitly add this easy-to-forget step. Also add a missing period.

Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-22 22:19:48 +00:00
Maxim Polyakov 0fcd37172f mb/kontron: Add Kontron mAL10 COMe module support
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.

Working:
  - UART console and I2C on Kontron kempld;
  - USB2/3
  - Ethernet controller
  - eMMC
  - SATA
  - PCIe ports
  - IGD/DP
  - SMBus
  - HWM

Not tested:
  - IGD/LVDS
  - SDIO

TODO:
  - HDA (codec IDT 92HD73C1X5, currently disabled)

Tested payloads:
  - SeaBIOS
  - Tianocore, UEFIPayload - without video, EFI-shell in console only

Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)

Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-22 22:18:22 +00:00
Angel Pons 5c186c6777 Documentation/releases: Update for 4.13
Fill in some blanks for 4.13, mark it done, add template for 4.14.
Also update the list of vboot supported boards.

Change-Id: Ie593efe515136a3b06620db6f0dbe3da00df7e9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-20 12:01:35 +00:00
Felix Singer d959a20114 mb/clevo/kbl-u: Add Clevo N130WU/N131WU
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3

WIP:
- Documentation

Not working:
- EC ACPI (e.g. Fn keys, battery and power information)

Boots Arch Linux (Linux 5.8.12) successfully.

Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-20 11:57:11 +00:00
Angel Pons 27f606b721 doc/relnotes/4.13: Remove duplicated `CPU`
Change-Id: Ib423a0d4341560301138e06b00a704c2baae4867
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47767
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 17:13:22 +00:00
Nico Huber 2421b88381 doc/relnotes/4.13: Fix random spelling mistakes
Change-Id: I7486124fbe43f15bfbbf0875a58935133639b35f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:32:13 +00:00
Furquan Shaikh a8e7b45816 Doc/relnotes/4.13: Add details about resource allocator v4
This change adds details about the new resource allocator v4 in
coreboot to the release notes for 4.13.

Change-Id: I7071bdf0faffda61fc5941886c963181939c07e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-19 16:23:46 +00:00
Nico Huber 900c3a32a3 doc/relnotes/4.13: Add changes to log-level configurability
Change-Id: Ia7ef57d20ea5099f344ccbf58d76597cb0e82c85
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47669
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 16:22:23 +00:00
Felix Singer 1268d4081e doc/relnotes/4.13: Add note about PCI bus mastering Kconfig options
Change-Id: I66a636f554d18e08a209a7cfd6a59cf13a88f2e1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47409
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-19 13:23:30 +00:00
Angel Pons 9fe0615ecc Doc/relnotes/4.13: Add several relevant changes
While some of these have little impact, they are worth mentioning here.

Change-Id: Idbf629ae77b8918ff1d93edb7b6c4669bbbe17df
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-13 16:11:48 +00:00
Julius Werner 9c50462fd7 Delete mainboard/google/cheza
Work on this mainboard was abandoned and never finished. It's not really
usable in its current state, so let's get rid of it.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4cd2e2cd0ee69d9846472653a942fa074e2b924d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-12 01:43:09 +00:00
Harshit Sharma 678e401eb8 Documentation/releases: Add ASan to 4.13 relnotes
Change-Id: I2953729c69dfcfa8b34192b3e1623fdfad87ca3a
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45118
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-11 10:28:05 +00:00
Iru Cai 85d0e7611a mb/hp: Add HP EliteBook Folio 9480m
The code is based on autoport, with necessary modifications.

This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.

Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.

Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-10 06:16:05 +00:00
Iru Cai 136380fcac Documentation: Introduce HP Sure Start and the method to bypass it
Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45577
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 10:38:32 +00:00
Matt DeVillier 12d515dcc5 mb/purism/librem_cnl: Add new variant 'Librem Mini v2'
Add Kconfig entries, and update existing documentation to
accomodate both v1/v2 versions of the board.

Change-Id: I856bb914941211cfbec4fed871ba2a5a038e23c3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46984
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09 07:48:23 +00:00
Matt DeVillier 184c794086 docs/librem_mini: update CPU, known issues section
Both 8565U and 8665U CPUs are used in the Librem Mini.

SATA issue updated based on addition of HSIO PHY tuning params
and resulting changes.

Change-Id: I33a093ccfea077402e1b3651f9ca5d6d8a2818f8
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-31 21:46:06 +00:00
Tim Wawrzynczak 24b4af668b fw_config: Convert fw_config to a 64-bit field
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.

BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 15:24:52 +00:00
Patrick Georgi 6065f616eb .gitignore: Split into subdirectory files
There's no need for the global list of files to ignore, so use git's
ability to work with more local configuration.

Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30 07:05:27 +00:00
Patrick Rudolph bc744f5893 drivers/smmstore: Implement SMMSTORE version 2
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.

Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
  memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
  returns error or success in registers.
* Returns an error if the requested operation would overflow the
  communication buffer.

Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.

The implementation has been tested against EDK2 master.

An example EDK2 implementation can be found here:
eb1127744a

Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-10-22 12:29:47 +00:00
Bill XIE 14ee0f94f3 mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20 09:00:18 +00:00
Paul Menzel b9a5152cfa Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:59 +00:00
Duncan Laurie 2cc126be2c drivers/intel/usb4: Add driver for USB4 retimer device
The USB4 retimer device needs to declare a _DSM with specific functions
that allow for GPIO control to turn off the power when an external
device is not connected.  This driver allows the mainboard to provide
the GPIO that is connected to the power control.

BUG=b:156957424

Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:51:40 +00:00
Iru Cai 871f62c376 lenovo/t440p: Add HDA verbs from the OEM firmware
To get the HDA verbs from the OEM firmware, open the firmware with
UEFITool, search for the existing HDA verbs, extract the UEFI module
and look for the verbs. Copy the consecutive 4 dword sets that look
like HDA verbs.

It is tested to make audio output from both the speaker and headphone
work.

Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30 10:13:48 +00:00
Jonathan Zhang 339fa7389b doc/mb/ocp: update deltalake server documentation
Upon completion of 2nd build/test/release cycle of Deltalake server
alternative firmware engineering, update the document.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1806526bd477ed407bb7fd36c7fe4ce0e57b72f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-09-28 09:37:57 +00:00
Christian Walter 90b0d85e73 Documentation/mainboard: Add Missing OCP Delta Lake Link
Change-Id: I379d6a7b72a0398c34ea8eeda09ccd663fc372ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-28 09:32:50 +00:00
Elyes HAOUAS 3f56b87c51 Documentation/getting_started/kconfig.md: Add a note about Kconfig defaults
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.

Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-25 08:41:45 +00:00
Harshit Sharma d8a722cb61 Documentation: Add ASan documentation
Change-Id: I710ea495798597189941620c7e48fd5aa7476781
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-09-21 07:45:37 +00:00
Bob Moragues c06c0ce559 strongbad / coachz : Add Initial Support
BUG=b:162409909
BUG=b:164196066
BRANCH=NONE
TEST=Verify build of strongbad target

Signed-off-by: Bob Moragues <moragues@chromium.org>
Change-Id: If83bd2c8f25fdd3c9625f40121e55c3c922a66fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45276
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-11 22:32:34 +00:00
Rob Barnes b2545cc3c6 soc/amd/picasso: Move APCB generation out of picasso
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.

BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
     Build and boot ezkinil

Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-10 20:26:03 +00:00
Patrick Georgi 4ad85ed156 Documentation: Discuss how we use language
Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-08-31 20:23:22 +00:00
Patrick Rudolph e828663392 Documentation: Update release notes for x86_64
Change-Id: I7d8d39bde3b3364ff6ce93030aa2bab34598acd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-31 17:08:58 +00:00
Angel Pons 85a4463976 Doc/soc/intel: Add info about microcode updates
Document a general overview of when and how microcode should be updated.
Also explain what microcode updates are, and why they are required.

Change-Id: I6dbe25122fa45a416ed64180ef1bfb11afe676ba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44400
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26 07:36:12 +00:00
Matt DeVillier dff9994b96 docs/purism/librem_mini: Fixup CPU model, markup links
Change-Id: I26c0936c912490fc0ba28ee53139e3a1f3a00911
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-21 18:17:17 +00:00
Patrick Rudolph 57907fcebf mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes

Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM

Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-19 10:50:49 +00:00
Patrick Rudolph e563815e05 arch/x86/boot: Jump to payload in protected mode
*   On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
*   Add a helper function to jump to arbitrary code in protected mode,
    similar to the real mode call handler.
*   Doesn't affect existing x86_32 code.
*   Add a macro to cast pointer to uint32_t that dies if it would overflow
    on conversion

Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-19 09:06:43 +00:00
Sam Lewis cb287987a1 arch/arm: Enable FIT payloads
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.

TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.

Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-08-19 07:16:59 +00:00
Matt DeVillier 87093758c5 documentation: Add documentation for Purism Librem Mini
Change-Id: Ie5699942f48d2d5b1417f447a9a36b98e4b18156
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18 16:01:05 +00:00
Iru Cai 1bda1c356a mainboard: Add HP EliteBook 2560p
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.

Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:25:19 +00:00
Rocky Phagura afb7a81478 cpu/x86/smm: Introduce SMM module loader version 2
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores).
Current coreboot SMM is unable to handle more than ~32 CPU threads.
This patch introduces a version 2 of the SMM module loader which
addresses this problem. Having two versions of the SMM module loader
prevents any issues to current projects. Future Xeon-SP products will
be using this version of the SMM loader.  Subsequent patches will
enable board specific functionality for Xeon-SP.

The reason for moving to version 2 is the state save area begins to
encroach upon the SMI handling code when more than 32 CPU threads are
in the system. This can cause system hangs, reboots, etc. The second
change is related to staggered entry points with simple near jumps. In
the current loader, near jumps will not work because the CPU is jumping
within the same code segment. In version 2, "far" address jumps are
necessary therefore protected mode must be enabled first. The SMM
layout and how the CPUs are staggered are documented in the code.

By making the modifications above, this allows the smm module loader to
expand easily as more CPU threads are added.

TEST=build for Tiogapass platform under OCP mainboard. Enable the
following in Kconfig.
        select CPU_INTEL_COMMON_SMM
        select SOC_INTEL_COMMON_BLOCK_SMM
        select SMM_TSEG
        select HAVE_SMI_HANDLER
        select ACPI_INTEL_HARDWARE_SLEEP_VALUES

Debug console will show all 36 cores relocated. Further tested by
generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all
cores entering and exiting SMM properly. In addition, booted to Linux
5.4 kernel and observed no issues during mp init.

Change-Id: I00a23a5f2a46110536c344254868390dbb71854c
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-15 02:16:32 +00:00
Patrick Rudolph 8daa12f7e0 arch/x86/postcar: Add x86_64 support
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.

Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-14 17:55:26 +00:00
Jonathan Zhang 6e36ee2544 doc/mb/ocp: update Delta Lake documentation
Update Delta Lake documentation following ww30 to ww33 build/test/release
cycle.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14 09:07:32 +00:00
Balazs Vinarz ffa710b9dd mb/asus: Add Asus A88XM-E FM2+ with documentation
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO

Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS:  Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13

Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation

Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-13 17:34:04 +00:00
Patrick Georgi 20245aa622 Documentation: Fix sphinx configuration
Without the brackets, the string seems to be added as a list of
characters, and since there's no extension called 's', sphinx
bails out.

Change-Id: If0fc9c1a74f334b6154df3cb26836509de913567
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44114
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-04 12:18:29 +00:00
Paul Menzel e1574e31f6 Doc/mb/facebook/monolith: Correct grammar by removing plural *s*
Change-Id: I2d14902f9d975e89cd2842f4c12eab8ca4018fbf
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44018
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:09:50 +00:00
Paul Menzel d3d316a28f Doc/mb/lenovo: Mark up file name as code/monospace
Change-Id: I397b1dc0c3faf65811889d4c5814d6dcca7fe6b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43748
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03 05:08:58 +00:00
Jonathan Zhang b84bd303ee doc/getting_started: update name of file generated by "make savedefconfig"
Update kconfig.md to reflect that defconfig (instead of mini-config)
file is generated by running "make savedefconfig".

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I4075e5b51e3c504eaad25e3abfc52ba593364ee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-29 09:36:33 +00:00
Patrick Georgi 71a22e3cfc Documentation: Revise "24 hours wait period" rules
They're more or less the same but reworked for hopefully some more
clarity. There have been some best practices around documenting the
reason for expedited processing so let's make them official, too.

Change-Id: I620e48016a1ceda2ac43f26624ed21af01f6a0a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 09:18:26 +00:00
Paul Menzel 229616419d Doc/mb/facebook/monolith: Use correct TianoCore commit hash
The commit hash is the same as the SeaBIOS one, and is indeed from the
SeaBIOS repository.

Change-Id: I820b9b748778050fc694c13b1e2b2fc80885b4f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43749
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28 19:24:05 +00:00
Rizwan Qureshi ec321094f6 soc/intel/common/basecode: Implement CSE update flow
The following changes are done in this patch:
 1. Get the CSE partition info containing version of CSE RW using
    GET_BOOT_PARTITION_INFO HECI command
 2. Get the me_rw.version from the currently selected RW slot.
 3. If the versions from the above 2 locations don't match start the update
    - If CSE's current boot partition is not RO, then
        * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
          HECI command.
        * Send global reset command to reset the system.
    - Enable HMRFPO (Host ME Region Flash Protection Override) operation
      mode using HMRFPO_ENABLE HECI command
    - Erase and Copy the CBFS CSE RW to CSE RW partition
    - Set the CSE's next boot partition to RW using
      SET_BOOT_PARTITION HECI command
    - Trigger global reset
    - The system should boot with the updated CSE RW partition.

TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995

Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:42:06 +00:00
Maxim Polyakov a76a64833b soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
2020-07-26 21:33:08 +00:00
David Hendricks 4cdc698707 Doc/tutorial/part1.md: Show how to list toolchain targets
Change-Id: I276ea0a6b52b55b8772c76f48f7a0fb149af6e78
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 04:56:25 +00:00
Tim Wawrzynczak 0115ba8835 Documentation: Add documentation for drivers/intel/dptf chip driver
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-18 16:05:43 +00:00
Patrick Georgi b8d0d089b3 Documentation: Remove mention of manual checkpatch.pl invocation
We typically call checkpatch.pl through make lint which properly adds
the option to tell checkpatch that our lines may be 96 columns long.

However there's one mention of calling checkpatch directly and that
confuses people with complaints about overly long lines that exceed
80 columns.

The lint test that runs checkpatch (and with the right options)
can also be used on a per-directory basis, so offer that instead.

Change-Id: If21e925d2d2394c876724a44b0e23c9b2744c56b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-16 10:48:18 +00:00
Patrick Rudolph 03a79520d6 cpu/x86/smm: Add support for long mode
Enable long mode in SMM handler.
x86_32 isn't affected by this change.

As the rsm instruction used to leave SMM doesn't restore MSR registers,
drop back to protected mode after running the smi_handler and restore
IA32_EFER MSR (which enables long mode support) to previous value.

NOTE: This commit does NOT introduce a new security model. It uses the
      same page tables as the remaining firmware does.
      This can be a security risk if someone is able to manipulate the
      page tables stored in ROM at runtime. USE FOR TESTING ONLY!

Tested on Qemu Q35.

Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08 07:28:32 +00:00
Patrick Rudolph d5321bf2fb Documentation: Add TODOs for secure SMM when using x86_64
Change-Id: I157238f18bc1c2eba0adc0b87caa9adaf3fc5d38
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08 07:27:52 +00:00
Paul Menzel 6663ad99cf arch/x86: Support x86_64 exceptions
*   Doesn't affect existing x86_32 code.

Tested on qemu using division by zero.
Tested on Lenovo T410 with additional x86_64 patches.

Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-05 19:56:09 +00:00
Jonathan Zhang 34cfeee406 doc/mb/ocp: Add documentation for Delta Lake
Add OCP platform Delta Lake documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I9216c80023db071591c8d3add7c0f041e9e6b97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-04 11:16:44 +00:00
Patrick Rudolph f664321508 Documentation: Add several fixes
* Add support for Sphinx 3.0+
* Add backward support for Sphinx 1.8 and older
* Make sphinxcontrib ditaa an optional extension
* Allow SPHINXOPTS to be set from command line
* Add sphinx and sphinx-lint to top level Makefile

Change-Id: If10aef51dc426445cb742aad13b19ee7fe169c51
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41492
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 21:51:26 +00:00
Kyösti Mälkki 239abaf759 ACPI GNVS: Replace uses of smm_get_gnvs()
Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-01 05:14:24 +00:00
Angel Pons 05ba1e9bf2 Doc/mb/google/dragonegg: Drop abandoned project info
Commit 0013623 (mb/google/dragonegg: remove abandoned project) dropped
this mainboard because it is no longer in development nor used. However,
the associated documentation remained. Rest in pieces, Dragonegg. ;-;

Change-Id: Idd2ee716717132ba3fa237ae97f34686007d3685
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-30 09:19:52 +00:00
Bill XIE d87277abbf mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini PCIe
    - No docking
    - No TPM

Tested:
    - CPU i5-3337U
    - 8GiB SO-DIMM
    - Camera
    - PCIe and USB2 on M.2 slot with A key for WLAN
    - SATA and USB2 (no SuperSpeed components) on M.2 slot with B key for WWAN
    - On board SDHCI connected to PCIe
    - USB3 ports
    - libgfxinit-based graphics init
    - NVRAM options for North and South bridges
    - Sound
    - ThinkPad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from SeaBIOS.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Id59cdc5479aaf70809dd1ca613056263661455eb
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41390
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-29 15:51:23 +00:00
Jonathan Zhang c664b90f05 Doc/mb/ocp: Add documentation for Tioga Pass
Add OCP platform Tioga Pass documentation.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If4c2832d5bd006c572dab035040b4242f8a3d53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-22 11:51:06 +00:00
Patrick Rudolph 2fdabd9038 smmstore: Verify userspace-provided pointer to protect SMM
Use the introduced functions and verify pointers in the SMMSTORE.
Make sure to not overwrite or leak data from SMM and update the
documentation as well.

Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:05 +00:00
Patrick Rudolph 41fec869fb cpu/x86/smm: Add helper functions to verify SMM access
* Add a function to check if a region overlaps with SMM.
* Add a function to check if a pointer points to SMM.
* Document functions in Documentation/security/smm

To be used to verify data accesses in SMM.

Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:17:56 +00:00
Furquan Shaikh 2778420f7f Documentation: Add section about SPD tools for TGL and JSL
CB:41612 added a new set of tools for generating SPDs for TGL and JSL
based mainboards. This change adds relevant documentation to
coreboot-4.13 release notes.

Change-Id: I168adad25df9195dec64e8104f2dbe992eebddc6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42092
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 18:39:15 +00:00
Kyösti Mälkki 4164476dfc mb,soc/intel: Rename acpi_fill_in_fadt() to acpi_fill_fadt()
Change-Id: I9025ca3b6b438e5f9a790076fc84460342362fc2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41919
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:45:45 +00:00
Angel Pons 455097616c Doc/mb/gigabyte/ga-h61m-s2pv: Fix in-circuit programming
It is NOT supported. The board is not meant to be flashed externally.

Change-Id: If422810e84355cb94004e5ca2b95d239804699d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
2020-06-06 20:13:34 +00:00
Christian Walter b646e28769 mb/prodrive/hermes: Add new mainboard port
This patch adds support for the Prodrive Hermes mainboard.

Tested with CoffeeLakeFspBinPkg FSP 7.0.68.41.

Untested:
* CNVi
* Intel Graphics

Tested:
* CPU Intel Xeon E2288G
* CPU Intel Core i3-9100F
* CPU Intel Core i7 9700KF
* CPU Intel Core i7 9700E
* CPU Intel Core i7 9700F
* CPU Intel Core i5 9600K
* CPU Intel Pentium Gold G5400
* PCIe Link Width x8 on Slot6 by changing PCIe mux
* All four DDR4 slots in different configurations
* USB2.0 HDR1
* USB2.0 HDR2
* USB3.0 HDR
* Slot1
* Slot2
* Slot3
* Slot4
* Slot6
* M2.M NVMEe
* Ethernet PHYs 0-4
* Aspeed BMC PCIe
* Aspeed BMC USB
* Aspeed Graphics init
* USB3 backplane all working
* I801 SMBUS

Not Working:
* Intel HDA

Change-Id: Id7d051d3fa6823618691d5572087c9ae589c2862
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-06-06 07:44:53 +00:00
Tim Wawrzynczak a4e2e0550c Documentation: Add section about 'hidden' devices to 4.13 release notes
CB:41384 (SHA dbcf7b1621) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.

Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06 01:33:38 +00:00
Duncan Laurie 36e6c6f8d2 fw_config: Add firmware configuration interface
This change introduces a new top-level interface for interacting with a
bitmask providing firmware configuration information.

This is motivated by Chromebook mainboards that need to support multiple
different configurations at runtime with the same BIOS.  In these
devices the Embedded Controller provides a bitmask that can be broken
down into different fields and each field can then be broken down into
different options.

The firmware configuration value could also be stored in CBFS and this
interface will look in CBFS first to allow the Embedded Controller value
to be overridden.

The firmware configuration interface is intended to easily integrate
into devicetree.cb and lead to less code duplication for new mainboards
that make use of this feature.

BUG=b:147462631
TEST=this provides a new interface that is tested in subsequent commits

Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02 16:40:04 +00:00
Jan Dabros 5694342a81 Documentation/tutorial: Add tutorial for writing unit tests
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I1ebd2786a49ec8bc25e209d67ecc4c94b475442d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-30 08:46:59 +00:00
Elyes HAOUAS a1b19de447 Documentation/acpi: Fix the path to variants/hatch/overridetree.cb
Change-Id: I7c3fd942318f28b4714bc7c2a47bedf85f7923ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-26 14:58:35 +00:00
Duncan Laurie ba56da85e8 Documentation: Add info about SoundWire coreboot implementation
This change adds a document about the SoundWire implementation in
coreboot with details adding new controllers and codecs and
connecting them in the mainboard devicetree.

BUG=b:146482091

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibc04442e22acfc03ff86c49c8a7a215ceefc24c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40892
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-22 01:49:11 +00:00
Bill XIE cfd78b1500 Revert "mainboard/lenovo/x230: Add ThinkPad x230s as a variant"
This reverts commit 6b95507ec5, in order
to recommit and review it again.

Change-Id: Id4ddf99200f77016a48d02a8421d080cea492aae
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41504
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-21 02:50:08 +00:00
Matt DeVillier dd467bfc14 drivers/intel/gma: Add override for presence straps
A handful of boards do not properly implement the presence straps,
leading libgfxinit to fail to detect an attached display. Add an
override, defaulting to N, which can be set for affected boards.

Add a section to the documentation detailing the option and its usage.

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I43c61d67147878887658b23d90fb1c0b91e7a2af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-05-20 23:38:05 +00:00
Patrick Georgi 736024afdb Documentation: Encourage documentation with code changes
The resource allocator woes post-4.12 release showed room for
improvement on both discussion and documentation.  To encourage this
(and encourage reviewers to look out for issues in that space),
extend the review guidelines so that they encourage to more clearly
document the reason for a change with the change (commit message or
our documentation) and also to loop in the mailing list.

Change-Id: I1962dba3fe7e1a01fa4c8b0058297c7d050cb7b7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-20 08:44:26 +00:00
Raul E Rangel cbaa835f21 soc/amd/picasso/Makefile: Use apcb_tool to generate APCBs from SPDs
BUG=b:147042464
TEST=Boot trembyle to OS

Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ife48d5268230f70c6a6f4a56c1f0d05b6c924891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41381
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18 07:40:51 +00:00
Patrick Georgi 33e19ac619 Documentation: Fix 4.12 release notes, improve checklist
Since I seem to forget to remove "Upcoming" in the release notes
every single time, and others might as well, fix it here and also
tell future release managers to take care of that.

Change-Id: I8ffe34f25e954621bdd635e115a8b1a914df9c27
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-18 07:04:04 +00:00
Michał Żygowski 72f06ca554 mb/dell/optiplex_9010: Add Dell OptiPlex 9010 SFF support
Based on the autoport. The OptiPlex 9010 comes in four different sizes:
MT, DT, SFF and USFF. Tested on SFF only. The other PCBs are slightly
different, but they are designed with intercompatibility in mind. With
small devicetree overrides it should work on OptiPlex 7010 and other
OptiPlex 9010 variants as well.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88d65cae30d08ca727d86d930707c2be25a527cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40351
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-16 17:38:46 +00:00
Bill XIE 6b95507ec5 mainboard/lenovo/x230: Add ThinkPad x230s as a variant
The code is based on autoport and that for X230. Major differences are:
    - Only one DDR3 slot
    - HM77 PCH
    - M.2 socket instead of mini pci-e
    - no docking
    - no tpm

Tested:
    - CPU i5-3337U
    - Slotted DIMM 8GiB
    - Camera
    - pci-e and usb2 on M.2 slot with A key for wlan
    - sata and usb2  (no superspeed components) on M.2 slot with B key for wwan
    - On board SDHCI connected to pci-e
    - USB3 ports
    - libgfxinit-based graphic init
    - NVRAM options for North and South bridges
    - Sound
    - Thinkpad EC
    - S3
    - Linux 4.9 within Debian GNU/Linux stable, loaded from
      Seabios.

Untested:
    - Touch screen, which is said to work under ubuntu but not debian.

Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-13 12:10:38 +00:00
Angel Pons 56875113b7 Doc/mb/lenovo: Fix broken link
Change-Id: Iafa7e0f3734042e35e8b4ea440baf1c3c3d147e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-12 19:45:02 +00:00
Paul Menzel 3b3512941b Documentation/getting_started: Fix typo
Change-Id: I41571c45719dfade49a021b6bafe80afdcb7b581
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-12 19:41:43 +00:00
Patrick Georgi f2c32515ee Documentation/releases: Update for 4.12
Fill in some blanks for 4.12, mark it done, add template for 4.13.
Also update the list of vboot supported boards.

Change-Id: Id6b663f13367eb40e66af30aadd33991c8dd635c
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-12 10:30:22 +00:00
Patrick Georgi 6b5bc77c9b treewide: Remove "this file is part of" lines
Stefan thinks they don't add value.

Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)

The exceptions are for:
 - crossgcc (patch file)
 - gcov (imported from gcc)
 - elf.h (imported from GNU's libc)
 - nvramtool (more complicated header)

The removed lines are:
-       fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-#  This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */

Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11 17:11:40 +00:00
Jan Dabros 50544a1999 Documentation/4.12-relnotes.md: Add a note about unit testing coreboot
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Id6365b86640832b91a722cd12f64c03fc8a41fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-11 13:36:31 +00:00
Patrick Georgi 2faeb11fcd treewide: more SPDX header work
Change-Id: Ib78c322730ec6dfa9dcaafa16e5741cd3d351b8d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-09 21:20:15 +00:00
Patrick Rudolph 0f4977705d Documentation: Update vboot on lenovo
Update the documentation now that CB:32705 is merged.

Change-Id: I9845c0750ec4016188478154610400d1b8556793
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40775
Reviewed-by:  Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04 19:17:54 +00:00
Furquan Shaikh 76cedd2c29 acpi: Move ACPI table support out of arch/x86 (3/5)
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.

In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'

BUG=b:155428745

Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02 18:45:16 +00:00
Christian Walter e4c81bcca5 documentation: Add documentation ideas for season of docs
Let's gather some documentation ideas for the season of docs. I reused
the project ideas style (thanks Patrick). Feel free to add yourself as a
mentor here. Also if you have more ideas, please add them to the
document.

Change-Id: I72221cbd53b99cdc946109753cf72af9c865a1e5
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40662
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01 13:47:06 +00:00
Evgeny Zinoviev d991bf1fb4 Doc/mb/51nb/x210: Do minor fixes
Fix code blocks, add a newline, use inline code blocks for commands.

Change-Id: Iecf04b00ed12323c124517f2557cc8b60640b618
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01 06:44:07 +00:00
Jan Dabros 6449b67427 Documentation: Add proposal for firmware unit testing
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I552d6c3373219978b8e5fd4304f993d920425431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-05-01 06:31:25 +00:00
Patrick Rudolph 8c82010c97 Documentation: Spell vboot all lowercase
Update all occurrences of vboot and spell it lowercase.

Change-Id: I432b0db8a3dda43b71844e557a3d89180f25f1c3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-04-28 06:14:25 +00:00
Patrick Rudolph fcfca1da5e Documentation: Add vboot on Lenovo devices
Describe vboot implementation details for retrofitted Lenovo ThinkPad devices.

Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39151
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-27 08:52:52 +00:00
Jacob Garber 2246216971 Doc,util: Update list of utilities
Remove entries for old utilities and add entries for new ones.
Generated using util/util_readme, with some tweaks to preserve the
markdown.

Change-Id: I3a4d8a6bf15a677aa07aa72b8809328110fb72da
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20 06:55:49 +00:00
Iru Cai 7691ebc379 Doc/mb/hp: rename the document about HP laptops with KBC1126
Later EliteBooks use different EC chips and have different EC firmware
interfaces, so rename the document elitebook_series.md to a more
precise name and also do some rewriting.

A link to the code review page for 8760w is also added because the
port for this laptop is not merged yet.

Change-Id: I2f9b8c4e52ed760c16977d16838cca9e490cda05
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-20 06:52:34 +00:00
Arthur Heymans 895c77f361 Documentation/vboot: Drop deprecated options from example
4K keys are now default.

Change-Id: I16599d0e8b874f9e8a56100fea06d6e4f94a5c00
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-14 10:04:10 +00:00
Arthur Heymans 15161d9284 4.12 release notes: Add some explanation behind deprecations
Some features are made mandatory, meaning that some platforms have
been dropped from master. This also explains that further development
on these popular platforms can happen on the 4.11 branch.

TODO is this really the right place or is it too technical for release
notes?

Change-Id: I95e01c301e7db6f81ef88a89d709ebab35c9ccfb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-04-14 09:55:47 +00:00
dalao 56a25a98db mainboard/lenovo: Use the original hardware ids for keyboard/pointing
Currently coreboot is using the compatible ID PNP0303 for all keyboards
and PNP0F13 for all pointing devices, which causes some problems. On
Windows, the touchpad driver can't be automatically matched and
installed through Windows Update. On Linux, there are some strange
issues. So it's better to use the original hardware IDs for each model.
The hardware IDs for the following models can be found By searching for
dmesg logs on vendor BIOS:

T60: https://mail.gnome.org/archives/networkmanager-list/2012-January/msg00110.html
Keyboard: PNP0303 Pointing: IBM0057

R60: https://openbenchmarking.org/system/1202279-AR-COMPRESS715/Lenovo%20R60/dmesg
Keyboard: PNP0303 Pointing: IBM0057

X60: https://github.com/pavelmachek/missy/blob/master/db/notebook/lenovo/thinkpad/x60/pavel/2018.3648803539788/dmesg.out
Keyboard: PNP0303 Pointing: IBM3780

X200: https://ubuntuforums.org/showthread.php?t=1833248&page=2
Keyboard: LEN0010 Pointing: IBM3780

T400: https://github.com/heradon/libreboot-fork/blob/master/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log
Keyboard: LEN0010 Pointing: IBM3780

T510: https://bbs.archlinux.org/viewtopic.php?id=120287
Keyboard: PNP0303 Pointing: LEN0015

T410: https://forum.ubuntuusers.de/topic/kein-sound-109/
Keyboard: PNP0303 Pointing: LEN0015

T420: https://linux-hardware.org/index.php?probe=e6a094ade5&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T420s: https://bbs.archlinux.org/viewtopic.php?id=191510
Keyboard: PNP0303 Pointing: LEN0015

T520: https://bbs.archlinux.org/viewtopic.php?id=195636
Keyboard: PNP0303 Pointing: LEN0015

W520: https://linux-hardware.org/index.php?probe=9306cac54c&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T430: https://github.com/farjump/fwtr/blob/master/lenovo/thinkpad-t430/2347ds2/lenovo/g1et73ww-2.09/fwts/20160218_174223/dmesg.log
Keyboard: PNP0303 Pointing: LEN0015

T430s: https://linux-hardware.org/index.php?probe=01545dc8fb&log=dmesg
Keyboard: PNP0303 Pointing: LEN0015

T530: https://forums.fedoraforum.org/showthread.php?316640-Fedora-27-High-CPU
Keyboard: LEN0071 Pointing: LEN0015

W530: https://bugs.freedesktop.org/attachment.cgi?id=115557
Keyboard: LEN0071 Pointing: LEN0015

L520: https://pastebin.com/U6MaBAY3
Keyboard: PNP0303 Pointing: LEN0017

X201: https://linux-hardware.org/index.php?probe=d7085ee4c8&log=dmesg.1
Keyboard: PNP0303 Pointing: LEN0018

X220: https://bbs.archlinux.org/viewtopic.php?id=237669
Keyboard: PNP0303 Pointing: LEN0020

X230: https://forums.bunsenlabs.org/viewtopic.php?id=2460
Keyboard: PNP0303 Pointing: LEN0020

X131e: https://linux-hardware.org/index.php?probe=d765880811&log=dmesg
Keyboard: MSF0001 Pointing: LEN0026

X1 Carbon Gen 1: https://bugzilla.kernel.org/show_bug.cgi?id=85851
Keyboard: LEN0071 Pointing: LEN0030

s230u: https://launchpadlibrarian.net/147231958/dmesg-reboot.txt
Keyboard: PTL0001 Pointing: LEN0031

T540p: https://linux-hardware.org/index.php?probe=da766a30bc&log=dmesg
Keyboard: LEN0071 Pointing: LEN0034

X240: https://linux-hardware.org/index.php?probe=fa7155b0e4&log=dmesg
Keyboard: LEN0071 Pointing: LEN0035

T440p: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T440s: https://bugzilla.kernel.org/show_bug.cgi?id=91541
Keyboard: LEN0071 Pointing: LEN0036

T450: https://gist.github.com/kzar/1c38630eb22e4bf5b976
Keyboard: LEN0071 Pointing: LEN200e

Others:
https://github.com/torvalds/linux/blob/master/drivers/input/mouse/synaptics.c

Test result: This can make Windows automatically install the Lenovo
touchpad driver. It also fixes the T440p touchpad issue.

Change-Id: Ifb635da99c5e05f987aaf4f172108d788dcc2932
Signed-off-by: dalao <dalao@tutanota.com>
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36371
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14 09:50:10 +00:00
Evgeny Zinoviev 408fdeba7f Doc/mb/lenovo/ivb_internal_flashing: Fix a typo
unmount -> umount. My mistake.

Change-Id: I5d1b675f6ab7c027f2e646424adb1f255967c753
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-04-09 23:44:21 +00:00
Christian Walter b2f8ce7591 soc/intel/cannonlake: Steal no memory for disabled IGD
Set IgdDvmt50PreAlloc to zero if InternalGfx is disabled. It's 'correct'
to do it like this, otherwise the FSP would always allocate memory for
the IGD even if it is disabled. In addition the FSP enables the graphics
panel power even if no IGD is present which leads to a crashing FSP.
Thus, if no IGD is present we switch off the panel via UPDs.

Refer to this issue on IntelFSP for details:
https://github.com/IntelFsp/FSP/issues/49

Tested on:
* CFL platform with IGD
* CFL platform without IGD

Change-Id: I6f9e0f9855224614471d8ed23bf2a9786386ddca
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-04-09 21:49:01 +00:00
Nico Huber 04da5d72d9 fsp2_0: Clean up around `config FSP_USE_REPO`
We can make our lifes much easier by removing its dependency on
`ADD_FSP_BINARIES`. Instead, we imply the latter if the repository
is to be used. We can also hide a lot of unnecessary prompts in
this case.

Also, remove default overrides and selects for the two that are
now unnecessary.

Change-Id: I8538f2e966adc9da0fbea2250c954d86e42dfeb3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39882
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-05 23:26:04 +00:00
Angel Pons b54c5168bd Doc/mb/index.md: Fix mainboard vendor order
Oops, Libretrend "stole" all the Thinkpads from Lenovo. Correct that.

Change-Id: I15f189dedab98fdbea8c26ceb8ac84486df2519b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40118
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-03 13:43:35 +00:00
Marcello Sylvester Bauer eff1306ea4 Documentation/mb/lenovo: Test shrunken ME on Ivy Bridge
Update the Lenovo Ivy Bridge documentation that no issues could be
observed on W530.

Tested on Lenovo W530 with stripped ME and found no issues:
commit 93b0c7cfc6

* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* mSATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* CPU temperature reporting
* Stress test stable (intel_pstate no_turbo due to W530 overheating bug)
  * Youtube videos
  * stress -c 8 -m 1 -t 3600

Change-Id: I46d23d41cc6ade5e641a6ddb3f357a6036002edc
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39603
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31 10:32:25 +00:00
Patrick Rudolph 5271776689 Documentation: Add lemp9 to toctree
Fix "WARNING: document isn't included in any toctree" by adding
the lemp9 to mainboard/index.md.

Change-Id: Id6d8f9e2aab6dc7ad4baf1b37d88e531acb757f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-25 16:10:15 +00:00
Christian Walter be3979c873 acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.

Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10

FWTS does not return FAIL anymore on ACPI tests

Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-03-23 16:54:58 +00:00
Marcello Sylvester Bauer e9aef1fe45 Doc/security/vboot: Add a script generated device list
Add a script generated list of vboot enabled devices to the
documentation. Add a entry to the release checklist.

Change-Id: Ibb57d26c5f0cb8efd27ca9a97fd762c25b566f93
Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-23 09:23:11 +00:00
Patrick Rudolph 903d9a225e Documentation: Add new GSoC projects
Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20 14:44:47 +00:00
Matthew Garrett 2f62a352ea mb/51nb: Add support for the 51nb X210
The 51nb X210 is a replacement motherboard for Thinkpad X200/X201 systems,
based on a modern Kabylake CPU. It also ships with no firmware protection,
(IFD is fully unlocked, no protected regions are set, no Bootguard),
making it an ideal coreboot target. This port is based on the support for
the Skylake-based Purism Librem 13v3, with the following significant
changes:

* EC firmware is contained within the system SPI flash, and so a blob of
  EC firmware must be injected to a defined location during image build.
* GPIO layout is different - this is currently just a raw import of the
  GPIO configuration from the vendor firmware
* The system has two DIMMs, so an additional SPD address has been added
* The USB port layout is different
* The EC must be enabled at boot time through SuperIO-style logical device
  configuration
* EC register layout is different, necessitating changes in the ACPI tables
* The HDA pins are different
* The genx_dec config is different

All hardware appears to work as expected, although the SD reader is
untested.

Signed-off-by: Matthew Garrett <mjg59@google.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: If74621e76d703f629b54f1feb1acfc95cc72d183
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-03-16 14:42:04 +00:00
Angel Pons 31b7ee4201 treewide: Replace uses of "Nehalem"
The code in coreboot is actually for the Arrandale processors, which
are a MCM (Multi-Chip Module) with two different dies:

- Hillel:   32nm Westmere dual-core CPU
- Ironlake: 45nm northbridge with integrated graphics

This has nothing to do with the older, single-die Nehalem processors.
Therefore, replace the references to Nehalem with the correct names.

Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:04:39 +00:00
Paul Menzel f897623aac mb/asus/p8z77-m_pro: Use uppercase for *PRO*
Consistently use the official uppercase spelling.

Change-Id: I2e2d62389d1b965f4a391080a10e7f97fa787d14
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39350
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15 13:00:07 +00:00
Paul Menzel fac491dab7 Docs: Fix link for ASUS P8Z77-M PRO
Change-Id: I2b8ff31acc7da2b1ded036604fa4a6b6d6d9cac0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-15 12:59:52 +00:00
Patrick Rudolph cb858d6d62 superio/nuvoton/nct5539d: Update documentation and remove DSDT
There seems to be no board using this, but some currently under review.
Remove the DSDT, which doesn't work together with the SSDT ACPI
code generation. Also update the documentation pointing to the SSDT
generator.

Change-Id: I8b7daeadaaac93d74ee2fc9eb18f0eff5ef50eb3
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-11 15:03:39 +00:00
Evgeny Zinoviev fc59f0860b Documentation: Fix a typo
filse -> files

Change-Id: Iaf0c3a064b42dde70b1e01cfc15ad3187bf8bfcc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-03-11 14:28:34 +00:00
Sebastian 'Swift Geek' Grzywna 49fb39b783 Documentation: Update codenames
austin-3 was a devel board, retracting
t60 comes in variants with discrete gpu and only intel gpu one

Change-Id: Ic1f7397b8676bdcc15f63d59d87518d35bba5b4d
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-10 20:26:32 +00:00
Michał Żygowski b9f9f6c12b mb/libretrend/lt1000: Add Libretrend LT1000 mainboard
Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:04:05 +00:00
Michał Żygowski 48be6b276a mb/protectli/vault_kbl: Add FW6 support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I03e8e8db5d827fe113280f2a6376d364edf42870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-10 10:03:17 +00:00
Michał Żygowski 83565dea86 mb/protectli/vault: Add FW2B and FW4B Braswell based boards support
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I553fd3a89299314a855f055014ca7645100e12e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-03-09 21:26:20 +00:00
Nico Huber 4ce52903b0 3rdparty/libgfxinit: Update submodule pointer
Changes allow to use the integrated panel logic (power sequen-
cing and backlight control) for more connectors. The Kconfigs
GFX_GMA_PANEL_1_PORT and GFX_GMA_PANEL_2_PORT can now be set
to any port, e.g.

  config GFX_GMA_PANEL_1_PORT
          default "DP3"

Now that the panel logic is not tied to the `Internal` port
choice anymore, we can properly split it into `LVDS` and `eDP`.

This also adds Comet Lake PCI IDs which should still work the
same as Kaby and Coffee Lake.

Change-Id: I78b1b458ca00714dcbe7753a7beb4fb05d69986b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38921
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-09 08:20:12 +00:00
Evgeny Zinoviev ef613b97cf Documentation: Add Montevina ThinkPads common page
- Add a common page about Montevina ThinkPads.
- Describe how to disable ME and remove its firmware on these models.
- Describe vendor flash layouts.

Thanks to swiftgeek for his help when writing this, especially the last
paragraph and flash layouts.

Change-Id: I85917821efe63fff4b933b6226e99c17b63eb1b9
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-09 08:10:36 +00:00
Chris Morgan 5e5e789f9b nb/intel/haswell/peg: Add PEG driver stub
This is a port of https://review.coreboot.org/c/coreboot/+/22337 to the
Haswell northbridge.  This code is necessary to support the dGPU of the
t440p. Code was cut and pasted from Sandy Bridge with vendor IDs updated
to the correct Haswell values.  Tested on t440p with dGPU on Ubuntu
18.04.4 with 5.3.0-28 kernel. Without patches dmesg reports Nouveau is
unable to read the VBIOS of the dGPU as it has an invalid checksum (I
checked that the ROM in CBFS is correct). With this patch DRM works
correctly with both the Nouveau driver and the Nvidia proprietary
driver. Windows 10 1909 also tested but generates bluescreen once GPU
driver is loaded.

Change-Id: Ie5f089fb6fd774e6c61f4f9281e2945bd44edf27
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-03-06 07:54:26 +00:00
Angel Pons 446e4dc238 util: Remove viatool
It somehow creeps into `make clean`, but is not used at all. Since no
VIA platform remains in coreboot, drop the utility as well.

Change-Id: Ia7e11379a6db650b5190a056226a9101c2be7dec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04 15:46:44 +00:00
Rajat Jain 310623b2dd arch/x86/acpigen: Add new helper routines for XOR and get_rx_gpio
Add new helper function in the acpigen library, that use the underlying
soc routines.

Change-Id: I8d65699d3c806007a50adcb51c5d84567ce451b7
Signed-off-by: Rajat Jain <rajatja@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-03-02 11:40:23 +00:00
Patrick Rudolph 4d9dd22bd1 Documentation: Add Heads to payloads
Add a small description about Heads.

Change-Id: I2e768a640751fee1b1b5df4401205e24cde0607c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-03-02 11:39:16 +00:00
Patrick Rudolph 0751d7bded Documentation: Add tutorial for me_cleaner on Lenovo devices
Add a tutorial how to use ME cleaner, and give some basic steps to
strip the ME. Update the Lenovo Sandy Bridge documentation that no
issues could be observed on X220 and give an example flash layout.

Tested on Lenovo X220 with stripped ME and found no issues:
commit: cbc5b99ac9

* Displayport
* VGA
* USB
* Bluetooth
* Wifi
* Wifi-kill switch
* libgfxinit
* SATA
* Audio
* SD-card
* Ethernet
* Keyboard
* Fn-Keys
* Display brightness
* ACPI S3 resume
* Battery events
* CPU temperature reporting
* FAN managment
* Stress test stable
  * Youtube videos over Wifi
  * stress -c 2 -m 1 -d 1
  * glxgears

Change-Id: I0b1d04f00b5dbb38cf04333f2b345749b740a375
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39129
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-02 11:39:05 +00:00
Arthur Heymans 4c28ccd0dc Docs/project_ideas.md: Add a memtest libpayload based payload
Change-Id: Iebdb75b99e18fe92aa4c801769532781edf44d9a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-28 10:42:57 +00:00
Patrick Georgi 6a4f46ac5e Documentation/project_ideas: Update after 2019
The coverity project is done, for the most part, so drop it. Expand
a bit on the scope of the toolchain binary project, and point out
that the Ghidra project already has code from GSoC 2019 but could be
developed further.

Change-Id: I7342cc3133494f69b175b11b1f8342a0f40840e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-24 14:20:04 +00:00
Elyes HAOUAS 2119d0ba43 treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 14:10:00 +00:00
Ivan Labáth 3ae1765df6 Documentation: getting_started/gpio.md: fix markup
Change-Id: I2c61770d60a4f290fd8d516850f16bc3808ad48d
Signed-off-by: Ivan Labáth <iger@labo.rs>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39082
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-24 12:59:53 +00:00
Evgeny Zinoviev 5efe122b27 Documentation: soc/amd/psp: Use real table markup
Currently, tables on this page are formatted as code blocks with
ASCII tables. Make it real beautiful tables.

Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:10:22 +00:00
Evgeny Zinoviev abe9673774 Documentation: Use inline code block for kernel parameter
Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:09:53 +00:00
Evgeny Zinoviev 286b07ca33 Documentation: Fix style issues on Lenovo X301 page
- Fix lists markup
- Some minor fixes in the text (e.g. lowercases)

Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-18 19:48:33 +00:00
Evgeny Zinoviev b3a247ccca Documentation: mb/lenovo: Make X1 uppercase
x1 -> X1.

Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:22:54 +00:00
Patrick Rudolph f6be41a988 Documentation/lenovo: Replace RST code with markdown
Latest Sphinx supports up path traversal in markdown. Replace old
RST code that's no longer needed to prevent it being copy and pasted.

Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:13:47 +00:00
Patrick Rudolph f9e10f26ba Documentation: Remove confusing xyz0 naming convention for Lenovo devices
Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge.
Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s.

Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:12:22 +00:00
Elyes HAOUAS 6dc9d0352e treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.

Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 20:11:24 +00:00
Evgeny Zinoviev c7a3152273 Documentation: ifdtool/layout: use real table for FD regions
Current doc transpiles to something completely unreadable.

Change-Id: I197deb52974c88e067bc1615986a42c889214888
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:08:41 +00:00
Felix Held b39bc2510e Documentation/superio: add formatting to generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17 16:27:24 +00:00
Patrik Tesarik 5aa043b800 doc/tutorial/part1.md: Add commands for yum- & pacman-based distro
* Add additional information on non-debian cli tools
* Improve spellings and descriptions to the best of my knowledge

Adding info about needed tools in other distribution's package
managers was requested at the coreboot beginner's workshop at 36C3.

Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237
Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-12 18:45:31 +00:00
Marshall Dawson 5b43484db3 Documentation/soc/amd/family17: Update to match current design
The Picasso no longer intends to implement a hybrid romstage,
opting instead for a more traditional bootblock/romstage/ramstage.
Update the documentation to reflect this.  Clarify additional
details that have come to light since the last revision.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11 07:52:04 +00:00
Marshall Dawson 5a1ba1bc29 Documentation/soc/amd: Add PSP integration information
Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-02-11 07:51:53 +00:00
Patrick Rudolph e7ad0f2a2a Documentation: Remove qemu aarch64 from project ideas
This has been implemented last year.

Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:31:21 +00:00
Paul Menzel 75372e5a75 Documentation: Mark up register names as code
Change-Id: I708385bca8edcd74b0d4c0a3ecc181b6ccd30c2b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38721
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:23:58 +00:00
Paul Menzel cedd4525f2 Documentation: Indent code blocks instead of using ```
Both versions are correct, but especially for one liners indenting them
with four spaces instead of using ``` blocks helps readability of the
source file.

Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09 19:23:49 +00:00
Evgeny Zinoviev d498e52c3f Documentation: xx30 ThinkPads internal flashing
Add detailed instructions on how to unlock protected SPI ranges and
flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by
exploiting stock BIOS security issues.

Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-05 09:57:26 +00:00
Wim Vervoorn 94545910e6 Documentation/vendorcode/eltan: Update security document
Update the security document to reflect the current state of the
coreboot implementation.

Add more detail and document the change to the public vboot API.

BUG=N/A
TEST=build

Change-Id: I228d0faae0efde70039680a981fea9a436d2384f
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-30 13:28:24 +00:00
Wim Vervoorn ea4d1246e8 Documentation/mainboard/facebook/monolith.md: Update to beta status
Update to reflect the beta status of the code.

BUG=N/A
TEST=build

Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-30 11:36:29 +00:00
Wim Vervoorn c4a71467d1 Documentation/mainboard/facebook/monolith.md: Add flash components
Add description of the procedure to create the flash components for this
system.

BUG=N/A
TEST=N/A

Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-29 10:32:01 +00:00
Bill XIE e4d6c033fe Doc/mb/lenovo: Shrink picture for x301
Fix a non-standard larger picture not handled in time before merging.

Change-Id: Ia494484cd0eff6b19408b065264911d0093ceeb0
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2020-01-27 07:48:30 +00:00
Jeremy Soller ec430ee343 mainboard/system76: Add System76 Lemur Pro (lemp9)
The System76 Lemur Pro (lemp9) is an upcoming laptop computer. Support
in coreboot is developed by System76 and provided as the default
firmware option. Testing is done on a pre-production model expected to
be identical from a firmware perspective to the production model.

Working:
- Payload
    - Tianocore
- CPU
    - Intel i7-10510U
    - Intel i5-10210U
- EC
    - ITE IT5570E running https://github.com/system76/ec
    - Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
    - Battery
    - Charger, using AC adapter or USB-C PD
    - Suspend/resume
    - Touchpad
- GPU
    - Intel UHD Graphics 620
    - GOP driver is recommended, VBT is provided
    - eDP 14-inch 1920x1080 LCD
    - HDMI video
    - USB-C DisplayPort video
- Memory
    - Channel 0: 8-GB on-board DDR4 Samsung K4AAG165WA-BCTD
    - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
- Networking
    - M.2 PCIe/CNVi WiFi/Bluetooth
- Sound
    - Realtek ALC293D
    - Internal speaker
    - Internal microphone
    - Combined headphone/microphone 3.5-mm jack
    - HDMI audio
    - USB-C DisplayPort audio
- Storage
    - M.2 PCIe/SATA SSD-1
    - M.2 PCIe/SATA SSD-2
    - RTS5227S MicroSD card reader
- USB
    - 1280x720 CCD camera
    - USB 3.1 Gen 2 Type-C (left)
    - USB 3.1 Gen 2 Type-A (left)
    - USB 3.1 Gen 1 Type-A (right)

Not working:
- TPM2 - SPI bus 0, chip select 2 is used. Chip selects other than 0
  are not currently supported by the intel fast_spi driver.

Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: Ib0a32bbc6f89a662085ab4a254676bc1fad7dc60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-27 07:42:41 +00:00
Felix Held 8b3380044d Documentation: link asus p5q on mainboard page
Change-Id: Ia3f58cc15897bff87dd699ab1fb1c42545119f0b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-23 16:38:39 +00:00
Ivan Vatlin 0ebb7840e7 mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)
Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2
Signed-off-by: Ivan Vatlin <jenrus@tuta.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-21 13:06:39 +00:00
Felix Held c83b9783d4 Documentation/superio: add generic PNP device documentation
Change-Id: Iee75faaef713dd6ec6b6e2d536df09a41010eebf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-20 10:54:56 +00:00
Tim Wawrzynczak ee6557c06e documentation: Add documentation on setting up mainboard GPIOs
The new documentation describes typical ways that mainboards will
set up their GPIOs, as well as the distinction between "early"
and "normal" GPIOs.  It also describes the typical properties
that GPIO configuration will cover.

Change-Id: I279eec4ed2bb0248a2bdb363fb73b40b8272267f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-01-18 10:58:36 +00:00
Felix Held bfafa9e037 Documentation: document non-Docker sphinx installation and usage
Also update the known-good versions of the needed tools.

Change-Id: I0f63860beb0a8a00360752318236e302c7170977
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37952
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14 18:29:41 +00:00
Elyes HAOUAS 0f82c12f71 {Documentation,soc/intel}: Fix typo
Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37468
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10 15:24:58 +00:00
Patrick Rudolph c83bab62b3 acpi: Be more ACPI compliant when generating _UID
* Add function to generate unique _UID using CRC32
* Add function to write the _UID based on a device's ACPI path

ACPI devices that have the same _HID must use different _UID.
Linux doesn't care about _UID if it's not used.
Windows 10 verifies the ACPI code on boot and BSODs if two devices
with the same _HID share the same _UID.

Fixes BSOD seen on Windows 10.

Change-Id: I47cd5396060d325f9ce338afced6af021e7ff2b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-01-09 14:22:51 +00:00
Patrick Rudolph 9e877ec60d util/supermicro: Add and use new tool smcbiosinfo
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.

Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.

You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID

Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.

Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works

No further validation is done on the firmware.

Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06 10:56:09 +00:00
Angel Pons a8ab2b33a4 Doc/tutorial/part2.md: Align headings with part1.md
Substitute `Part` with `Step` on this file's headings and use present
tense instead of gerund.

Change-Id: Ic130ed9865be43716e7de3121534761d9fc2ae8d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26 10:50:51 +00:00
Angel Pons 93b343a779 Doc/tutorial/part1.md: Fix minor formatting issues
Make sure all titles are capitalized, and add a missing period.

Change-Id: I48b8d6c85b915cc422bdfa3a89804f92f46800ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-12-26 10:50:48 +00:00
Angel Pons d28b74ce6a Doc/index.md: Fix a typo
Change-Id: Ib2f48d03e78f6da97383e67b1d50dfe859e59612
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-26 10:49:46 +00:00
Angel Pons 58ececfb28 Doc/releases/checklist.md: Correct some inconsistencies
Use periods on every element of a list, and make `IRC` uppercase.
Also, correct a grammar mistake that slipped through.

Change-Id: Id05865719c7c845265416e89bfd9b02b6d22ca6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-12-26 10:47:13 +00:00
Patrick Rudolph 95bff2e17e superio/common: Add more ACPI methods
* Make use of introduced SSDT config mode access
* Make use of introduced SSDT mutex
* Provide ACPI functions to safely access SIO config space
* Implement method to query LDN enable state
* Implement method to set LDN enable state
* Use introduced functions to implement _DIS and _STA in the device
* Update documentation

Tested on Aspeed AST2500 and Linux 5.2.
Manually verified ACPI code that generates no errors in Linux.

Change-Id: I520b29de925f368cd71ff8f1f58d2d57d72eff8d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-22 13:47:55 +00:00
Patrick Georgi ed06e11900 Documentation: Extend release checklist (list to-be deprecated boards)
Make it part of the release process to note not only what config flags /
code properties etc will be deprecated, but to also spell out which
boards would be affected at the time of the release.

Change-Id: I0ef1404e75182ea4bacae31edb0a843e7a359545
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37702
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-16 09:37:53 +00:00
Angel Pons 5232eb1a10 Doc/mb/gigabyte/ga-h61m-s2pv: Correct IFD section
Change-Id: Ic94dd7381e9a107081011d083286d27005148557
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-13 17:33:06 +00:00
Wim Vervoorn 9a0f093343 Documentation: Fix EC type for facebook and portwell boards
Board description contained incorrect EC type.

Change EC type to ITE8528

BUG=N/A
TEST=build

Change-Id: Ib5af79fb00bfdfc5dbe001b60010a74bddc696e2
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12 15:09:30 +00:00
Patrick Georgi a73317e5cf Documentation: enable ditaa integration
For prettier diagrams: http://ditaa.sourceforge.net/

Change-Id: Ic28dc5ea9d82ff6bf8654e2e33e675a536348654
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-12 08:18:49 +00:00
Patrick Georgi 6cfda93c6c Documentation: Fix table and layout
The table wasn't pretty enough so sphinx complained, while the second
paragraph had trailing whitespace, could be wrapped differently and
also came with a typo.

Change-Id: I6c16a3a1fcc306d0b12043ebec7d4e69e9339d7d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-11 17:05:35 +00:00
Patrick Georgi e86ded841f Documentation: Describe how to deal with snooping https proxies
Disabling SSL verification is far from optimal, but depending on the
circumstances may be the most practical way, so describe how to do
that instead of leaving users confused.

It's also not _that_ bad because git's hashing scheme should uncover
most attempts to tamper with code, either when checking signed tags
or when people push (and see lots of modified commits).

State the command in a way that isn't conductive to careless
copy & paste.

Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-10 11:15:42 +00:00
Arthur Heymans edcce07531 Documentation: Move ACPI documentation in a subindex
Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:40:28 +00:00
Arthur Heymans 1bb330348d Documentation: Remove redundant 'documentation'
We are already in documentation so it should be obvious that other
links point to other documentation.

Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:40:02 +00:00
Wim Vervoorn 7c04acff8a mb/facebook/monolith: Add Facebook Monolith
The board is booting Linux and has been briefly tested.

SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.

BUG=N/A
TEST=tested on Facebook Monolith

Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06 15:15:08 +00:00
Arthur Heymans c1abf137ff Documentation/4.12-relnotes.md: Add SMMSTORE as production ready
Change-Id: I9fa0473dd8ab9d0476400fc2f40c684db0188fc3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37244
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-29 08:58:07 +00:00
Arthur Heymans b52cc0e094 Documentation: Add SMMSTORE documentation
This documents the smmstore API.

Change-Id: I992c04c0cf9b3f03755cf3fede2c82c6471a5ef4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-29 08:58:01 +00:00
David Hendricks 6572fe538a Documentation: Rework staging and commit information
This patch does two things:
- The CLI and Git Cola sections contained some duplicated information
  about pushing patches, which is now factored out into its own section.
- The draft workflow is now disabled, so that part has been reworded to
  describe how to submit a private patch.

Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Change-Id: I562c101ab2ee78d901be7e99165daba7473dc3c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-28 10:49:30 +00:00
Patrick Georgi eb80e053b6 Documentation/releases: Update checklist
Having the release notes mostly ready one week before the release
allows for better review.

Some statistics, the actual release date and commit ID can only be
filled in on release day, but there's a tried & true technique for
that: placeholders.

It's also a nice touch to have the release notes of a release within
its source tarballs, so push them right before creating the release
(since changes in Documentation/releases won't break coreboot in
any way).

Change-Id: Iad7ba1ba4fc841bf437f2a997428b7f636e15422
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36957
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-22 21:48:26 +00:00
Patrick Georgi 6059c9d133 Documentation/releases: Drop reference to piratenpad
Piratenpad is dead.

Change-Id: Id9cfb68f6c6e05d1af2a526c817713a92220d370
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36958
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 19:15:10 +00:00
Patrick Georgi 4f1d6ff42e Documentation/releases: Releasing includes announcing on the list
Change-Id: I063997d51a80b1b244a0cb35ae90446610ef2c21
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36975
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 11:28:57 +00:00
Patrick Georgi 26d2dad980 Documentation/releases: 4.11 isn't "upcoming" anymore.
Change-Id: I7102519b171c3e5269fefaa66d12d605f5d9ddb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36974
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 11:28:52 +00:00
Julius Werner f96d9051c2 Remove MIPS architecture
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.

Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 10:10:48 +00:00
Julius Werner 63c444a69b Remove imgtec/pistachio SoC
After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).

Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-20 10:10:44 +00:00
Patrick Georgi ab8edda14a Documentation/releases: Finalize 4.11, start 4.12
Fill in some stats using our repo analysis scripts in
util/release/, thank the contributors, add some prose
about notable achievements since 4.10.

Also start a new doc for 4.12.

Change-Id: I10a39081762d6e01f4040f717d36662975e4c8e9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36948
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19 14:58:22 +00:00
Patrick Rudolph 0209f3dd15 Documentation: Remove duplicated entry
The mainboard was accidently added due to bad rebase.

Change-Id: Ie7215e551651dbbc8d92316c48e455405923a30b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36077
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-19 13:47:07 +00:00
Paul Menzel 44b54aa947 Documentation: Reword Supermicro X10SLM+-F datasheet references
Change-Id: I24c4254ef65edcddadcf0386e0cbe996a5e99458
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19 12:57:28 +00:00
Michael Niewöhner a911216926 docs: intel fsp: add memory retraining bug on SPS systems
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.

Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-19 12:56:10 +00:00
Nico Huber 934b8da442 Documentation/releases: Add libgfxinit changes in 4.11
Change-Id: Id7babdc9b1d908fa90ebac098a019615fa00b973
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-18 11:00:29 +00:00
Nico Huber 1e245c1536 Documentation/releases: Add more c-env-bb platforms for 4.11
Change-Id: Ie5c83befc8e595016c63729a19e7e71438c996b5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-18 10:59:49 +00:00
Frans Hendriks 0a8e8e84f1 Documentation/mb/facebook/fbg1701.md: Update microcode blob
The microcode is available in 3rdparty microcode now.
This ucode can be used.

BUG=N/A
TEST=build

Change-Id: I52a04c7dc97608f868ee0b415bbbb328937f18f7
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-15 10:57:07 +00:00
Wim Vervoorn 700c024057 Documentation/mb/portwell/pq7-m107.md: Update microcode blob
The microcode is available in 3rdparty microcode now.
This ucode can be used.

BUG=N/A
TEST=build

Change-Id: I1d83a58e9051fa9402666f05e4f2c43e76026dfb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36854
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-15 10:56:57 +00:00
Patrick Georgi 71a94301c0 Documentation: Add more entries to 4.11 release notes
Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-12 18:21:45 +00:00
Kyösti Mälkki 19825e8e37 Documentation: Add some significant 4.11 release notes
Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-11 10:31:14 +00:00
Patrick Rudolph 1b95501fad Documentation: Add some significant 4.11 release notes
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-11 10:24:50 +00:00
Arthur Heymans 55069d15d8 arch/riscv: Pass cbmem_top to ramstage via calling argument
Tested on the Qemu-Virt target both 32 and 64 bit.

Change-Id: I5c74cd5d3ee292931c5bbd2e4075f88381429f72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 11:46:10 +00:00
Wim Vervoorn 114e2e8830 lib/cbfs: Add fallback to RO region to cbfs_boot_locate
With this change cbfs_boot_locate will check the RO (COREBOOT) region if
a file can not be found in the active RW region. By doing so it is not
required to duplicate static files that are not intended to be updated
to the RW regions.

The coreboot image can still be updated by adding the file to the RW
region.

This change is intended to support VBOOT on systems with a small flash
device.

BUG=N/A
TEST=tested on facebook fbg1701

Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 14:12:00 +00:00
Patrick Rudolph b1ef725f39 cpu/qemu-x86: Add x86_64 bootblock support
Add support for x86_64 bootblock on qemu.

Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.

Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.

Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.

The code can be easily ported to real hardware bootblock.

Tested on qemu q35.

Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-04 11:58:58 +00:00
Kyösti Mälkki 334211e4a6 Documentation: Add some significant 4.11 release notes
Change-Id: I44369bc7dee77beab480d9a16cd7268be6686eb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2019-11-04 11:34:29 +00:00
Patrick Rudolph 5666c29df1 Documentation: Fix typo
The document isn't included in any toc-tree due to a typo.

Change-Id: Ic1491dde2d48b5d004fc28c743bbee6de12f433c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36540
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:53:01 +00:00
Wim Vervoorn f6671a89c5 mb/portwell/m107: Add Kingston memory support
Add support for board revision 1.3 containing Kingston memory.

BUG=N/A
TEST=tested on portwell m107 module

Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01 11:43:05 +00:00
Marshall Dawson 86278a0361 Documentation: Add amd_blobs license agreement text
AMD has generated a simpler and more flexible license agreement for
using proprietary precompiled binary images.  The new agreement is
intended to cover all blobs in the directory structure below where
the license resides and eliminates any unique agreements previously
provided for individual products.

Add a description of the repo, as well as the license agreement it
contains.

Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-30 21:42:40 +00:00
Iru Cai b559432604 mainboard: Add Lenovo ThinkPad T440p
The code is based on autoport.

This port is tested on a T440p without a dGPU and can boot Arch Linux
from SATA disk with SeaBIOS payload. The tested components and issues
are in the documentation.

Change-Id: I56a6b94197789a83731d8b349b8ba6814bf57ca2
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34359
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-30 08:21:13 +00:00
Joe Moore b7f117dd52 Documentation/releases: Note pending AMD fam12h removal
Change-Id: I386572c772ea9de571bbb9d51ef9090e9c429b99
Signed-off-by: Joe Moore <awokd@danwin1210.me>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-29 13:13:18 +00:00
Arthur Heymans 11b910281e Documentation/writing_documentation.md: Explain how to use docker
Using docker to build to documentation eases the process of building
the documentation. Given that some versions of sphinx are
incompatible, the option to use docker is presented first.

Change-Id: I6c18f81a829364ada1859c04ba2dc4f886934bcc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36105
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27 23:36:07 +00:00
Maccraft 0cd098e4e4 mb/lenovo/{t60,r60}: Add ThinkPad R60 support as variant board
- This port should be Reclaim Your Freedom compliant
  (not certified yet).
- Untested on boards with external Radeon graphics adapter.
- Some columns on the left-most side of display are completely
  black on 1400x1050 IPS display[1]. Display works fine on Linux.
  I don't know why it appears like that. So far it has been observed
  only with native graphics initialization.
- Only GRUB2 and SeaBIOS payloads tested for now.
- 2504 docking station USB doesn't work under Linux.
  Can detect pendrive in GRUB2 payload.
- Sometimes it takes 20s of "pretending it's powered off" to run
  coreboot code. Issue is payload agnostic.
  Probably caused by missing one capacitor on my unit.

[1] https://imgur.com/a/0wpMGsm

Change-Id: Ibd9208a5eafd228f8eedbc8fb4f4eb9ed1932a14
Signed-off-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-25 20:07:16 +00:00
Marty E. Plummer 5fc8805a71 Documentation: trivial typo fix strcut/struct
Change-Id: I5e7d8e8a95e5bef23307eb50456a89e0e23c445a
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-24 16:27:47 +00:00
Arthur Heymans 62a6741bba Documentation: Add a technote section
Change-Id: I8676f89399a0def3409f19dc92e4f65924d0ba22
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23 14:22:58 +00:00
Arthur Heymans 750ce06cd5 technotes/coreboot-image-generation: Fix markdown
The manifest example has to be marked as code. The Manifest parsing
section header should be L2 and finally # is a special character in
markdown.

Change-Id: I38cb1a508ec9ccb39cb39048de3742a5cb595f7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-23 14:22:55 +00:00
Michael Niewöhner 7f2aaacd9e mb/supermicro/x11-lga1151-series: add x11ssm-f board
This adds another x11 series board, the X11SSM-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, GPIO settings and
Ethernet interfaces.

Change-Id: I24e6f0f41a844652f88b562285b26beef311a2c9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
2019-10-23 14:21:40 +00:00
Patrick Georgi 71e70130a1 Documentation: Fix typo
Change-Id: Ic208ae7ae38565cf97023adba3639fa12b83a21e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-22 12:46:23 +00:00
Patrick Georgi 91841af6b2 Documentation: Add proposal for a comprehensive image assembly stage
I originally put up this document for discussion in 2015
(mailing list: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/FXX4V2OSXAQC4B2VUENSFZEWRPPOVRH2/)
(doc: https://docs.google.com/document/d/1o2bFl5HCHDFPccQsOwa-75A8TWojjFiGK3r0yeIc7Vo/edit)

It may be time to revisit the way we define our image layouts now that
there are new fmap schemes for new vboot uses. The approach outlined in
this document may or may not be the right one, but it's something we
have, so let's discuss.

Compared to the doc, this will
 * be updated (things changed in the last 3.5 yearws)
 * integrate feedback to the doc and on the mailing list back then

Change-Id: Ib40d286e2c9b817f55e58ecc5c9bc8b832ac5783
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-21 14:18:17 +00:00
Arthur Heymans 194422af82 Documentation: Make sure ifdtool/index gets added to toctree
Change-Id: I57b37ebd3383e73a101511e303ad3beeb9d4ea31
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21 09:16:24 +00:00
Arthur Heymans 3e42dbac30 Documentation/writing_documentation.md: Fix typo
Change-Id: I18483332324ddfa45bc37a58c169901910e5a0cb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-21 09:16:03 +00:00
T Michael Turney 7783c606a4 sc7180: Provide initial SoC support
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-10-21 09:06:55 +00:00
Bill XIE 96ae7a3a2d mb/lenovo/x200: Add ThinkPad X301 as a variant
It is similar to X200s, with U-series CPU, slightly different gpio
setup, no docking support, and no superio chip.

Tested:
    - CPU Core 2 Duo U9400
    - Slotted DIMM 4GiB*2 from samsung
    - Camera
    - pci-e slots
    - sata and usb2
    - libgfxinit-based graphic init
    - NVRAM options for North and South bridges
    - Sound
    - Thinkpad EC
    - S3
    - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
      Linux payload (Heads) and Seabios.

TODO: repurpose and/or rename flag H8_DOCK_EARLY_INIT (introduced in
      CB:4294 ) for h8-using devices without a dock.

Change-Id: Ic6a6059ccf15dd2e43ed4fc490c1d3c36aa1e817
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-20 09:49:44 +00:00
Andrey Petrov ee0b7ad683 mainboard/ocp/monolake: Hide IIO root ports before memory init
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.

TEST=the patch was ran on affected HW and success was reported

Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-10-16 14:11:17 +00:00
Wim Vervoorn ea98989e2c Documentation/mainboard/facebook: Add rev 1.3
Add rev 1.3 of the fbg1701 board.

This adds Kingston memory.

BUG=none
TEST=none

Change-Id: Iaba6f28368e2e4ca412122b5fa28ed93c705f4df
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-10-16 14:09:26 +00:00
Patrick Rudolph 05bad430b6 soc/intel/common/block/sgx: Fix crash in MP init
On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.

To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.

Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.

Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.

Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-15 08:19:02 +00:00
Nicolas Reinecke b165c4a46f mainboard/lenovo/t410: Add new port
The port is based on the x201 / t410s.
2537-vg5 / i5, no discrete gpu

Tested and working:
* Native raminit
* Native gfxinit
* Booting Seabios 1.12.1
* Booting from EHCI
* Running GNU/Linux 5.0.0
* No errors in dmesg
* EHCI debug on the devices left side, bottom-right
* Keyboard
* Fn keys (Mute, Volume, Mic)
* Touchpad
* TPM
* Wifi
* Sound
* USB
* Ethernet
* S3 resume
* VBOOT

Testing in progress.

Untested:
* VGA
* Displayport
* Docking station

Bugs:
* AC adapter can't be read from ACPI
* TPM not working with VBOOT and C_ENV BB

Details for flashing externally:
1. Disconnect all power
2. Connect the external flasher
3. Connect the power cord (This fixes internal power control)
4. Remove the power cord

Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/11791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-15 06:47:48 +00:00
Nico Huber 465dd5c524 Documentation/gfx: Update support list of libgfxinit
Also get rid of some manual hyphenation.

Change-Id: Ibeb4eceeae48cf375171d0261ed9475010b0d5b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-10-14 19:33:22 +00:00
Elyes HAOUAS 495bb66541 src: Capitalize Super I/O
Change-Id: I9ad9294dd2ae3e4a8a9069ac6464ad753af65ea5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-10-07 19:18:36 +00:00
Patrick Georgi 64c14b5dcf Documentation/RFC: Drop obsolete doc
The format was retired 10 years ago when we moved to the new build
system, kconfig and sconfig. Retire the doc as well.

Change-Id: Ica1c353a80d411845b92038521d85ad5f3d359bc
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:08:55 +00:00
Patrick Georgi 11b3d2123f Documentation: Add our issue tracker to services
Change-Id: Ib249d5c6f2431336a01850f4a8d708795983e7d3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-07 01:08:40 +00:00
Patrick Georgi 0df412d8cc Documentation/mb: Link AMD mainboards directly in the big list
Fixes an issue with amd/index.md not being part of a toctree

Change-Id: Id419695d24a49951afb844c81cc0951d6920e0d2
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:08:26 +00:00
Patrick Georgi ad1fb31318 Documentation/mb/amd/padmelon: Fix relative link
Change-Id: I132aed69107153785c5e824108677e60243483ce
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:08:10 +00:00
Patrick Georgi 6a303185ef Documentation: remove invalid fragment type specifier
Change-Id: I1a07180532c6fa7c7ac487e39632438eef3b34e7
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:07:47 +00:00
Patrick Georgi f3df6fa9a7 Documentation: Fix typo
Change-Id: I832ff41a322081d3bae80df463659ec6ffffcd34
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:07:21 +00:00
Patrick Georgi 2528b9b4bf Documentation: start documenting our services
Change-Id: I4d687d13e8d47e3e3e6f319b9117d3c4f31caa78
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-07 01:07:06 +00:00
Patrick Georgi e0f150b171 Documentation: Update list of release notes
Change-Id: I963be1536be5155a114eef1149fdd8c5a067eff8
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-10-07 01:06:49 +00:00
Michael Niewöhner 258f52b520 mb/supermicro/x11-lga1151-series: rework documentation
This splits the x11-lga1151-series' documentation into a generic and a
board specific section as a preparation for CB:35427.

Additionally this adds some more information on the x11ssh board.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I40ddd0b5cce0b1a3306eae22fc0a0bc6b2a6263c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-10-04 16:24:59 +00:00
Mathew King c7ddc999fc ifdtool: Add validate option to ifdtool
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.

BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
     run 'ifdtool -t' with a bad bios image and verify expected issues

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03 15:28:15 +00:00
Richard Spiegel 5387144a93 Documentation/mainboard/amd: Add padmelon documentation and images
Create documentation on padmelon, including how to program the SPI. Also
include an index.md pointing to the documentation, as currently there's no
maiboard documentation folder for AMD.

BUG=none.
TEST=none.

Change-Id: I1a684c1acd3fb9441df71e2bc0fffa6131148b98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-01 15:15:30 +00:00
Richard Spiegel 6453c9062b Documentation/soc/amd: Add Family 15h
Create documentation for AMD Family 15h.

BUG=none.
TEST=none.

Change-Id: Iaab4edc431329a691283121494595f3797c566c6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-10-01 15:13:29 +00:00
Michael Niewöhner 0a6c62fbbe mb/supermicro: restructure x11ssh-tf to represent a x11 board series
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.

There are about 20 boards that can be added, if there is a community for
testing.

To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.

It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").

The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.

X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.

Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.

Documentation is reworked in CB:35547

Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-26 09:29:25 +00:00
Frans Hendriks ee8ca86dd6 Documentation/vendorcode: Add Eltan to vendor index
Eltan is missing in the vendor index.

Documentation of the eltan vendorcode is availlabe already.
Add eltan to vendor index.

BUG=N/A
TEST=N/A

Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-25 12:53:07 +00:00
Paul Menzel 3b99d6298e Documentation: Capitalize Super I/O
Change-Id: I6bfe11abc1b3763f3d6c390bbccd9191b417945d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-22 20:11:49 +00:00
Patrick Rudolph ee9a42af8e Documentation: X11SSH-TF update known issues
Change-Id: I5811fb829b45381ac19b2c3f2411c91f85b61d08
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-09-20 07:18:52 +00:00
Nico Huber 7f7ab8f16c Documentation/mainboard: Fix index
Remove duplicate headings, move vendor sections that were placed
amidst other vendor hierarchies, and while we are at it, sort it
alphabetically.

Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-20 07:16:15 +00:00
Patrick Georgi 3c599a2c08 Documentation: rename "Rookie guide" to "tutorial"
We generally try to stay away from ascribing attributes to (future)
devs. "Rookie guide" refers to the reader, while "tutorial" refers
to the material.

In the same spirit, move from "lessons" to "parts". It's not school :-)

Change-Id: I11a69a2a05ba9a0bc48f8bf62463d9585da043ec
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-16 21:17:33 +00:00
Patrick Georgi de2b6b8349 Documentation: minor grammar fixes
Change-Id: Iff6df888a293b525d436a5be215e8972ae2dd46a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-16 21:17:14 +00:00
Patrick Rudolph c162131d00 superio/common: Add ssdtgen for generic SuperIOs
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.

It generates a device HID based on the decoded I/O range.

Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.

Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
  resource settings on specific LDNs

Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-09-06 15:31:06 +00:00
Subrata Banik fb6ea0af40 Documentation/soc/intel/fsp: Add link for external FSP2.1 spec
Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-04 10:56:22 +00:00
Angel Pons bcbf2deb42 Documentation/coding_style.md: Update line length limit
Line length limit was bumped to 96 characters, but the coding style did
not reflect such a change.

Change-Id: Ifdbb8bc04e49e1fbe9b0c8a642ae814d5a60004a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-04 10:54:41 +00:00
Patrick Rudolph 5fffb5e30d security/intel: Add TXT infrastructure
* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled

The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.

Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-09-02 04:52:04 +00:00
Christian Walter 08aa502d79 mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
Add support for the X11SSH-TF which is based on Intel KBL.

Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init

Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common

For more details have a look at the documentation.

Please apply those patches as well for good user experience:

Ica0c20255f661dd61edc3a7d15646b7447c4658e

Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-09-01 22:18:38 +00:00
Raul E Rangel 7b2deddbb0 Kconfig: Write tmp files into same directory as target files
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.

Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.

BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.

Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30 10:42:29 +00:00
Tim Wawrzynczak 66e356c662 Documentation/acpi: Add new document on adding ACPI devices to devicetree
Change-Id: I9636e65f7d2499b06b1d71e5f8d09c528b850027
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-29 17:31:24 +00:00
Asami Doi a5d9e7a628 mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MB
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.

Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-26 07:15:06 +00:00
Jonathan Neuschäfer 3a4511eb6c arch/riscv: Enable FIT support
Tested on qemu-riscv.
Depends on OpenSBI integration and proper memory detection in qemu.

Boots into Linux until initrd should be loaded.

Tested on SiFive/unleashed:
Boots into Linux until earlycon terminates.

Change-Id: I5ebc6cc2cc9e328f36d70fba13555386bb8c29d6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30292
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-08 13:03:59 +00:00
Asami Doi f795242f26 mainboard/emulation/qemu-aarch64: Add new board for ARMv8
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.

To execute:
$ qemu-system-aarch64 -M virt,secure=on,virtualization=on \
  -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic

Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-08 01:12:06 +00:00
Kyösti Mälkki 3dddf4fb41 soc/intel: Obsolete mmap_region_granularity()
Change-Id: I471598d3ce61b70e35adba3bd983f5d823ba3816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-07 05:38:14 +00:00
Patrick Rudolph c4d56d668f Documentation: Advertise support for OpenSBI
Change-Id: Ie990bb95fcdcfab0246e8c694704022d9b8b5195
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-08-06 12:04:01 +00:00
Tim Wawrzynczak 25f9dcb685 Documentation/drivers: Fix typo in index.md
Change-Id: Ibf8f37d1e1223c5481cf1a40f08d4113bd80ed41
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-02 10:00:44 +00:00
Matt DeVillier b2e75d2d1d docs/distributions: remove entry for John Lewis' ROMs
John Lewis has updated his homepage to indicate he is no longer
producing coreboot images, nor supporting existing ones, so
remove the entry from the list.

Change-Id: I9b07cc4cb4adeb36eff1f904b23fb25da2c89c68
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-02 09:59:44 +00:00
Patrick Georgi 6664dd0208 Documentation/releases/checklist: Add instructions for crossgcc sources
We keep a mirror in case any of the originals disappear, but we also
have to remember to update it.

Change-Id: Ib4be91d1d508d3d5dba7ace1d167d8e528d58b3d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-30 22:30:58 +00:00
Patrick Georgi 544c124b79 Documentation/releases: Make sure lists look like lists in markdown
Add bullet points for to achieve that.

Change-Id: Iea6811147ddad4e6e3372ca1ccd8fdaf8bb5cb77
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-24 08:22:15 +00:00
Patrick Georgi e7c9781bdc Documentation/releases: Also mention RELOCATABLE_RAMSTAGE in deprecations
We plan to retire that symbol after 4.11 as well, with relocatable
ramstage becoming the normal mode of operation.

Change-Id: I36029215e5c8726f7dcc268bddc0d2b0161e3c40
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-24 08:22:04 +00:00
Patrick Georgi cebf57905b Documentation: Add 4.10/4.11 release notes
For 4.11 that's obviously just the release notes template.

Change-Id: I44c15bcaedf1367d745c533cc0a4acebdd2f812e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-07-22 23:33:57 +00:00
Patrick Georgi ad4641024a Documentation/code_of_conduct: Update arbitration team
Marc found more interesting things to do (yay, Marc!) and Martin
offered to volunteer on the arbitration board in his place.

Change-Id: Ic5bf00735afdf8942e543043238890011a82c890
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19 16:37:51 +00:00
Patrick Georgi 0feb983a1a Documentation/code_of_conduct: Emphasize definition of community org.
The paragraph starts talking about community organizers. By making
their definition a separate paragraph it's hopefully easier to find
what this means.

Change-Id: Icb9abbbd05b59bd4ee741d10f4c9c1a8c321b430
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19 16:37:36 +00:00
Patrick Georgi c52078fd01 Documentation/code_of_conduct: Highlight the reporting process
Make it a separate section, emphasize that people should get support
early, note that personal interaction and email are the two best
ways to seek help.

Change-Id: I8cb613fefe1a7b4db1ee948fb9927a38f0421011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-19 16:36:47 +00:00
Patrick Rudolph fa0ef81d15 Documentation: Add Intel TXT
Change-Id: I9e9606d0e4294ad3552ec3b3b44629f9e732d82b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-19 12:19:19 +00:00
Patrick Georgi 5865e3c4e1 Documentation/code_of_conduct: Assume the best as long as you can
"Always assume" is rather final and (in some readings) invalidates the
need for the rest of the text.

Change-Id: Ibf6f776494367d012ce69a64fa928c1dd4206c0e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-19 10:25:35 +00:00
Frans Hendriks ed52e3dd9c mainboard/portwell/m107: Do initial mainboard commit
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.

BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107

Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-17 14:21:52 +00:00
Angel Pons d472c4f01e Doc/lessons/lesson1: Fix title consistency
Make the title for lesson 1 match the format used for lesson 2 and the
lessons index, for consistency purposes.

Change-Id: I133d758ddf4974096cbf9f10ae96c148fc859efc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-16 15:01:11 +00:00
Patrick Rudolph 96d8e43178 Documentation: Add FSP bugs
As Intel doesn't even document known bugs add a list of
FSP bugs here.

Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-15 07:14:57 +00:00
Arthur Heymans b3af349284 soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INIT
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.

Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.

Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-10 10:14:39 +00:00
Patrick Rudolph c1b7e8a60b cpu/x86/pae/pgtbl: Add memset with PAE
To clear all DRAM on x86_32, add a new method that uses PAE to access
more than 32bit of address space.
Add Documentation as well.

Required for clearing all system memory as part of security API.

Tested on wedge100s:
 Takes less than 2 seconds to clear 8GiB of DRAM.
Tested on P8H61M-Pro:
 Takes less than 1 second to clear 4GiB of DRAM.

Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31549
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-02 08:45:50 +00:00
Vlado Cibic 2bf6a301d3 mainboard: Add support for ASUS P8Z77-M PRO desktop mainboard
Add support for ASUS P8Z77-M PRO desktop mainboard

Working:

- Tianocore and SeaBIOS boot
- PS/2 keyboard and mouse
- Audio
- S3 Suspend, shutdown and reboot
- USB2 / USB3
- Gigabit Ethernet
- SATA3, SATA2 and eSATA
- NVME
- CPU Temp sensors
- TPM
- Native raminit and also MRC
- PCIe GPU in all PCIe slots (16x/8x/4x) (linux)
- Integrated graphics with both libgfxinit and Intel Video OpROM
  (all connectors VGA/DVI-D/HDMI)

Signed-off-by: Vlado Cibic <vladocb@protonmail.com>
Change-Id: I47d24ac8b236f929c3160f9a769b971d83710f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-27 16:17:04 +00:00
Patrick Rudolph 1b35295ec2 security: Add memory subfolder
Add files to introduce a memory clearing framework.
Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by
platforms, that are able to clear all DRAM.

Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user
selectable to always clear DRAM on non S3 boot.

The function security_clear_dram_request tells the calling platform when
to wipe all DRAM. Will be extended by TEE frameworks.

Add Documentation for the new security API.

Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2019-06-27 10:02:04 +00:00
Piotr Kleinschmidt 2d6ed31cbd Documentation: Add PC Engines apu2
Describe how to run coreboot on the PC Engines apu2 mainboard.

Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581
Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-24 12:29:52 +00:00