CONFIG_MAINBOARD_PART_NUMBER sometimes contains spaces, but spaces
inside compat strings aren't nice, so let's convert all spaces to
dashes.
Change-Id: I46f2b2d7091782e04df5476e50698001511f664b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The previous settings caused the I2C frequency for the audio bus to be
too high, at 417kHz. The settings in this commit correct the frequency
to 396kHz.
BUG=b:119423345
Change-Id: Ibed886e6e1b0df4df6b87f6291e515364b3bf718
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
commit msg copied from
commit id: 64c9f1584c
The GPIO drivers in Windows and Linux for the Icelake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
Change-Id: I94fafd8af13cf229f5c467de5179aed021465739
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This reverts commit ad41f55123.
Reason for revert: <Issue have seen on EVT platform that vboot always fail to verify keyblock A>
BUG=b:121169122
Change-Id: I2790ef3463a228008b614498009fbdc8b493cfb0
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the BMC firmware module is installed on the KGPE-D16, the
RAM SPD multiplexer lines are disconnected by hardware from the
SP5100 GPIOs and attached to BMC GPIO lines instead.
Set the BMC GPIOs to match the state of the SP5100 GPIOs during
RAM setup.
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac5
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/19820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The device ID is documented in "Intel Xeon Processor E3-1200 v3
Product Family Datasheet volume 2" section 2.2.
Tested with ASRock H81M-HDS with Xeon E3-1271 v3. SeaBIOS payload can
find the boot devices, and GRUB payload can boot Debian GNU/Linux on
the SATA disk.
Change-Id: I999391c9bbc6b39526ad7aec8a6d8fe1a9b5f921
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Intel GMA ACPI opregion address needs to be set on S3 resume,
otherwise the Windows display driver fails to re-initialize correctly.
Fix by ensuring the address is set correctly regardless of display
init type used (GOP or VBIOS).
Test: build/boot on google/edgar, ensure internal display functional
following S3 resume under Windows 10.
Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Mirrors addition to Braswell SoC in commit d3d0f07.
Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Commit d80884ea5a ("mb/google/kahlee: Disable IOMMU") disabled the IOMMU
in all kahlee variants, but omitted the explaining comment only in
liara's devicetree.cb. Copy this comment to liara.
Change-Id: I564013a16217445003467e2a0579abd50597b205
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
They are hopefully stable enough by now.
TEST=Building with for emulation/spike-riscv with BUILD_TIMELESS,
with and without this patch, results in the same coreboot.rom.
Change-Id: Ie6747c7eeea6cd8fd2138c5ba535a08c5add9038
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Using ${...} in some places is slightly confusing.
Fixes: 395cbb4f97 ("mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetree")
Change-Id: Id0856a10d92786a41d45ca697945699f6f4c1f4c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bobba would prefer to use different SAR values per sku-id for regulatory
compliance. This commit uses the newly added interface for custom wifi
SAR CBFS filenames.
CQ-DEPEND=CL:*729429
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: I354382d651d65d533459f0ca460ca6fd6de547fd
Reviewed-on: https://review.coreboot.org/c/30223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using a fixed filename only allows for one SAR configuration to be
checked into CBFS. However, we have devices with shared firmware that
would desire separate SAR configurations. This change allows boards to
define a function to select one of multiple files stored in CBFS to be
used.
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: Ib852aaaff39f1e9149fa43bf8dc25b2400737ea5
Reviewed-on: https://review.coreboot.org/c/30222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It seems they are not included anywhere, Jenkins?
Change-Id: I629cdeb337fce381c69bd1ba0520e524ccdd90dd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/26756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
According to bard/ekko cpu types, PL2 need to set the values
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.
BUG=b:120874861
TEST=power on and check the DUT can boot up well
Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enaebl the RTC driver to be used on mc_apl4.
Change-Id: Ib8d2a9f6b8cea47cd10db4dfcc59eec1b21c7993
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This function returns APIC id for respective cpu core.
BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.
Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements board reset on the Cheza board. The real board
reset used by the operating system uses the PMIC, but unfortunately the
PMIC needs to be configured right for that to work. The PMIC
configuration currently happens in the Qualcomm blob (QcLib) that is run
from romstage, but vboot needs to be able to reboot during verstage
already. Porting all the PMIC initialization code to run in the
bootblock seems excessive (and at odds with the goal of doing as little
as possible before verification), so we'll just do a little hack and ask
the EC to perform a cold reset instead. For vboot purposes, this should
work just as well.
BUG=b:118501305
TEST=Hacked vboot code to call vboot_reboot(), confirmed that board
reset and came back up as expected.
Change-Id: I3858d95f481884a87c243d4fa3d6369c1e8a5a2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/29849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO pin map for CNL-H does not match with the OS expected
pin numbers. This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.
I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c
Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO drivers in Windows and Linux for the Cannonlake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
BUG=b:120686247
TEST=tested with write protect GPIO on sarien board. Before this
change the ACPI pin number was 220 which did not correspond to the
pin number in Linux. After this change the ACPI number is 303,
which maps to the correct GPIO in Linux. Now the GPIO value reported
by the kernel changes when the WP pin is toggled in hardware.
Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the generic GPIO library is enabled the code that generates the
GPIO table in ACPI should attempt to get the GPIO pin value from
the gpio_acpi_pin() function.
BUG=b:120686247
TEST=Tested on Sarien board to ensure that GPIO pin exported by
Chrome OS for the Write Protect signal is correct.
Change-Id: I267694b576009f79bacac6eda5f32bbf51742d78
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct Ram_ID=0b0000 SPD Module Part Number mismatch last alphabet 'C'
to "H5AN8G6NAFR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4f4b83589ad6b53c0a24f2637f0fe8b92a1168e3
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Correct to add Ram_ID=0b0001 SPD Module Part Number mismatch last alphabet 'C'
to "H5ANAG6NAMR-UHC".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I4d320b2e10c4865456a9a9ccb400db5dd9256b3e
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30177
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Creating skeleton files and directories in mainboard for the new Hatch
board. This is to facilitate development for different parties
involved.
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/30169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I64e79904c7ad95091ea29d9f80444c4e3b493471
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update the TRACKPAD_INT1_1V8_ODL GPIO configuration so that it acts as a
wakeup source
BUG=b:119598593
BRANCH=octopus
TEST=Ensure that the system wakes up on trackpad events. Ensure that the
suspend_stress_test runs successfully for 25 iterations.
Change-Id: I28292682cf9c8037abb87d265e49a60139550db2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/30171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change-Id: I15cfbbab15b940641c3952f2cfb4b11c37574816
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/29299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Disable SATA port 0 and port 1 as that's not used as SATA on platform.
BUG=N/A
TEST=Build and boot up fine on google arcada board.
Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
There are 2 vendor BIOS's for the Lenovo X200 with the difference being the
settings in the VBT blob to accommodate different backlight frequencies.
Linux however sticks with the setting set by the firmware.
Tested on Lenovo X200 with CCFL backlight.
Change-Id: I4c4a7011ce03cdd511fa2e2160c2f006ba2707ba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29904
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PEN_EJECT GPIOs are active high and also require an internal pull-up.
Update the GPIO configuration appropriately.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the stylus
tools open on pen eject. Ensure that the system can enter S0ix and S3
states successfully when the pen is inserted. Ensure that the system
wakes on Pen Eject. Ensure that the system does not enter S0ix and S3
states when the pen is placed in its holder. Ensure that the
suspend_stress_test runs successfully for 25 iterations with the pen
placed in its holder.
Change-Id: Ibf9cb214a8ce7561efbb77a7e99d1e386cf064c3
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add mechanism to configure GPE wake event which in turn can be used as ACPI
Power Resources for Wake
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the wake GPE event is added to ACPI Power Resource for
Wake.
Change-Id: Iacc12b8636aaac98a8689a211cbe1dcfe306f342
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update the GPIOs for the next board build. Mostly minor changes but
the polarity change on GPP_E8/RECOVERY on sarien will result in it
booting to recovery every time unless using new hardware.
For this reason the recovery mode GPIO that is passed to vboot is
commented out for sarien. It is only used for testing and currently
it is useful to have an image that works on both board versions.
Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30062
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.
This affects the display-related SOC pads with the following UPD variables:
UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17
Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.
This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg
As well as the current top-of-tree for the FSP sources.
BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel
Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Synaptics Trackpad wake event is incorrectly routed to GPE0_DW2_02. The
concerned GPIO is not connected and hence wont trigger a wakeup. Fix the
GPE wake configuration for synaptics trackpad.
BUG=b:120666158
BRANCH=octopus
TEST=Ensure that the wake on trackpad works with Synaptics touch pad.
Ensure that the system can enter S0ix successfully(run
suspend_stress_test -c 25).
Change-Id: I87b8c266266280f61700839d428e6f8938b0f72f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30105
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP defined a special clock source usage 0x70 for PCH LAN device, update
that to google sarien platform.
BUG=b:120003760
TEST=Boot up into OS, ethernet able to be listed in ifconfig.
Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Part Number
Correct Ram_ID=0b0011 SPD Module Part Number to "MT40A1G16KNR-075:E" from
"4ATS1G64HZ-2G6E1".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I9d582b3753de9a48865eb6eca7e4fbdb31b799ff
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Number
Correct Ram_ID=0b0000 SPD Module Part Number to "H5AN8G6NAFR-UH" from
"HMA851S6AFR6N-UH".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I1f6e885638589a35334a9a8f905af4877c5d1f91
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Part Number
Correct Ram_ID=0b0010 SPD Module Part Number to "MT40A512M16JY-083E:B"
from "4ATF51264HZ-2G3B2".
BUG=b:120000816
BRANCH=master
TEST=mosys memory spd print all
Change-Id: I6847a55968260cdbc1588ddeb8d23c515ad87920
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/30050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Intel Sensor Hub was enabled on the wrong variant so this change
moves the enable from sarien to arcada.
Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A new liara specific VBIOS updating eDP power sequence is available now,
Change Kconfig to use it if board is google liara.
BUG=b:120534087
TEST=Build liara, booted, tested eDP test compliance.
Change-Id: I444cfa0bd755480e006f11c0d692b25b96129c29
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/30090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Recently there has been a change to print ME version. But the stage at
which the version is printed causes the HECI device to remain in D0 state.
This in turn prevents the SoC from entering S0ix state.
This change moves printing ME version a little earlier so that the HECI
device is put into D0i3 state by FSP and the SoC can enter S0ix state
successfully.
BRANCH=octopus
BUG=b:120571529
TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that
the device boots to ChromeOS. Ensure that the device enters S0ix
successfully(using suspend_stress_test -c 25).
Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use CONFIG_CPU_MAX which defaults to 1 instead of CONFIG_RISCV_HART_NUM.
The default value of CONFIG_RISCV_HART_NUM was 0 and cause a jump to address 0.
Add a die() call to fail gracefully.
Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/29993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Correct a build error that occurs when HUDSON_UART is selected.
Replace sizeof() of a nonexistent variable with the intended type.
This was introduced in
bd48b23 "southbridge//hudson: Get rid of void pointer math".
BUG=b:118484178
TEST=Build Bettong with Chipset/"UART controller for Kern"
Change-Id: Icc0ff9d80c3f5cab9ab837cf1cd0cd8eb0753284
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The code annotated by the comment is dealing with root port 7, so update
the comment to reflect that. It looks like the comment was copied from
the root port 3 case, but not updated.
Change-Id: I0e27e4453f4c3b2b1b9dffb0c89b71373c6b303e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The code is based on autoport and that for T430s
Tested:
- CPU i5-3337U
- Slotted DIMM 2GiB
- Soldered RAM 4GiB from samsung (There may be more models here)
- Camera
- pci-e and usb2 on M.2 slot with A key for wlan
- sata and usb2 (no superspeed components) on M.2 slot with B key for wwan
- On board SDHCI connected to pci-e
- USB3 ports
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- Sound
- Thinkpad EC
- S3
- TPM1 on LPC
- EHCI debug on SSP2 (USB3 port on the left)
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
Linux payload (Heads), Seabios may also work.
Not tested:
- Fingerprint reader on USB2 (not present on mine)
- Keyboard backlight (not present on mine)
- "sticky_fn" flag in nvram
Not implemented yet:
- Fn locking in nvram (may not be identical to "sticky_fn")
- C-based native graphic init (since T431s has eDP instead of LVDS)
- Detecting the model of Soldered RAM at runtime, and loading the
corresponding SPD datum (3 observed) from CBFS (the mechanism may be
similar to that on x1_carbon_gen1 and s230u, but I do not know how
to find gpio ports for that, and SPD data stored in vendor firmware.)
Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Provide rise/fall times as measured on existing boards. This will
need adjusted for new boards but provides a starting point that
makes I2C clocks look reasonable.
Tested by measuring I2C bus speed and rise/fall times with a scope.
Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add an entry to the soc_clock table for a 216MHz clock so that
the I2C controller clock is calculated correctly when the I2C
bus is used in coreboot.
This was tested by measuring the I2C clock speed on H1 I2C bus
on a sarien board in coreboot and ensuring it is ~400KHz.
Change-Id: I6c3cacdad318a5ce41bc41e3ac81385c2d4f396c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The input clock for the I2C controllers was set at 133MHz but should
really be 216MHz according to the kernel:
https://patchwork.kernel.org/patch/10408729/
"Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C."
This change was tested on a sarien board where an I2C trackpad that was
measuring ~700MHz on I2C and is now measuring ~380MHz.
Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of the memory mapped BIOS region is covered by SRAM, check
that CBFS always fits the effectively mapped region of flash. This
is usually taken care of by reserving the SRAM range in the FMAP
(e.g. as BIOS_UNUSABLE), but can be missed.
Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Re-write the UAO handling code as it had stopped working (#171)
(the flag was not getting read from the RTC properly in SMM)
Remove the SMM code as it's not needed (but EC flag won't be set
upon entering S3 now)
Set the EC flags on boot the same way other flags are set
Document bitwise operators for clarity
Propagate changes to other Thinkpads
(updated X201 to have 2 bits for the flag as it only had 1)
Per Nicola Corna's previous commits, 0x0d is set for "AC only"
"AC only" does exhibit different behaviour - the USB port is
turned on a few seconds after entering S3, rather than < 1 sec,
regardless of AC status
Tested on X220
Change-Id: If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested - Lenovo t520 still builds fine with this patch.
Change-Id: I82492c071ca760f0790b992acbdb86021f470cfe
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fix some compiler warnings due to pointer to integer conversions
with different size.
Required for 64bit ramstage.
Change-Id: Ibfb3cacf25adfb4a242d38e4ea290fdc3929a684
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/29875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is needed so the next patch can set up GPIOs before
AGESA runs.
BUG=b:120436919
TEST=Verified romstage mainboard code runs before AGESA
Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30038
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platform have a 32MB SPI chip, so we can increase the bios region from
16MB to 28MB.
BUG=b:119267832
TEST=Build and boot fine on sarien platform.
Change-Id: I9bc0fa0f662e5ec64e77f2005dbb2e7edb8b2524
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
AMD traditionally claims the resource at I/O port 61 for the onboard
PC-AT speaker. In later designs, the speaker may be omitted in favor
of routing the SPKR signal to the codec.
Some systems implement neither, and for those it is not correct to
identify the resource as a speaker. Modify the EISAID reported to
the OS depending on the system design. The default is that port 61
is reported as reserved. In order to report a speaker, add #define
in mainboard//dsdt.asl.
TEST=check /proc/ioports and iasl -d for both ways using a Grunt
BUG=b:117818432
Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When building grunt with flags set to detect variables that get a value but
then are unused, there are 5 instances that causes error (unused variable).
In most cases it's enough to simply remove the variable. Other instances,
is better to simply use the variables (one instance it's a return value, on
the other instance using the variables makes code more readable).
BUG=b:120260448
TEST=Build and boot grunt.
Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29985
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sort mainboard-specific defines in the same order as in all other Lenovo
boards. This is a purely cosmetic change which just makes diff between
boards smaller.
Change-Id: I4e379bb727b356fc6010e93de492f6d73f97a750
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Most Lenovo mainboards define their own specific defines in dsdt.asl.
Let's make it consistent across all Lenovo mainboards.
Tested - builds fine.
Change-Id: I03fbeb09b25e42af2dfbb220c0f726e6abb73673
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
