Commit graph

93 commits

Author SHA1 Message Date
Patrick Georgi
e82618d037 Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 14:50:12 +00:00
Myles Watson
24a5213a39 Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5875 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28 16:16:58 +00:00
Warren Turkal
e0afe735a0 All these boards already had the CACHE_AS_RAM option in their individual
configs. I just moved it the the CPU that they all use.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5871 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:18:26 +00:00
Uwe Hermann
5df4168db8 Drop some useless "../../../" in #includes (trivial).
Build-tested using abuild.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5844 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25 16:17:20 +00:00
Uwe Hermann
b015d02a85 Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.
Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.

Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-24 18:18:20 +00:00
Uwe Hermann
8fa90ec274 Cut the crap.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 21:16:27 +00:00
Marc Jones
3f1d29c408 IEI Kino added to IEI mainboard Kconfig. I missed this in r5812
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 19:31:21 +00:00
Marc Jones
738347e7c3 IEI Kino mainboard support based on Mahogany Fam10.
svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch.

Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 19:24:38 +00:00
Aurelien Guillaume
34697d67c1 Set up an arbitrary amount of system memory on Geode LX, so
coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.

Move RAMBASE to the default of 1MB for the affected boards

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-07 07:43:10 +00:00
Stefan Reinauer
704b59662d We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 17:53:13 +00:00
Jens Rottmann
9a684fcb0f Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block.  This makes it possible to
define user visible board specific options.  Moved all vendor names and PCI
ids to the vendors' Kconfigs.  Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if".  Sorted boards
(sort -d), cleaned whitespace.

This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used.  It it simply needed to have something to attach
the boards' "select" statements to.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:36:51 +00:00
Myles Watson
78265d5609 Remove unused mainboard_config definitions. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 18:24:04 +00:00
Stefan Reinauer
8c4f31b3b5 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /
board porter: printk should always be available in CAR mode.

Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
but it's not been used there. Very odd.

There is one usage of CONFIG_USE_INIT which was always off in 
src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
those few lines.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-03 15:42:29 +00:00
Edwin Beasant
eb50c7d922 Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06 21:05:04 +00:00
Edwin Beasant
f333ba0958 This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-10 15:24:57 +00:00
Nils Jacobs
dd6ad3447b license header fixes
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:48:05 +00:00
Patrick Georgi
bf9e5384d7 Remove pc80/serial.c includes in ROMCC boards and include
it centrally in console/console.h instead.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-09 21:09:58 +00:00
Patrick Georgi
12584e2bd2 Drop console/console.c and pc80/serial.c from mainboards'
romstage.c.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-08 09:14:51 +00:00
Patrick Georgi
8d313685b0 Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster"
in device trees. Adapt sconfig as necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-05 13:12:42 +00:00
Stefan Reinauer
14e2277962 Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:56:47 +00:00
Stefan Reinauer
9839cbd53f * clean up all but two warnings on artecgroup dbe61
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
  on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
  to life)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-21 20:06:10 +00:00
Myles Watson
4839e2c495 Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix some white space.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-08 15:06:44 +00:00
Stefan Reinauer
0c781b2694 - get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()"

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-01 09:50:32 +00:00
Stefan Reinauer
5a1f597085 This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.

While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
  from romcc)

Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code 
		in cache_as_ram.inc)

Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31 14:34:40 +00:00
Stefan Reinauer
798ef2893c This drops the ASSEMBLY define from romstage.c, too
(since it's not assembly code, this was a dirty hack anyways)
Also run 
    awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
    mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c 
cut some holes into the source.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29 22:08:01 +00:00
Stefan Reinauer
5e32823a68 __PRE_RAM__ is now correctly specified in the Makefile. No need to hack it into
romstage.c anymore

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5315 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29 19:19:16 +00:00
Patrick Georgi
37bdb87fab - make HAVE_HARD_RESET match what newconfig did
- introduce BOARD_HAS_HARD_RESET and use it if a board provides
hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component
- move a couple of rules out of the mainboards' Makefiles into
src/arch/i386/Makefile.inc:
	initobj-y += crt0.o
	obj-y += mainboard.o
	obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
	obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
	obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o
- remove Makefile.incs that are empty (or comment-only) after these
changes, incl. Makefile.romccboard.inc (and references to it)
- Make include not fail if Makefile.inc doesn't exist.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-27 08:39:04 +00:00
Patrick Georgi
31b0bea940 Move the ldscripts logic to src/arch/i386/Makefile.inc
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-25 21:50:26 +00:00
Patrick Georgi
eb49f9d04f Unify crt0s setup to src/arch/i386/Makefile.inc. This variable
is not something users have to concern themselves with anymore.

Also fixes some wrong romstrap configs for boards, fixing a couple
of them.

Also add "make printcrt0s" target for debugging crt0s when updating
modified checkouts.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5162 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-25 17:03:17 +00:00
Patrick Georgi
8dc4b933b1 Only handle code as "driver" that actually uses our driver
infrastructure (special linking, data structures, etc)

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-23 16:54:20 +00:00
Patrick Georgi
2063197a4f Move all the copies of the romstage.inc rule to
src/arch/i386/Makefile.inc

For that to work, I had to:
- Add a CONFIG_ROMCC variable
- Set that variable on all ROMCC boards
- conditionally choose romcc or gcc rule based on that variable
- remove those two rules from all the boards' Makefiles
- switch a couple of boards to HAVE_OPTION_TABLE, as they actually have.

Also remove the duplication of rules with the sole difference of if
they depend on option_table.h or not.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-09 12:21:10 +00:00
Stefan Reinauer
38f147ed3d janitor task: unify and cleanup naming.
cache_as_ram_auto.c and auto.c are both called "romstage.c" now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-08 12:20:50 +00:00
Stefan Reinauer
d51eddbb66 fix further build.h dependencies that were undetected before we enabled it on
our parallel build server ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5091 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 22:56:06 +00:00
Patrick Georgi
abf2ad716d newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 21:43:48 +00:00
Stefan Reinauer
04d74b1fdd Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.
This automatically adds the settings for those boards that didn't have settings
at all yet. Also, small fixup to compareboard.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

--> Please help porting all boards from newconfig to Kconfig <--

This is a lot of janitor work and we can use your helping hands.
The sooner we can get rid of Kbuild, the better. The KBuild report
on the mailing list shows the config differences between newconfig
and Kconfig. In theory, all Kconfig configs should be equal to their
newconfig pendant. In practice it's better to come close but stay 
clean.

--> Please help porting all boards from newconfig to Kconfig <--



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 01:32:43 +00:00
Stefan Reinauer
e37785791a * fix crt0s/ldscripts paths to fix out of tree build.
* fix iasl output directory for i945 boards (patch
  for moving it to the mainboard directory will follow)
* coreboot_table.c: lb_mainboard can be static
* coreboot_table.c: dump memory table in debug and spew mode
* fix a warning in bootblock.c
* don't include arch/i386/init in arch/i386/Makefile.inc
* announce generation of crt0_includes.h
* allow overriding $(obj)
* drop unused src_types from Makefile
* correctly use hostname -s instead of hostname for COMPILE_HOST

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5065 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-30 09:47:18 +00:00
Patrick Georgi
e8d943f266 Fix ACPI build on a couple of boards (now that it's active)
Fix timer handling on amd/sc520 systems
Match UDELAY_* configuration of newconfig in Kconfig

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 15:17:11 +00:00
Patrick Georgi
29647d97c5 Align several kconfig options to match newconfig:
HT_CHAIN_UNITID_BASE
HT_CHAIN_END_UNITID_BASE
SB_HT_CHAIN_ON_BUS0
SB_HT_CHAIN_UNITID_OFFSET_ONLY
MAX_CPUS
MAX_PHYSICAL_CPUS
ROM_SIZE
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2

Also hook up asus/p2b-ds

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5051 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 07:56:01 +00:00
Stefan Reinauer
9fe4d797a3 coreboot used to have two different "APIs" for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)

read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.

This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 17:53:38 +00:00
Stefan Reinauer
a0c68f864e * Explicitly add __PRE_RAM__ where it should be added.
* Don't implicitly add __PRE_RAM__ in romcc. 

Fixes intel/xe7501devkit

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-05 13:03:02 +00:00
Myles Watson
123a684ce6 Fix iei/pcisa-lx-800-r10. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4865 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 21:41:06 +00:00
- supermicro/x6dhe_g/auto.c
d1327ce963 Major cleanups of the hard_reset() code and config in coreboot.
- Drop unused "#object reset.o" entries.

 - Use CONFIG_HAVE_HARD_RESET for all "object reset.o" entries.

 - Drop dead/commented code, i.e. useless hard_reset() from:
   - supermicro/x6dhe_g/auto.c
   - supermicro/x6dhe_g2/auto.c
   - supermicro/x6dhe_g2/auto.updated.c
   - supermicro/x6dhr_ig/auto.c
   - supermicro/x6dhr_ig2/auto.c
   - digitallogic/msm586seg/auto.c
   - dell/s1850/auto.c

 - Add "obj-$(CONFIG_HAVE_HARD_RESET) += reset.o" to kconfig files of boards
   that actually have a reset.c file.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4849 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 19:17:24 +00:00
Uwe Hermann
4e015eb674 Fix all board names in Kconfig as per wiki / vendor website.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-20 13:55:35 +00:00
Uwe Hermann
7f30050939 Drop a duplicated implementation of failover.c.
Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-18 18:27:42 +00:00
Peter Stuge
d08be7eecd Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 15:01:00 +00:00
Uwe Hermann
d65509de14 Set default ROM sizes per-board to match the ROM chip that came
with the respective board.

Of course, the user can still override the size in menuconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 17:37:20 +00:00
Myles Watson
b8e2027be8 Add CONFIG_GENERATE_* for tables so that the user can select which tables not
to build, but by default all the tables that are available are built.

Make PIRQ table build for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 13:35:47 +00:00
Uwe Hermann
748475b800 More kconfig cleanups:
- Use "default n" for all components that shall be "select"ed.

 - Use "0x0" instead of "0" for hex variables for clarity and to reduce
   the risk of people passing integer instead of hex values to such variables.

 - Add TODO comments for boards that have irq_tables.c but don' set
   CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling.

 - ASUS M2V-MX SE doesn't have irq_tables.c so don't define
   IRQ_SLOT_COUNT in its Kconfig file.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 11:47:21 +00:00
Patrick Georgi
98402455c5 More kconfig:
AMD LX
AMD SC520
boards by iei, pcengines, technexion, technologic, thomson

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 14:31:56 +00:00
Uwe Hermann
95313d824d Major CONFIG_IRQ_TABLE_COUNT fixing and cleanups. Some of these boards
and PIRQ tables were actually wrong, I cannot imagine they ever
worked properly.

 - Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
   hard-coded numbers.

 - Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.

 - Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
   in the irq_tables.c file.

 - Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
   boards where they were set to 0 (in order to be overridden in
   the respective targets/.../Config.lb).

   This is mainly done to aid Patrick's scripts for kconfig conversion.

 - Fix a number of comments in irq_tables.c files.

 - Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
    - tyan/s1846
    - asus/a8v-e_se
    - asus/m2v-mx_se

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 21:51:33 +00:00