Lock down several HD Audio registers by setting the HDCFG.BCLD bit.
Tested on Asrock B85M Pro4, the GCAP register becomes read-only.
Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This bit is hardwired to 1 (Intel High Definition Audio mode).
Change-Id: I3683497c5e2446f1d8319037583890b5d0a8a95c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This allows dropping the SOC_INTEL_COMMON selection. Pull in the options
selected by SOC_INTEL_COMMON into Broadwell Kconfig as they still apply.
Change-Id: I0dd7de5358667240b0b3c1a550ba373a2a5af7d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.
Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.
Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.
Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now every AML package had to be closed using acpigen_pop_len().
This commit introduces set of package closing functions corresponding
with their opening function names. For example acpigen_write_if()
opens if-statement package, acpigen_write_if_end() closes it.
Now acpigen_write_else() closes previously opened acpigen_write_if(),
so acpigen_pop_len() is not required before it.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Icfdc3804cd93bde049cd11dec98758b3a639eafd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add I2C initialization in romstage and ramstage.
TEST=To test the I2C connection on Majolica, which doesn't have SPD
connection, call the function below after i2c_soc_init is called.
i2c_read_bytes(2, 0x4d, addr, data, 1);/* Read out 1 byte one time */
It can get the register values of TMP432B.
Or
/* Override EC port in ec.h */
#define EC_DATA 0x662
#define EC_SC 0x666
ec_write(0xA9, 0x40);
i2c_read_bytes(1, 0x10, addr, data, 2);/* Read out 2 bytes one time */
It can get the register values of CM32181A3OP(ALS).
Change-Id: I3a2a1494b44b68e8d8204fba0c90e769e0256e6f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51029
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add macros, settings and callbacks to support I2C for cezanne.
Change-Id: Ic480681d4b7c6fb8591e729090e4faeb5fccf800
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.
Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C driver is replicated in each generation of AMD SoCs. Introduce a
common I2C driver that can be used across all the AMD SoCs. To begin
with, peripheral reset functionality is moved into this common driver.
SoC specific I2C driver passes the SCL pin configuration in order for
the common driver to reset the peripherals. More functionality can be
moved here in subsequent changes.
Also sb_reset_i2c_slaves() is renamed as sb_reset_i2c_peripherals() as
an effort towards using inclusive language.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz.
localhost ~ # i2cdetect -y 0
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: 50 51 -- -- -- -- -- -- 58 59 -- -- -- -- -- --
60:
70:
localhost ~ # i2cdetect -y 1
Warning: Can't use SMBus Quick Write command, will skip some addresses
0 1 2 3 4 5 6 7 8 9 a b c d e f
00:
10:
20:
30: -- -- -- -- -- -- -- --
40:
50: UU -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
60:
70:
Change-Id: I9f735dcfe8375abdc88ff06e8c4f8a6b741bc085
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set the PCU locks as indicated by the BWG.
Lock the following:
P_STATE_LIMITS
PACKAGE_RAPL_LIMIT
SAPMCTL
DRAM_PLANE_POWER_LIMIT
CONFIG_TDP_CONTROL
Change-Id: I5f44d83e2dd8411358a83b5641ddb4c370eb4e84
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51505
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the SMI_LOCK to post SMM setup. Also, use the correct access
method for SMI_LOCK. GEN_PMCON_A is in PCI config space and not
in MMIO space on this PCH.
Change-Id: Ibbb183ef61ca7330198c1243ecfc2d4df51e652b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51452
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This macro is unused and its value is often wrong. Drop it.
Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is currently only used in this translation unit.
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib779a38306fb45320f3e4eb71f63630023d59906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51535
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All platforms implement those and using a no-op function is not
expected, so it is better to fail the build if the soc specific code
is not implemented.
Change-Id: Id946f5b279dcfa6946381b9a67faba6b8c1ca332
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51522
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are currently writing invalid ACPI tables. We are missing the GPP
ACPI names. There is an assert in acpi_device_write_pci_dev that checks
to see if we have a scope, but by default asserts don't halt, so we were
writing a NULL scope.
BUG=b:171234996
TEST=Boot majolica and dump ACPI tables
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6a861ad1b9259ac3b79af76e18a9354997b0491e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In pursuit of the goal of eliminating the proliferation of raw region
devices to represent CBFS files outside of the CBFS core code, this
patch removes the get_spd_cbfs_rdev() API and instead replaces it with
spd_cbfs_map() which will find and map the SPD file in one go and return
a pointer to the relevant section. (This makes it impossible to unmap
the mapping again, which all but one of the users didn't bother to do
anyway since the API is only used on platforms with memory-mapped
flash. Presumably this will stay that way in the future so this is not
something worth worrying about.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch rewrites some parts of the Agesa refcode loader to eliminate
the passing of raw rdevs between functions, so that we can get rid of
cbfs_boot_locate() in favor of more high-level APIs.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2a6e1158ed7425c69c214462bc52e8694a69997a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In pursuit of the eventual goal of removing cbfs_boot_locate() (and
direct rdev access) from CBFS APIs, this patch replaces all remaining
"simple" uses of the function call that can easily be replaced by the
newer APIs (like cbfs_load() or cbfs_map()). Some cases of
cbfs_boot_locate() remain that will be more complicated to solve.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The CBFS stage header is part of the file data (not the header) from
CBFS's point of view, which is problematic for verification: in pre-RAM
environments, there's usually not enough scratch space in CBFS_CACHE to
load the full stage into memory, so it must be directly loaded into its
final destination. However, that destination is decided from reading the
stage header. There's no way we can verify the stage header without
loading the whole file and we can't load the file without trusting the
information in the stage header.
To solve this problem, this patch changes the CBFS stage format to move
the stage header out of the file contents and into a separate CBFS
attribute. Attributes are part of the metadata, so they have already
been verified before the file is loaded.
Since CBFS stages are generally only meant to be used by coreboot itself
and the coreboot build system builds cbfstool and all stages together in
one go, maintaining backwards-compatibility should not be necessary. An
older version of coreboot will build the old version of cbfstool and a
newer version of coreboot will build the new version of cbfstool before
using it to add stages to the final image, thus cbfstool and coreboot's
stage loader should stay in sync. This only causes problems when someone
stashes away a copy of cbfstool somewhere and later uses it to try to
extract stages from a coreboot image built from a different revision...
a debugging use-case that is hopefully rare enough that affected users
can manually deal with finding a matching version of cbfstool.
The SELF (payload) format, on the other hand, is designed to be used for
binaries outside of coreboot that may use independent build systems and
are more likely to be added with a potentially stale copy of cbfstool,
so it would be more problematic to make a similar change for SELFs. It
is not necessary for verification either, since they're usually only
used in post-RAM environments and selfload() already maps SELFs to
CBFS_CACHE before loading them to their final destination anyway (so
they can be hashed at that time).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8471ad7494b07599e24e82b81e507fcafbad808a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since prog_locate() was eliminated, prog_rdev() only ever represents the
loaded program in memory now. Using the rdev API for this is unnecessary
if we know that the "device" is always just memory. This patch changes
it to be represented by a simple pointer and size. Since some code still
really wants this to be an rdev, introduce a prog_chain_rdev() helper to
translate back to that if necessary.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If7c0f1c5698fa0c326e23c553ea0fe928b25d202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
Test=Verified on Alderlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6779f4a9e140deebf7f3cecd9fc5dac18813f246
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch removes the prog_locate() call for all instances of loading
payload formats (SELF and FIT), as the previous patch did for stages.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I582b37f36fe6f9f26975490a823e85b130ba49a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes the prog_locate() step for stages and rmodules.
Instead, the stage and rmodule loading functions will now perform the
locate step directly together with the actual loading. The long-term
goal of this is to eliminate prog_locate() (and the rdev member in
struct prog that it fills) completely in order to make CBFS verification
code safer and its security guarantees easier to follow. prog_locate()
is the main remaining use case where a raw rdev of CBFS file data
"leaks" out of cbfs.c into other code, and that other code needs to
manually make sure that the contents of the rdev get verified during
loading. By eliminating this step and moving all code that directly
deals with file data into cbfs.c, we can concentrate the code that needs
to worry about file data hashing (and needs access to cbfs_private.h
APIs) into one file, making it easier to keep track of and reason about.
This patch is the first step of this move, later patches will do the
same for SELFs and other program types.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia600e55f77c2549a00e2606f09befc1f92594a3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The i2c actiming with the default reg setting cannot meet spec,
so we need to set some regs.
1. adjust the ratio of SCL high and low level, to adjust "tLOW".
2. modify ext_conf reg to adjust "tSU,STO".
BUG=b:179000159
TEST=Test on asurada (MT8192), boot pass,
timing pass.
Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Ifbe97edbc38972af5b782fb93342ee0616127dd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51024
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop the 100ms delay in the _PS0 method because kernel already adds this
100ms. This change also drops polling TBT PCIe root ports Link Active
State because this scheme is not applicable for SW CM.
BUG=None
TEST=Built Alderlake coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I792d3c8ca4249ed74d4090ec1efba5a180429c75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no PCI host interface for this version of CNVi BT.
CNVi BT on Tigerlake is an USB device.
Change-Id: Ib71a827c36dfac55c3e5ce586b00a26fc6264464
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no PCI host interface for Cnvi BT in Alderlake.
CNVi BT on Alderlake is an USB device.
Change-Id: I3e08c6d6f00e81267dc28c9b37b2dfff5cd75db1
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51352
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP has added the Cnvi BT Core enabling in addition to the existing
CnviMode. This change adds the flag at the soc config side (i.e.
soc_intel_tigerlake_config for devicetree). Also, there is no longer PCI host
interface for BT. Therefore, BT core should not use the pci port status to turn
on/off.
TEST: BT enumeration is checked using 'lsusb -d 8087:0026' from OS to make
sure BT is turned on.
Change-Id: I71c512fe884060e23ee26e7334c575c4c517b78d
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
making the symbols common accross targets to avoid duplicates for each soc.
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: Ic60f46891dfadc7db5ece02756cb449aacdd63c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
I was bugged by spurious "Failed to enable LTR" messages for years.
Looking at the the current algorithm, it is flawed in multiple ways:
* It looks like the author didn't know they implemented a
recursive algorithm (pciexp_enable_ltr()) inside another
recursive algorithm (pciexp_scan_bridge()). Thus, at every
tree level, everything is run again for the whole sub-
tree.
* LTR is enabled no matter if `.set_ltr_max_latencies` is
implemented or not. Leaving the endpoints' LTR settings
at 0: They are told to always report zero tolerance.
In theory, depending on the root-complex implementation,
this may result in higher power consumption than without
LTR messages.
* `.set_ltr_max_latencies` is only considered for the direct
parent of a device. Thus, even with it implemented, an
endpoint below a (non-root) bridge may suffer from the 0
settings as described above.
* Due to the double-recursive nature, LTR is enabled starting
with the endpoints, then moving up the tree, while the PCIe
spec tells us to do it in the exact opposite order.
With the current implementation of pciexp_scan_bridge(), it is
hard to hook anything in that runs for each device from top to
bottom. So the proposed solution still adds some redundancy:
First, for every device that uses pciexp_scan_bus(), we enable
LTR if possible (see below). Then, when returning from the bus-
scanning recursion, we enable LTR for every device and configure
the maximum latencies (if supported). The latter runs again on
all bridges, because it's hard to know if pciexp_scan_bus() was
used for them.
When to enable LTR:
* For all devices that implement `.set_ltr_max_latencies`.
* For all devices below a bridge that has it enabled already.
Change-Id: I2c5b8658f1fc8cec15e8b0824464c6fc9bee7e0e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel ADL BIOS specification #627270 recommends reserving the
following resources for each PCIe TBT root port:
- 42 buses
- 192 MiB Non-prefetchable memory
- 448 MiB Prefetchable memory
Add a mainboard Kconfig which will auto-select these recommended values,
in addition to PCIEXP_HOTPLUG.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51460
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common pcie
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iee25a77bf5cc6636f46a5c32f3eeabe8524e0a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The _DSD is generated at runtime using the Intel common USB4
driver, therefore remove it from the ASL files.
BUG=b:182522802, b:182478306
TEST=boot into latest kernel, no thunderbolt driver errors
seen
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I77dc283aeb5f52191255137e941487cf68cb7970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8192 devapc supports remapping domains.
There may be different domain bit for different subsys.
For example, domain bit in INFRA is 4-bit, while in MMSYS,
domain bit is 2-bit. For INFRA master to access MM registers,
the domain bit will change from 4 to 2 and need to be remapped.
In this patch we have remapped:
1. TINYSYS (3-bit to 4-bit)
- domain 3 to domain 3
- others to domain 15
2. MMSYS slave (4-bit to 2-bit)
- domain X to domain X, for X = 0 ~ 3
- others to domain 0
Change-Id: Id10a4c0bdf141cc76a386159896c861d0dc302aa
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move the initialization from bootblock to romstage for following reasons:
- Follow MT8183 initialization sequence.
- PMIC and RTC functions are only called after verstage.
- Reduce bootblock size.
- PMIC initialization setting is complex and may need to be changed by
an RW firmware update.
TEST=boot to kernel successfully
Change-Id: I3e4c3f918639590ffc73076450235771d06aae91
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The Picasso APUs advertise 23 MCA banks in the lower byte of the
IA32_MCG_CAP MSR, which is more than the 7 core MCA banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The bank names were copied over from Stoneyridge, but they don't match
for Picasso.
TEST=Checked the Picasso PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia86cf3874f8b16b007bad46535af6dafb776fbdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51476
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed to get the _SX ASL methods.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6323ba413a21d9d867727dbb28340e6df807c86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, `check-fmap-16mib-crossing` compares the offset and end of
each SPI flash region to 16MiB to ensure that no region is placed
across this 16MiB boundary from the start of SPI flash. What really
needs to be checked is that the region isn't placed across the 16MiB
boundary from the end of BIOS region. Thus, current check works only
if the SPI flash is 32MiB under the assumption that the BIOS region
is mapped at the top of SPI flash. However, this check will not work
if a flash part greater than 32MiB is used.
This change replaces the hardcoded boundary value of 16MiB with a
value calculated by subtracting 16MiB from the SPI flash size (if it
is greater than 16MiB). This calculated value is used as the boundary
that no region defined in the flashmap should be placed across.
The assumption here is that BIOS region is always placed at the top of
SPI flash. Hence, the standard decode window would be from
end_of_flash - 16M to end_of_flash (because end_of_flash =
end_of_bios_region). Currently, there is no consistency in the name
used for BIOS region in flashmap layout for boards in
coreboot. But all Intel-based boards (except APL and GLK) place BIOS
region at the end of SPI flash. Since APL and GLK do not support the
extended window, this check does not matter for these platforms.
Change-Id: Icff83e5bffacfd443c1c3fbc101675c4a6f75e24
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51359
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform some cosmetical changes:
* Override the first prerequisite so we can use `$<`.
* Add/remove whitspace to align things (recipe needs to be indented
by a single tab only).
* We can use shell variables inside double quotes. To make the
end of the variable name clear, use braces, e.g. "${x}".
NB. Most of the double quotes are unnecessary. They only change
the way the script would be failing in case of spurious whitespace.
* Break some lines doing multiple things at once.
* To reduce remaining clutter, put reading numbers into a shell
function.
And functional changes:
* No need to spawn `cat`, the shell can redirect input as well as
output (using `<`).
* To read a number from the `fmap_config.h`, we spawned 4 processes
where a single one can achieve the same. With one exception: GNU
awk refuses to parse hex numbers by default. Luckily, it turned
out that we don't need intermediate decimal numbers: Shells can
do arithmetic with hex values as well.
Change-Id: Ia7bfba0d7864fc091ee6003e09b705fd7254e99b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, if everything worked fine, `$fail` will be unset, leading
to the following `if` statement:
if [ -eq 1 ]
Resulting in the error message:
/bin/sh: line 9: [: -eq: unary operator expected
Fix this by removing the whole `if`, we can just use `exit`.
Change-Id: I1bc7508d2a45a2bec07ef46b9c5d9d0b740fbc74
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000)
since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not
set). Add Cezanne GFX PID.
BUG=b:171234996
BRANCH=Zork
Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gpe_configure_sci has a size_t type parameter, so we need to include
types.h instead of stdint.h here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Function is identical for all mainboards, so factor it out.
Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex
values and rename BIOS_CONTROL macros, as the register is not in SPIBAR.
Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.
Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.
Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Convert the lines starts with whitespace with tab as applicable.
TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.
Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.
This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.
The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.
BUG=b:181354692
TEST=Boot zork past bootblock
Fixes: 82d16b150c ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Even though AMD does not need VBT we still need to implement the
vbt_get() function to not break the build with GOP driver enabled
(see fsps_return_value_handler() in fsp2_0/silicon_init.c
BUG=b:171234996
BRANCH=Zork
Change-Id: I80a5131a9852a05998b55b847243748d24cf535f
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.
Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.
Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We saw EXT_PMIC_EN1 and PPVAR_DVDD_PROC_BC power off sequence
failure, and after checking MT6315 MT6315 PMIC protection key
summary.xlsx and MT6315 Top and CLK programming guide.docx,
we found there are something wrong about the sequence of magic
key protection flow and clk setting. Update correct initial
flow.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I1b7f970a44904fda09a97f4064eef7c95feefad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51245
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The initial settings for MT6315 were not applied correctly
because the setup process didn't specify correct slave id
(incorrectly always sending 0), and may cause failure in
power off sequence.
BUG=b:179000151
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Ifd04da8ac55bcc9f9fdbc088d430522c2725ad47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This also replaces the southbridge_ prefix of the handler functions with
a handle_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prevent writes to Global SMI enable as recommended by the BWG.
Change-Id: I7824464e53a2ca1e860c1aa40d8a7d26e948c418
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add SOC_INTEL_COMMON_PCH_LOCKDOWN and PMC_GLOBAL_RESET_ENABLE_LOCK
to meet device security requirements.
LOCKDOWN has dependencies on SOC_INTEL_COMMON_PCH_BASE and
several other common block devices. Add COMMON_PCH_BASE and
COMMON_PCH_SERVER to pick up LOCKDOWN and the dependencies.
COMMON_PCH_SERVER adds the following common devices that were not
previously included by XEON_SP:
SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
SOC_INTEL_COMMON_BLOCK_CSE
SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
SOC_INTEL_COMMON_BLOCK_ITSS
SOC_INTEL_COMMON_PCH_LOCKDOWN
SOC_INTEL_COMMON_BLOCK_SATA
SOC_INTEL_COMMON_BLOCK_SMBUS
SOC_INTEL_COMMON_BLOCK_XHCI
Change-Id: Iab97123e487f4f13f874f364a9c51723d234d4f0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a server Kconfig option to select a subset of common PCH devices.
Client devices are included if server isn't selected. This maintains
the current Kconfig behavior.
Change-Id: If11d1a51192dd87ad770b8aa53ce02b6a28b8da8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch pulls control of the memory pool serving allocations from the
CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the
CBFS API. Previously, platforms would independently instantiate this as
part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache
pool is exported as a global so these platforms can still use it to
directly back rdev_mmap() on their boot device, but the cbfs_cache can
now also use it to directly make allocations itself. This is used to
allow transparent decompression support in cbfs_map().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Mainboards can configure gpios in their smihandler.
BUG=b:180507707
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6c2b28f981f580cfb6f982a2d7e4c309d6f82e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change will allow for GEVENTs to be used in ASL code.
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I77abd134555c21a32a302ee92cd080284cd2e634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
If bit 0 of byte 0x47 is set FSP will perform full memory training
even if previously saved data is supplied.
Up to and including FSP 2021 WW01 it was reset internally at the end
of PostMemoryInit. Starting with WW03 this is no longer the case and
Intel advised that this bit should be reset externally if valid MRC
data is present.
Change-Id: I9c4191d2fa2e0203b3464dcf40d845ede5f14c6b
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The default value for the LidStatus is "LidClosed" mean 0
Because of this GOP skips graphics initialization assuming
lid is closed even though lid is open. This Patch is to set
LidStatus UPD to 1 whenever RUN_FSP_GOP config is selected.
BUG=b:178461282
BRANCH=None
TEST=Build and boot ADLRVP and verify eDP is coming up in
depthcharge
Change-Id: I1648ae0f06e414b2a686e325acf803deb702b7a5
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Move PRERAM_CBMEM_CONSOLE to SRAM L2C and increase its size from 15K to
400K. With this change, most part of the DRAM full calibration log can
be stored in CBMEM console.
BUG=b:181933863
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=none
Change-Id: I896884d298e197149f75865e9d00579124a34404
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Many header files and helper macros have been moved to the
common folder and we want to use them in mt8173/mt8183
DRAM calibration code.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ifa483dcfffe0e1383cb46811563c90f0ab484d5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51224
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
