src/: Replace GPL boilerplate with SPDX headers
Used commands:
perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist)
perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist)
Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08 22:50:46 +02:00
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## SPDX-License-Identifier: GPL-2.0-only
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2009-08-12 17:00:51 +02:00
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2012-04-12 22:00:03 +02:00
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mainmenu "coreboot configuration"
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2009-08-12 17:00:51 +02:00
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2009-10-05 15:55:28 +02:00
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menu "General setup"
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2017-04-03 16:38:20 +02:00
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config COREBOOT_BUILD
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bool
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default y
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2009-10-05 15:55:28 +02:00
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config LOCALVERSION
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2009-10-07 18:15:40 +02:00
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string "Local version string"
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2009-10-05 15:55:28 +02:00
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help
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Append an extra string to the end of the coreboot version.
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2009-10-07 18:15:40 +02:00
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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2019-06-08 11:28:52 +02:00
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config CONFIGURABLE_CBFS_PREFIX
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bool
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help
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Select this to prompt to use to configure the prefix for cbfs files.
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2019-10-06 13:34:20 +02:00
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choice
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prompt "CBFS prefix to use"
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depends on CONFIGURABLE_CBFS_PREFIX
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default CBFS_PREFIX_FALLBACK
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config CBFS_PREFIX_FALLBACK
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bool "fallback"
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config CBFS_PREFIX_NORMAL
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bool "normal"
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config CBFS_PREFIX_DIY
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bool "Define your own cbfs prefix"
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endchoice
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2010-02-09 20:35:16 +01:00
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config CBFS_PREFIX
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2019-10-06 13:34:20 +02:00
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string "CBFS prefix to use" if CBFS_PREFIX_DIY
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default "fallback" if !CONFIGURABLE_CBFS_PREFIX || CBFS_PREFIX_FALLBACK
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default "normal" if CBFS_PREFIX_NORMAL
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2010-02-09 20:35:16 +01:00
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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2010-03-16 02:17:19 +01:00
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choice
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2012-04-12 22:00:03 +02:00
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prompt "Compiler to use"
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2010-03-16 02:17:19 +01:00
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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2016-01-19 20:01:09 +01:00
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You must build the coreboot crosscompiler for the board that you
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have selected.
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To build all the GCC crosscompilers (takes a LONG time), run:
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make crossgcc
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For help on individual architectures, run the command:
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make help_toolchain
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2010-03-16 02:17:19 +01:00
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config COMPILER_GCC
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bool "GCC"
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2012-04-12 22:00:03 +02:00
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help
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Use the GNU Compiler Collection (GCC) to build coreboot.
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For details see http://gcc.gnu.org.
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2010-03-16 02:17:19 +01:00
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config COMPILER_LLVM_CLANG
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2016-01-19 20:01:09 +01:00
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bool "LLVM/clang (TESTING ONLY - Not currently working)"
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2012-04-12 22:00:03 +02:00
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help
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2016-01-19 20:01:09 +01:00
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Use LLVM/clang to build coreboot. To use this, you must build the
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coreboot version of the clang compiler. Run the command
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make clang
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Note that this option is not currently working correctly and should
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really only be selected if you're trying to work on getting clang
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operational.
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2012-04-12 22:00:03 +02:00
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For details see http://clang.llvm.org.
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2010-03-16 02:17:19 +01:00
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endchoice
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2013-12-29 18:45:23 +01:00
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config ANY_TOOLCHAIN
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bool "Allow building with any toolchain"
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default n
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help
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Many toolchains break when building coreboot since it uses quite
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unusual linker features. Unless developers explicitely request it,
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we'll have to assume that they use their distro compiler by mistake.
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Make sure that using patched compilers is a conscious decision.
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2010-03-25 22:45:25 +01:00
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config CCACHE
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2012-04-12 22:00:03 +02:00
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bool "Use ccache to speed up (re)compilation"
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2010-03-25 22:45:25 +01:00
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default n
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help
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Enables the use of ccache for faster builds.
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2012-04-12 22:00:03 +02:00
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Requires the ccache utility in your system $PATH.
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For details see https://ccache.samba.org.
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2010-03-25 22:45:25 +01:00
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2015-02-26 20:47:19 +01:00
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config FMD_GENPARSER
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bool "Generate flashmap descriptor parser using flex and bison"
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default n
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help
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Enable this option if you are working on the flashmap descriptor
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parser and made changes to fmd_scanner.l or fmd_parser.y.
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Otherwise, say N to use the provided pregenerated scanner/parser.
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2017-04-10 03:12:42 +02:00
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config UTIL_GENPARSER
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2018-01-10 14:35:55 +01:00
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bool "Generate SCONFIG & BINCFG parser using flex and bison"
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2010-08-09 15:28:18 +02:00
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default n
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help
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2012-04-12 22:00:03 +02:00
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Enable this option if you are working on the sconfig device tree
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2018-01-10 14:35:55 +01:00
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parser or bincfg and made changes to the .l or .y files.
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2012-04-12 22:00:03 +02:00
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2015-02-26 20:47:19 +01:00
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Otherwise, say N to use the provided pregenerated scanner/parser.
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2010-08-09 15:28:18 +02:00
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2010-05-19 20:41:15 +02:00
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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2010-07-06 23:05:04 +02:00
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depends on HAVE_OPTION_TABLE
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2010-05-19 20:41:15 +02:00
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help
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Enable this option if coreboot shall read options from the "CMOS"
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2012-04-12 22:00:03 +02:00
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NVRAM instead of using hard-coded values.
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2010-05-19 20:41:15 +02:00
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2015-02-14 23:15:31 +01:00
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config STATIC_OPTION_TABLE
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bool "Load default configuration values into CMOS on each boot"
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depends on USE_OPTION_TABLE
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help
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Enable this option to reset "CMOS" NVRAM values to default on
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every boot. Use this if you want the NVRAM configuration to
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never be modified from its default values.
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2011-05-02 21:53:04 +02:00
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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2019-06-08 08:59:02 +02:00
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depends on HAVE_RAMSTAGE
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2016-12-15 23:05:37 +01:00
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# Default value set at the end of the file
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2011-05-02 21:53:04 +02:00
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help
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2019-11-08 11:59:25 +01:00
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Compress ramstage to save memory in the flash image.
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2011-05-02 21:53:04 +02:00
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2015-09-29 22:51:35 +02:00
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config COMPRESS_PRERAM_STAGES
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bool "Compress romstage and verstage with LZ4"
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2019-06-08 08:59:02 +02:00
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depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
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2016-12-15 23:05:37 +01:00
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# Default value set at the end of the file
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2015-09-29 22:51:35 +02:00
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help
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Compress romstage and (if it exists) verstage with LZ4 to save flash
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space and speed up boot, since the time for reading the image from SPI
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(and in the vboot case verifying it) is usually much greater than the
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time spent decompressing. Doesn't work for XIP stages (assume all
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ARCH_X86 for now) for obvious reasons.
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Introduce bootblock self-decompression
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-16 23:14:04 +02:00
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config COMPRESS_BOOTBLOCK
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bool
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2019-06-08 08:59:02 +02:00
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depends on HAVE_BOOTBLOCK
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Introduce bootblock self-decompression
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-16 23:14:04 +02:00
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help
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This option can be used to compress the bootblock with LZ4 and attach
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a small self-decompression stub to its front. This can drastically
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reduce boot time on platforms where the bootblock is loaded over a
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very slow connection and bootblock size trumps all other factors for
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2018-09-29 17:42:52 +02:00
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speed. Since using this option usually requires changes to the
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Introduce bootblock self-decompression
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-16 23:14:04 +02:00
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SoC memlayout and possibly extra support code, it should not be
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user-selectable. (There's no real point in offering this to the user
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anyway... if it works and saves boot time, you would always want it.)
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2011-06-19 03:03:28 +02:00
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config INCLUDE_CONFIG_FILE
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2012-04-12 22:00:03 +02:00
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bool "Include the coreboot .config file into the ROM image"
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2016-12-15 23:05:37 +01:00
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# Default value set at the end of the file
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2012-04-12 22:00:03 +02:00
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help
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Include the .config file that was used to compile coreboot
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in the (CBFS) ROM image. This is useful if you want to know which
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options were used to build a specific coreboot.rom image.
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2014-07-22 18:00:56 +02:00
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Saying Y here will increase the image size by 2-3KB.
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2012-04-12 22:00:03 +02:00
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You can use the following command to easily list the options:
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grep -a CONFIG_ coreboot.rom
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Alternatively, you can also use cbfstool to print the image
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contents (including the raw 'config' item we're looking for).
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Example:
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$ cbfstool coreboot.rom print
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coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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offset 0x0
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Alignment: 64 bytes
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2012-05-18 19:18:47 +02:00
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2012-04-12 22:00:03 +02:00
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Name Offset Type Size
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2020-02-16 10:01:33 +01:00
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cmos_layout.bin 0x0 CMOS layout 1159
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2012-04-12 22:00:03 +02:00
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fallback/romstage 0x4c0 stage 339756
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2014-07-22 18:00:56 +02:00
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fallback/ramstage 0x53440 stage 186664
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2012-04-12 22:00:03 +02:00
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fallback/payload 0x80dc0 payload 51526
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config 0x8d740 raw 3324
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(empty) 0x8e480 null 3610440
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2011-06-19 03:03:28 +02:00
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2011-09-21 23:46:43 +02:00
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config COLLECT_TIMESTAMPS
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bool "Create a table of timestamps collected during boot"
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2015-10-11 11:57:44 +02:00
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default y if ARCH_X86
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2011-09-21 23:46:43 +02:00
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help
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2012-04-12 22:00:03 +02:00
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Make coreboot create a table of timer-ID/timer-value pairs to
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allow measuring time spent at different phases of the boot process.
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2018-03-07 23:32:16 +01:00
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config TIMESTAMPS_ON_CONSOLE
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bool "Print the timestamp values on the console"
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default n
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depends on COLLECT_TIMESTAMPS
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help
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2020-01-09 07:41:46 +01:00
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Print the timestamps to the debug console if enabled at level info.
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2018-03-07 23:32:16 +01:00
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2012-04-30 21:06:10 +02:00
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config USE_BLOBS
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bool "Allow use of binary-only repository"
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2019-12-28 19:10:12 +01:00
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default y
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2012-04-30 21:06:10 +02:00
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help
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This draws in the blobs repository, which contains binary files that
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might be required for some chipsets or boards.
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This flag ensures that a "Free" option remains available for users.
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2019-10-28 22:55:03 +01:00
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config USE_AMD_BLOBS
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bool "Allow AMD blobs repository (with license agreement)"
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depends on USE_BLOBS
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help
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This draws in the amd_blobs repository, which contains binary files
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distributed by AMD, including VBIOS, PSP bootloaders, SMU firmwares,
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etc. Selecting this item to download or clone the repo implies your
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agreement to the AMD license agreement. A copy of the license text
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may be reviewed by reading Documentation/soc/amd/amdblobs_license.md,
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and your copy of the license is present in the repo once downloaded.
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Note that for some products, omitting PSP, SMU images, or other items
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may result in a nonbooting coreboot.rom.
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Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
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config COVERAGE
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bool "Code coverage support"
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depends on COMPILER_GCC
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help
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Add code coverage support for coreboot. This will store code
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coverage information in CBMEM for extraction from user space.
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If unsure, say N.
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2017-06-12 06:07:31 +02:00
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config UBSAN
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bool "Undefined behavior sanitizer support"
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default n
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help
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Instrument the code with checks for undefined behavior. If unsure,
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say N because it adds a small performance penalty and may abort
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on code that happens to work in spite of the UB.
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2014-10-17 13:08:36 +02:00
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config RELOCATABLE_RAMSTAGE
|
2016-06-18 06:39:31 +02:00
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bool
|
2019-12-08 12:05:21 +01:00
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default y if ARCH_X86
|
2015-05-30 22:21:37 +02:00
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select RELOCATABLE_MODULES
|
2014-10-17 13:08:36 +02:00
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help
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The reloctable ramstage support allows for the ramstage to be built
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as a relocatable module. The stage loader can identify a place
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out of the OS way so that copying memory is unnecessary during an S3
|
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wake. When selecting this option the romstage is responsible for
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determing a stack location to use for loading the ramstage.
|
2012-11-29 05:16:28 +01:00
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2019-12-17 23:19:06 +01:00
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choice
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prompt "Stage Cache for ACPI S3 resume"
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default NO_STAGE_CACHE if !HAVE_ACPI_RESUME || !RELOCATABLE_RAMSTAGE
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default TSEG_STAGE_CACHE if SMM_TSEG
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config NO_STAGE_CACHE
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bool "Disabled"
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help
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Do not save any component in stage cache for resume path. On resume,
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all components would be read back from CBFS again.
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|
2019-08-01 19:29:14 +02:00
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config TSEG_STAGE_CACHE
|
2019-12-17 23:19:06 +01:00
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bool "TSEG"
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depends on SMM_TSEG
|
2019-08-01 19:29:14 +02:00
|
|
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help
|
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The option enables stage cache support for platform. Platform
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can stash copies of postcar, ramstage and raw runtime data
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inside SMM TSEG, to be restored on S3 resume path.
|
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config CBMEM_STAGE_CACHE
|
2019-12-17 23:19:06 +01:00
|
|
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bool "CBMEM"
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|
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depends on !SMM_TSEG
|
2014-10-17 13:08:36 +02:00
|
|
|
help
|
2019-08-01 19:29:14 +02:00
|
|
|
The option enables stage cache support for platform. Platform
|
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can stash copies of postcar, ramstage and raw runtime data
|
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inside CBMEM.
|
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While the approach is faster than reloading stages from boot media
|
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it is also a possible attack scenario via which OS can possibly
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circumvent SMM locks and SPI write protections.
|
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If unsure, select 'N'
|
2014-02-07 03:58:24 +01:00
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2019-12-17 23:19:06 +01:00
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endchoice
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|
2014-05-07 03:00:19 +02:00
|
|
|
config UPDATE_IMAGE
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|
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bool "Update existing coreboot.rom image"
|
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|
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help
|
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|
|
If this option is enabled, no new coreboot.rom file
|
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|
is created. Instead it is expected that there already
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is a suitable file for further processing.
|
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The bootblock will not be modified.
|
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|
2016-01-20 22:59:21 +01:00
|
|
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If unsure, select 'N'
|
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|
2015-01-24 15:52:10 +01:00
|
|
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config BOOTSPLASH_IMAGE
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|
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bool "Add a bootsplash image"
|
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|
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help
|
|
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|
Select this option if you have a bootsplash image that you would
|
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like to add to your ROM.
|
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This will only add the image to the ROM. To actually run it check
|
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options under 'Display' section.
|
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|
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config BOOTSPLASH_FILE
|
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|
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string "Bootsplash path and filename"
|
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|
|
depends on BOOTSPLASH_IMAGE
|
2016-12-15 23:05:37 +01:00
|
|
|
# Default value set at the end of the file
|
2015-01-24 15:52:10 +01:00
|
|
|
help
|
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|
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The path and filename of the file to use as graphical bootsplash
|
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screen. The file format has to be jpg.
|
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|
2020-05-10 04:20:10 +02:00
|
|
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config FW_CONFIG
|
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|
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bool "Firmware Configuration Probing"
|
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default n
|
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|
|
help
|
|
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|
|
Enable support for probing devices with fw_config. This is a simple
|
|
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|
|
bitmask broken into fields and options for probing.
|
|
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|
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config FW_CONFIG_SOURCE_CBFS
|
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|
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bool "Obtain Firmware Configuration value from CBFS"
|
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|
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depends on FW_CONFIG
|
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default n
|
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help
|
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|
|
With this option enabled coreboot will look for the 32bit firmware
|
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|
|
configuration value in CBFS at the selected prefix with the file name
|
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|
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"fw_config". This option will override other sources and allow the
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|
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local image to preempt the mainboard selected source.
|
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|
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config FW_CONFIG_SOURCE_CHROMEEC_CBI
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|
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bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
|
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|
|
depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
|
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default n
|
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|
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help
|
|
|
|
|
This option tells coreboot to read the firmware configuration value
|
|
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|
|
from the Google Chrome Embedded Controller CBI interface. This source
|
|
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|
|
is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
|
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|
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found in CBFS.
|
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|
|
2019-06-06 19:36:02 +02:00
|
|
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config HAVE_RAMPAYLOAD
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bool
|
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|
|
2019-05-06 10:47:41 +02:00
|
|
|
config RAMPAYLOAD
|
|
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|
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bool "Enable coreboot flow without executing ramstage"
|
2019-06-28 14:48:37 +02:00
|
|
|
default y if ARCH_X86
|
2019-06-06 19:36:02 +02:00
|
|
|
depends on HAVE_RAMPAYLOAD
|
2019-05-06 10:47:41 +02:00
|
|
|
help
|
|
|
|
|
If this option is enabled, coreboot flow will skip ramstage
|
|
|
|
|
loading and execution of ramstage to load payload.
|
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Instead it is expected to load payload from postcar stage itself.
|
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In this flow coreboot will perform basic x86 initialization
|
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|
|
(DRAM resource allocation), MTRR programming,
|
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|
|
Skip PCI enumeration logic and only allocate BAR for fixed devices
|
|
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|
|
(bootable devices, TPM over GSPI).
|
|
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|
|
|
2020-02-09 14:43:52 +01:00
|
|
|
config HAVE_CONFIGURABLE_RAMSTAGE
|
|
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|
|
bool
|
|
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|
|
|
Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2019-10-22 04:02:24 +02:00
|
|
|
config CONFIGURABLE_RAMSTAGE
|
|
|
|
|
bool "Enable a configurable ramstage."
|
|
|
|
|
default y if ARCH_X86
|
2020-02-09 14:43:52 +01:00
|
|
|
depends on HAVE_CONFIGURABLE_RAMSTAGE
|
Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2019-10-22 04:02:24 +02:00
|
|
|
help
|
|
|
|
|
A configurable ramstage allows you to select which parts of the ramstage
|
|
|
|
|
to run. Currently, we can only select a minimal PCI scanning step.
|
|
|
|
|
The minimal PCI scanning will only check those parts that are enabled
|
|
|
|
|
in the devicetree.cb. By convention none of those devices should be bridges.
|
|
|
|
|
|
|
|
|
|
config MINIMAL_PCI_SCANNING
|
|
|
|
|
bool "Enable minimal PCI scanning"
|
2020-02-09 15:05:16 +01:00
|
|
|
depends on CONFIGURABLE_RAMSTAGE && PCI
|
Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2019-10-22 04:02:24 +02:00
|
|
|
help
|
2020-02-09 15:05:16 +01:00
|
|
|
If this option is enabled, coreboot will scan only PCI devices
|
Add configurable ramstage support for minimal PCI scanning
This CL has changes that allow us to enable a configurable
ramstage, and one change that allows us to minimize PCI
scanning. Minimal scanning is a frequently requested feature.
To enable it, we add two new variables to src/Kconfig
CONFIGURABLE_RAMSTAGE
is the overall variable controlling other options for minimizing the
ramstage.
MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal
PCI scanning.
Some devices must be scanned in all cases, such as 0:0.0.
To indicate which devices we must scan, we add a new mandatory
keyword to sconfig
It is used in place of on, off, or hidden, and indicates
a device is enabled and mandatory. Mandatory
devices are always scanned. When MINIMAL_PCI_SCANNING is enabled,
ONLY mandatory devices are scanned.
We further add support in src/device/pci_device.c to manage
both MINIMAL_PCI_SCANNING and mandatory devices.
Finally, to show how this works in practice, we add mandatory
keywords to 3 devices on the qemu-q35.
TEST=
1. This is tested and working on the qemu-q35 target.
2. On CML-Hatch
Before CL:
Total Boot time: ~685ms
After CL:
Total Boot time: ~615ms
Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2019-10-22 04:02:24 +02:00
|
|
|
marked as mandatory in devicetree.cb
|
2014-10-17 13:08:36 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2015-06-20 07:17:15 +02:00
|
|
|
menu "Mainboard"
|
|
|
|
|
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/mainboard/Kconfig"
|
2014-10-17 13:08:36 +02:00
|
|
|
|
2016-09-04 16:38:33 +02:00
|
|
|
config DEVICETREE
|
|
|
|
|
string
|
|
|
|
|
default "devicetree.cb"
|
|
|
|
|
help
|
|
|
|
|
This symbol allows mainboards to select a different file under their
|
|
|
|
|
mainboard directory for the devicetree.cb file. This allows the board
|
|
|
|
|
variants that need different devicetrees to be in the same directory.
|
|
|
|
|
|
|
|
|
|
Examples: "devicetree.variant.cb"
|
|
|
|
|
"variant/devicetree.cb"
|
|
|
|
|
|
2018-06-22 03:50:48 +02:00
|
|
|
config OVERRIDE_DEVICETREE
|
|
|
|
|
string
|
|
|
|
|
default ""
|
|
|
|
|
help
|
|
|
|
|
This symbol allows variants to provide an override devicetree file to
|
|
|
|
|
override the registers and/or add new devices on top of the ones
|
|
|
|
|
provided by baseboard devicetree using CONFIG_DEVICETREE.
|
|
|
|
|
|
|
|
|
|
Examples: "devicetree.variant-override.cb"
|
|
|
|
|
"variant/devicetree-override.cb"
|
|
|
|
|
|
2019-09-25 13:18:52 +02:00
|
|
|
config FMDFILE
|
|
|
|
|
string "fmap description file in fmd format"
|
|
|
|
|
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
|
|
|
|
|
default ""
|
|
|
|
|
help
|
|
|
|
|
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
|
|
|
|
|
but in some cases more complex setups are required.
|
|
|
|
|
When an fmd is specified, it overrides the default format.
|
|
|
|
|
|
2015-06-20 07:17:15 +02:00
|
|
|
config CBFS_SIZE
|
|
|
|
|
hex "Size of CBFS filesystem in ROM"
|
2019-09-25 13:18:52 +02:00
|
|
|
depends on FMDFILE = ""
|
2016-12-15 23:05:37 +01:00
|
|
|
# Default value set at the end of the file
|
2015-06-20 07:17:15 +02:00
|
|
|
help
|
|
|
|
|
This is the part of the ROM actually managed by CBFS, located at the
|
|
|
|
|
end of the ROM (passed through cbfstool -o) on x86 and at at the start
|
|
|
|
|
of the ROM (passed through cbfstool -s) everywhere else. It defaults
|
|
|
|
|
to span the whole ROM on all but Intel systems that use an Intel Firmware
|
|
|
|
|
Descriptor. It can be overridden to make coreboot live alongside other
|
|
|
|
|
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
|
2019-09-25 13:18:52 +02:00
|
|
|
binaries. This symbol should only be used to generate a default FMAP and
|
|
|
|
|
is unused when a non-default fmd file is provided via CONFIG_FMDFILE.
|
2015-09-16 18:10:52 +02:00
|
|
|
|
2015-12-27 00:51:16 +01:00
|
|
|
endmenu
|
|
|
|
|
|
2016-01-25 03:38:33 +01:00
|
|
|
# load site-local kconfig to allow user specific defaults and overrides
|
|
|
|
|
source "site-local/Kconfig"
|
|
|
|
|
|
2014-10-17 13:08:36 +02:00
|
|
|
config SYSTEM_TYPE_LAPTOP
|
2015-04-27 02:53:26 +02:00
|
|
|
default n
|
|
|
|
|
bool
|
2014-10-17 13:08:36 +02:00
|
|
|
|
2019-02-01 20:33:57 +01:00
|
|
|
config SYSTEM_TYPE_TABLET
|
|
|
|
|
default n
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config SYSTEM_TYPE_DETACHABLE
|
|
|
|
|
default n
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config SYSTEM_TYPE_CONVERTIBLE
|
|
|
|
|
default n
|
|
|
|
|
bool
|
|
|
|
|
|
2016-01-14 15:08:36 +01:00
|
|
|
config CBFS_AUTOGEN_ATTRIBUTES
|
|
|
|
|
default n
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
If this option is selected, every file in cbfs which has a constraint
|
|
|
|
|
regarding position or alignment will get an additional file attribute
|
|
|
|
|
which describes this constraint.
|
|
|
|
|
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
menu "Chipset"
|
|
|
|
|
|
2015-06-09 03:11:56 +02:00
|
|
|
comment "SoC"
|
2017-10-20 18:43:39 +02:00
|
|
|
source "src/soc/*/Kconfig"
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "CPU"
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/cpu/Kconfig"
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "Northbridge"
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/northbridge/*/*/Kconfig"
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "Southbridge"
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/southbridge/*/*/Kconfig"
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
comment "Super I/O"
|
2016-07-29 23:31:45 +02:00
|
|
|
source "src/superio/*/*/Kconfig"
|
2011-01-27 12:43:03 +01:00
|
|
|
comment "Embedded Controllers"
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/ec/acpi/Kconfig"
|
|
|
|
|
source "src/ec/*/*/Kconfig"
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
|
2015-06-21 00:17:12 +02:00
|
|
|
source "src/southbridge/intel/common/firmware/Kconfig"
|
2015-06-20 06:30:43 +02:00
|
|
|
source "src/vendorcode/*/Kconfig"
|
2015-06-21 00:17:12 +02:00
|
|
|
|
2015-06-20 06:30:43 +02:00
|
|
|
source "src/arch/*/Kconfig"
|
|
|
|
|
|
Add kconfig menus for most chipset VIDEO_MB values.
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 22:42:13 +01:00
|
|
|
endmenu
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/device/Kconfig"
|
2012-11-14 02:00:01 +01:00
|
|
|
|
2010-05-16 17:31:53 +02:00
|
|
|
menu "Generic Drivers"
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/drivers/*/Kconfig"
|
2016-03-12 05:22:28 +01:00
|
|
|
source "src/drivers/*/*/Kconfig"
|
2017-05-09 01:56:03 +02:00
|
|
|
source "src/commonlib/storage/Kconfig"
|
2010-05-16 17:31:53 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2017-10-16 17:09:33 +02:00
|
|
|
menu "Security"
|
|
|
|
|
|
|
|
|
|
source "src/security/Kconfig"
|
2019-11-14 14:10:28 +01:00
|
|
|
source "src/vendorcode/eltan/security/Kconfig"
|
2017-10-16 17:09:33 +02:00
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
|
2016-05-17 19:28:23 +02:00
|
|
|
source "src/acpi/Kconfig"
|
|
|
|
|
|
2016-08-11 18:02:26 +02:00
|
|
|
# This option is for the current boards/chipsets where SPI flash
|
|
|
|
|
# is not the boot device. Currently nearly all boards/chipsets assume
|
|
|
|
|
# SPI flash is the boot device.
|
|
|
|
|
config BOOT_DEVICE_NOT_SPI_FLASH
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config BOOT_DEVICE_SPI_FLASH
|
|
|
|
|
bool
|
|
|
|
|
default y if !BOOT_DEVICE_NOT_SPI_FLASH
|
|
|
|
|
default n
|
|
|
|
|
|
2016-08-11 21:04:10 +02:00
|
|
|
config BOOT_DEVICE_MEMORY_MAPPED
|
|
|
|
|
bool
|
|
|
|
|
default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Inform system if SPI is memory-mapped or not.
|
|
|
|
|
|
2016-08-12 22:00:10 +02:00
|
|
|
config BOOT_DEVICE_SUPPORTS_WRITES
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Indicate that the platform has writable boot device
|
|
|
|
|
support.
|
|
|
|
|
|
2015-04-22 13:28:21 +02:00
|
|
|
config RTC
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config HEAP_SIZE
|
|
|
|
|
hex
|
2019-04-23 03:46:27 +02:00
|
|
|
default 0x100000 if FLATTENED_DEVICE_TREE
|
2009-10-16 21:12:49 +02:00
|
|
|
default 0x4000
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2014-09-19 22:18:16 +02:00
|
|
|
config STACK_SIZE
|
|
|
|
|
hex
|
2015-10-13 01:45:21 +02:00
|
|
|
default 0x1000 if ARCH_X86
|
|
|
|
|
default 0x0
|
2014-09-19 22:18:16 +02:00
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config MAX_CPUS
|
|
|
|
|
int
|
|
|
|
|
default 1
|
|
|
|
|
|
2015-04-04 01:58:28 +02:00
|
|
|
source "src/console/Kconfig"
|
2009-08-12 17:00:51 +02:00
|
|
|
|
|
|
|
|
config HAVE_ACPI_RESUME
|
|
|
|
|
bool
|
|
|
|
|
default n
|
2018-06-03 22:04:28 +02:00
|
|
|
depends on RELOCATABLE_RAMSTAGE
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2020-01-15 11:31:25 +01:00
|
|
|
config DISABLE_ACPI_HIBERNATE
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Removes S4 from the available sleepstates
|
|
|
|
|
|
2016-01-22 22:26:04 +01:00
|
|
|
config RESUME_PATH_SAME_AS_BOOT
|
|
|
|
|
bool
|
|
|
|
|
default y if ARCH_X86
|
|
|
|
|
depends on HAVE_ACPI_RESUME
|
|
|
|
|
help
|
|
|
|
|
This option indicates that when a system resumes it takes the
|
|
|
|
|
same path as a regular boot. e.g. an x86 system runs from the
|
|
|
|
|
reset vector at 0xfffffff0 on both resume and warm/cold boot.
|
|
|
|
|
|
2019-07-01 16:25:41 +02:00
|
|
|
config NO_MONOTONIC_TIMER
|
2013-04-30 05:31:51 +02:00
|
|
|
def_bool n
|
2019-07-01 16:25:41 +02:00
|
|
|
|
|
|
|
|
config HAVE_MONOTONIC_TIMER
|
|
|
|
|
bool
|
|
|
|
|
depends on !NO_MONOTONIC_TIMER
|
2019-07-01 14:38:25 +02:00
|
|
|
default y
|
2013-04-30 05:31:51 +02:00
|
|
|
help
|
|
|
|
|
The board/chipset provides a monotonic timer.
|
|
|
|
|
|
2014-09-25 17:05:15 +02:00
|
|
|
config GENERIC_UDELAY
|
2019-07-01 16:25:41 +02:00
|
|
|
bool
|
2014-09-25 17:05:15 +02:00
|
|
|
depends on HAVE_MONOTONIC_TIMER
|
2019-07-01 16:25:41 +02:00
|
|
|
default y if !ARCH_X86
|
2014-09-25 17:05:15 +02:00
|
|
|
help
|
|
|
|
|
The board/chipset uses a generic udelay function utilizing the
|
|
|
|
|
monotonic timer.
|
|
|
|
|
|
2013-04-30 16:58:12 +02:00
|
|
|
config TIMER_QUEUE
|
|
|
|
|
def_bool n
|
|
|
|
|
depends on HAVE_MONOTONIC_TIMER
|
|
|
|
|
help
|
2013-09-13 06:57:49 +02:00
|
|
|
Provide a timer queue for performing time-based callbacks.
|
2013-04-30 16:58:12 +02:00
|
|
|
|
2013-05-06 19:20:52 +02:00
|
|
|
config COOP_MULTITASKING
|
|
|
|
|
def_bool n
|
2013-05-06 19:22:23 +02:00
|
|
|
depends on TIMER_QUEUE && ARCH_X86
|
2013-05-06 19:20:52 +02:00
|
|
|
help
|
|
|
|
|
Cooperative multitasking allows callbacks to be multiplexed on the
|
|
|
|
|
main thread of ramstage. With this enabled it allows for multiple
|
|
|
|
|
execution paths to take place when they have udelay() calls within
|
|
|
|
|
their code.
|
|
|
|
|
|
|
|
|
|
config NUM_THREADS
|
|
|
|
|
int
|
|
|
|
|
default 4
|
|
|
|
|
depends on COOP_MULTITASKING
|
|
|
|
|
help
|
|
|
|
|
How many execution threads to cooperatively multitask with.
|
|
|
|
|
|
2009-08-12 17:00:51 +02:00
|
|
|
config HAVE_OPTION_TABLE
|
|
|
|
|
bool
|
2010-07-06 23:05:04 +02:00
|
|
|
default n
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
This variable specifies whether a given board has a cmos.layout
|
|
|
|
|
file containing NVRAM/CMOS bit definitions.
|
2010-07-06 23:05:04 +02:00
|
|
|
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
|
2009-08-12 17:00:51 +02:00
|
|
|
|
|
|
|
|
config PCI_IO_CFG_EXT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config IOAPIC
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2009-09-22 20:49:08 +02:00
|
|
|
config USE_WATCHDOG_ON_BOOT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
|
|
|
|
config GFXUMA
|
|
|
|
|
bool
|
2009-10-26 16:14:07 +01:00
|
|
|
default n
|
2009-09-22 20:49:08 +02:00
|
|
|
help
|
|
|
|
|
Enable Unified Memory Architecture for graphics.
|
|
|
|
|
|
2009-10-15 15:35:47 +02:00
|
|
|
config HAVE_MP_TABLE
|
|
|
|
|
bool
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
This variable specifies whether a given board has MP table support.
|
|
|
|
|
It is usually set in mainboard/*/Kconfig.
|
|
|
|
|
Whether or not the MP table is actually generated by coreboot
|
|
|
|
|
is configurable by the user via GENERATE_MP_TABLE.
|
2009-10-15 15:35:47 +02:00
|
|
|
|
|
|
|
|
config HAVE_PIRQ_TABLE
|
|
|
|
|
bool
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
This variable specifies whether a given board has PIRQ table support.
|
|
|
|
|
It is usually set in mainboard/*/Kconfig.
|
|
|
|
|
Whether or not the PIRQ table is actually generated by coreboot
|
|
|
|
|
is configurable by the user via GENERATE_PIRQ_TABLE.
|
2009-10-15 15:35:47 +02:00
|
|
|
|
2015-11-17 23:31:00 +01:00
|
|
|
config ACPI_NHLT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Build support for NHLT (non HD Audio) ACPI table generation.
|
|
|
|
|
|
2009-10-26 16:14:07 +01:00
|
|
|
#These Options are here to avoid "undefined" warnings.
|
|
|
|
|
#The actual selection and help texts are in the following menu.
|
|
|
|
|
|
|
|
|
|
menu "System tables"
|
2009-09-22 20:49:08 +02:00
|
|
|
|
2009-10-15 15:35:47 +02:00
|
|
|
config GENERATE_MP_TABLE
|
2012-11-14 02:33:08 +01:00
|
|
|
prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
|
|
|
|
bool
|
|
|
|
|
default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
Generate an MP table (conforming to the Intel MultiProcessor
|
|
|
|
|
specification 1.4) for this board.
|
|
|
|
|
|
|
|
|
|
If unsure, say Y.
|
2009-09-22 20:49:08 +02:00
|
|
|
|
2009-10-15 15:35:47 +02:00
|
|
|
config GENERATE_PIRQ_TABLE
|
2012-11-14 02:33:08 +01:00
|
|
|
prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
|
|
|
|
|
bool
|
|
|
|
|
default HAVE_PIRQ_TABLE
|
2009-10-15 19:49:07 +02:00
|
|
|
help
|
|
|
|
|
Generate a PIRQ table for this board.
|
|
|
|
|
|
|
|
|
|
If unsure, say Y.
|
2009-09-22 20:49:08 +02:00
|
|
|
|
2011-08-14 20:56:34 +02:00
|
|
|
config GENERATE_SMBIOS_TABLES
|
|
|
|
|
depends on ARCH_X86
|
|
|
|
|
bool "Generate SMBIOS tables"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Generate SMBIOS tables for this board.
|
|
|
|
|
|
|
|
|
|
If unsure, say Y.
|
|
|
|
|
|
2015-05-30 23:08:26 +02:00
|
|
|
config SMBIOS_PROVIDED_BY_MOBO
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
|
2014-10-17 13:28:15 +02:00
|
|
|
config MAINBOARD_SERIAL_NUMBER
|
2017-11-01 09:49:16 +01:00
|
|
|
prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
|
|
|
|
|
string
|
2014-10-17 13:28:15 +02:00
|
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
|
|
|
default "123456789"
|
2015-04-27 02:53:26 +02:00
|
|
|
help
|
2014-10-17 13:28:15 +02:00
|
|
|
The Serial Number to store in SMBIOS structures.
|
|
|
|
|
|
|
|
|
|
config MAINBOARD_VERSION
|
2017-11-01 09:49:16 +01:00
|
|
|
prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
|
|
|
|
|
string
|
2014-10-17 13:28:15 +02:00
|
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
|
|
|
default "1.0"
|
|
|
|
|
help
|
|
|
|
|
The Version Number to store in SMBIOS structures.
|
|
|
|
|
|
|
|
|
|
config MAINBOARD_SMBIOS_MANUFACTURER
|
2017-11-01 09:49:16 +01:00
|
|
|
prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
|
|
|
|
|
string
|
2014-10-17 13:28:15 +02:00
|
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
|
|
|
default MAINBOARD_VENDOR
|
|
|
|
|
help
|
|
|
|
|
Override the default Manufacturer stored in SMBIOS structures.
|
|
|
|
|
|
|
|
|
|
config MAINBOARD_SMBIOS_PRODUCT_NAME
|
2017-11-01 09:49:16 +01:00
|
|
|
prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
|
|
|
|
|
string
|
2014-10-17 13:28:15 +02:00
|
|
|
depends on GENERATE_SMBIOS_TABLES
|
|
|
|
|
default MAINBOARD_PART_NUMBER
|
|
|
|
|
help
|
|
|
|
|
Override the default Product name stored in SMBIOS structures.
|
|
|
|
|
|
2009-09-22 20:49:08 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2016-02-05 03:52:27 +01:00
|
|
|
source "payloads/Kconfig"
|
2009-09-17 18:21:31 +02:00
|
|
|
|
2009-10-07 18:15:40 +02:00
|
|
|
menu "Debugging"
|
|
|
|
|
|
2018-11-13 19:28:07 +01:00
|
|
|
comment "CPU Debug Settings"
|
2019-11-04 21:50:21 +01:00
|
|
|
source "src/cpu/*/Kconfig.debug_cpu"
|
2018-11-13 19:28:07 +01:00
|
|
|
|
2019-10-20 14:20:53 +02:00
|
|
|
comment "BLOB Debug Settings"
|
|
|
|
|
source "src/drivers/intel/fsp*/Kconfig.debug_blob"
|
|
|
|
|
|
2018-11-13 19:28:07 +01:00
|
|
|
comment "General Debug Settings"
|
|
|
|
|
|
2009-10-07 18:15:40 +02:00
|
|
|
# TODO: Better help text and detailed instructions.
|
2009-08-12 17:00:51 +02:00
|
|
|
config GDB_STUB
|
2009-08-25 02:53:22 +02:00
|
|
|
bool "GDB debugging support"
|
2012-03-25 20:51:16 +02:00
|
|
|
default n
|
2019-11-04 09:33:04 +01:00
|
|
|
depends on DRIVERS_UART
|
2009-08-12 17:00:51 +02:00
|
|
|
help
|
2009-08-25 02:53:22 +02:00
|
|
|
If enabled, you will be able to set breakpoints for gdb debugging.
|
2010-12-11 21:33:41 +01:00
|
|
|
See src/arch/x86/lib/c_start.S for details.
|
2009-08-12 17:00:51 +02:00
|
|
|
|
2012-06-22 15:56:37 +02:00
|
|
|
config GDB_WAIT
|
2015-12-10 21:58:52 +01:00
|
|
|
bool "Wait for a GDB connection in the ramstage"
|
2012-06-22 15:56:37 +02:00
|
|
|
default n
|
|
|
|
|
depends on GDB_STUB
|
|
|
|
|
help
|
2015-12-10 21:58:52 +01:00
|
|
|
If enabled, coreboot will wait for a GDB connection in the ramstage.
|
|
|
|
|
|
2012-06-22 15:56:37 +02:00
|
|
|
|
2015-02-18 02:27:23 +01:00
|
|
|
config FATAL_ASSERTS
|
|
|
|
|
bool "Halt when hitting a BUG() or assertion error"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
|
|
|
|
|
|
2018-11-13 22:06:40 +01:00
|
|
|
config HAVE_DEBUG_GPIO
|
|
|
|
|
bool
|
|
|
|
|
|
|
|
|
|
config DEBUG_GPIO
|
|
|
|
|
bool "Output verbose GPIO debug messages"
|
|
|
|
|
depends on HAVE_DEBUG_GPIO
|
|
|
|
|
|
2012-05-03 01:33:18 +02:00
|
|
|
config DEBUG_CBFS
|
|
|
|
|
bool "Output verbose CBFS debug messages"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option enables additional CBFS related debug messages.
|
|
|
|
|
|
2010-08-26 14:46:02 +02:00
|
|
|
config HAVE_DEBUG_RAM_SETUP
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config DEBUG_RAM_SETUP
|
|
|
|
|
bool "Output verbose RAM init debug messages"
|
|
|
|
|
default n
|
2010-08-26 14:46:02 +02:00
|
|
|
depends on HAVE_DEBUG_RAM_SETUP
|
2010-03-05 11:03:50 +01:00
|
|
|
help
|
|
|
|
|
This option enables additional RAM init related debug messages.
|
|
|
|
|
It is recommended to enable this when debugging issues on your
|
|
|
|
|
board which might be RAM init related.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-06-01 21:25:31 +02:00
|
|
|
config DEBUG_PIRQ
|
|
|
|
|
bool "Check PIRQ table consistency"
|
|
|
|
|
default n
|
|
|
|
|
depends on GENERATE_PIRQ_TABLE
|
|
|
|
|
help
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-08-26 14:46:02 +02:00
|
|
|
config HAVE_DEBUG_SMBUS
|
|
|
|
|
def_bool n
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config DEBUG_SMBUS
|
|
|
|
|
bool "Output verbose SMBus debug messages"
|
|
|
|
|
default n
|
2010-08-26 14:46:02 +02:00
|
|
|
depends on HAVE_DEBUG_SMBUS
|
2010-03-05 11:03:50 +01:00
|
|
|
help
|
|
|
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config DEBUG_SMI
|
|
|
|
|
bool "Output verbose SMI debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on HAVE_SMI_HANDLER
|
2018-06-05 22:34:08 +02:00
|
|
|
select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
|
2010-03-05 11:03:50 +01:00
|
|
|
help
|
|
|
|
|
This option enables additional SMI related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-11-10 01:14:32 +01:00
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
|
|
|
config DEBUG_MALLOC
|
2012-11-14 02:00:01 +01:00
|
|
|
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
bool
|
2010-11-10 01:14:32 +01:00
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option enables additional malloc related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
2011-07-01 23:44:39 +02:00
|
|
|
|
2018-12-31 14:22:34 +01:00
|
|
|
config DEBUG_CONSOLE_INIT
|
|
|
|
|
bool "Debug console initialisation code"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
With this option printk()'s are attempted before console hardware
|
|
|
|
|
initialisation has been completed. Your mileage may vary.
|
|
|
|
|
|
|
|
|
|
Typically you will need to modify source in console_hw_init() such
|
|
|
|
|
that a working console appears before the one you want to debug.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-11-10 01:14:32 +01:00
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
|
|
|
# printk(BIOS_DEBUG, ...) calls.
|
2010-09-08 00:30:15 +02:00
|
|
|
config REALMODE_DEBUG
|
2012-11-14 02:00:01 +01:00
|
|
|
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
bool
|
2010-09-08 00:30:15 +02:00
|
|
|
default n
|
2010-11-10 03:00:32 +01:00
|
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
2010-09-08 00:30:15 +02:00
|
|
|
help
|
|
|
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
config X86EMU_DEBUG
|
|
|
|
|
bool "Output verbose x86emu debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
|
|
|
help
|
|
|
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
|
|
|
bool "Trace JMP/RETF"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
|
|
|
bool "Trace all opcodes"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print _all_ opcodes that are executed by x86emu.
|
2010-04-27 08:56:47 +02:00
|
|
|
|
2010-03-05 11:03:50 +01:00
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
|
|
|
bool "Log Plug&Play accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
|
|
|
bool "Log Disk I/O"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print Disk I/O related messages.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
|
|
|
bool "Log PMM"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
|
|
|
bool "Debug VESA BIOS Extensions"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
|
|
|
bool "Redirect INT10 output to console"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
|
|
|
bool "Log intXX calls"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to interrupt handling.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
|
|
|
bool "Log special memory accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print messages related to accesses to certain areas of the virtual
|
|
|
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
|
|
|
bool "Log all memory accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print memory accesses made by option ROM.
|
|
|
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
|
|
|
|
config X86EMU_DEBUG_IO
|
|
|
|
|
bool "Log IO accesses"
|
|
|
|
|
default n
|
|
|
|
|
depends on X86EMU_DEBUG
|
|
|
|
|
help
|
|
|
|
|
Print I/O accesses made by option ROM.
|
|
|
|
|
|
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2013-05-15 00:19:49 +02:00
|
|
|
config X86EMU_DEBUG_TIMINGS
|
|
|
|
|
bool "Output timing information"
|
|
|
|
|
default n
|
2019-07-10 14:10:22 +02:00
|
|
|
depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER
|
2013-05-15 00:19:49 +02:00
|
|
|
help
|
|
|
|
|
Print timing information needed by i915tool.
|
|
|
|
|
|
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
2012-05-10 20:27:32 +02:00
|
|
|
config DEBUG_SPI_FLASH
|
|
|
|
|
bool "Output verbose SPI flash debug messages"
|
|
|
|
|
default n
|
|
|
|
|
depends on SPI_FLASH
|
|
|
|
|
help
|
|
|
|
|
This option enables additional SPI flash related debug messages.
|
|
|
|
|
|
2012-04-04 00:07:22 +02:00
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
|
|
|
|
|
# Only visible with the right southbridge and loglevel.
|
|
|
|
|
config DEBUG_INTEL_ME
|
|
|
|
|
bool "Verbose logging for Intel Management Engine"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable verbose logging for Intel Management Engine driver that
|
|
|
|
|
is present on Intel 6-series chipsets.
|
|
|
|
|
endif
|
|
|
|
|
|
2011-09-02 23:23:41 +02:00
|
|
|
config TRACE
|
|
|
|
|
bool "Trace function calls"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If enabled, every function will print information to console once
|
|
|
|
|
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
|
|
|
|
|
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
|
2015-11-18 17:46:53 +01:00
|
|
|
of calling function. Please note some printk related functions
|
2011-09-02 23:23:41 +02:00
|
|
|
are omitted from trace to have good looking console dumps.
|
Implement GCC code coverage analysis
In order to provide some insight on what code is executed during
coreboot's run time and how well our test scenarios work, this
adds code coverage support to coreboot's ram stage. This should
be easily adaptable for payloads, and maybe even romstage.
See http://gcc.gnu.org/onlinedocs/gcc/Gcov.html for
more information.
To instrument coreboot, select CONFIG_COVERAGE ("Code coverage
support") in Kconfig, and recompile coreboot. coreboot will then
store its code coverage information into CBMEM, if possible.
Then, run "cbmem -CV" as root on the target system running the
instrumented coreboot binary. This will create a whole bunch of
.gcda files that contain coverage information. Tar them up, copy
them to your build system machine, and untar them. Then you can
use your favorite coverage utility (gcov, lcov, ...) to visualize
code coverage.
For a sneak peak of what will expect you, please take a look
at http://www.coreboot.org/~stepan/coreboot-coverage/
Change-Id: Ib287d8309878a1f5c4be770c38b1bc0bb3aa6ec7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2052
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-19 01:23:28 +01:00
|
|
|
|
|
|
|
|
config DEBUG_COVERAGE
|
|
|
|
|
bool "Debug code coverage"
|
|
|
|
|
default n
|
|
|
|
|
depends on COVERAGE
|
|
|
|
|
help
|
|
|
|
|
If enabled, the code coverage hooks in coreboot will output some
|
|
|
|
|
information about the coverage data that is dumped.
|
|
|
|
|
|
2016-06-29 21:59:32 +02:00
|
|
|
config DEBUG_BOOT_STATE
|
|
|
|
|
bool "Debug boot state machine"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Control debugging of the boot state machine. When selected displays
|
|
|
|
|
the state boundaries in ramstage.
|
|
|
|
|
|
2016-10-05 17:43:56 +02:00
|
|
|
config DEBUG_ADA_CODE
|
|
|
|
|
bool "Compile debug code in Ada sources"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Add the compiler switch `-gnata` to compile code guarded by
|
|
|
|
|
`pragma Debug`.
|
|
|
|
|
|
2018-07-12 23:26:07 +02:00
|
|
|
config HAVE_EM100_SUPPORT
|
|
|
|
|
bool "Platform can support the Dediprog EM100 SPI emulator"
|
|
|
|
|
help
|
|
|
|
|
This is enabled by platforms which can support using the EM100.
|
|
|
|
|
|
|
|
|
|
config EM100
|
|
|
|
|
bool "Configure image for EM100 usage"
|
|
|
|
|
depends on HAVE_EM100_SUPPORT
|
|
|
|
|
help
|
|
|
|
|
The Dediprog EM100 SPI emulator allows fast loading of new SPI images
|
|
|
|
|
over USB. However it only supports a maximum SPI clock of 20MHz and
|
|
|
|
|
single data output. Enable this option to use a 20MHz SPI clock and
|
|
|
|
|
disable "Dual Output Fast Read" Support.
|
|
|
|
|
|
|
|
|
|
On AMD platforms this changes the SPI speed at run-time if the
|
|
|
|
|
mainboard code supports this. On supported Intel platforms this works
|
|
|
|
|
by changing the settings in the descriptor.bin file.
|
|
|
|
|
|
2009-10-07 18:15:40 +02:00
|
|
|
endmenu
|
|
|
|
|
|
2016-12-15 23:25:15 +01:00
|
|
|
|
|
|
|
|
###############################################################################
|
|
|
|
|
# Set variables with no prompt - these can be set anywhere, and putting at
|
|
|
|
|
# the end of this file gives the most flexibility.
|
2017-05-18 18:07:34 +02:00
|
|
|
|
|
|
|
|
source "src/lib/Kconfig"
|
|
|
|
|
|
2009-11-12 17:38:03 +01:00
|
|
|
config WARNINGS_ARE_ERRORS
|
|
|
|
|
bool
|
2014-11-17 17:17:54 +01:00
|
|
|
default y
|
2009-11-27 17:55:13 +01:00
|
|
|
|
2010-10-13 08:23:02 +02:00
|
|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
|
|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
|
|
|
# mutually exclusive. One of these options must be selected in the
|
|
|
|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
|
|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
|
|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board has a power button which can optionally be
|
|
|
|
|
disabled by the user.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board has a power button which can optionally be
|
|
|
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
|
|
|
the power switch contacts.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board requires that the power button is always
|
|
|
|
|
enabled.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
|
|
|
def_bool n
|
|
|
|
|
help
|
|
|
|
|
Select when the board requires that the power button is always
|
|
|
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
|
|
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
|
|
|
bool
|
|
|
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
|
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
|
|
|
help
|
|
|
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
2013-10-31 16:26:23 +01:00
|
|
|
|
|
|
|
|
config REG_SCRIPT
|
|
|
|
|
bool
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Internal option that controls whether we compile in register scripts.
|
Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-23 19:18:48 +02:00
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config MAX_REBOOT_CNT
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int
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default 3
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2015-03-18 07:31:34 +01:00
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help
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Internal option that sets the maximum number of bootblock executions allowed
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with the normal image enabled before assuming the normal image is defective
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2014-07-23 18:40:02 +02:00
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and switching to the fallback image.
|
Kconfig: Move defaults for CBFS_SIZE
We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults. Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.
- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.
Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.
Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default. Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.
Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-02-09 17:06:46 +01:00
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2016-12-15 23:25:15 +01:00
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config UNCOMPRESSED_RAMSTAGE
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bool
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config NO_XIP_EARLY_STAGES
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bool
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default n if ARCH_X86
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default y
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help
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Identify if early stages are eXecute-In-Place(XIP).
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config EARLY_CBMEM_LIST
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bool
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default n
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help
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Enable display of CBMEM during romstage and postcar.
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config RELOCATABLE_MODULES
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bool
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help
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If RELOCATABLE_MODULES is selected then support is enabled for
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building relocatable modules in the RAM stage. Those modules can be
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loaded anywhere and all the relocations are handled automatically.
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config GENERIC_GPIO_LIB
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bool
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help
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If enabled, compile the generic GPIO library. A "generic" GPIO
|
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implies configurability usually found on SoCs, particularly the
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ability to control internal pull resistors.
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config BOOTBLOCK_CUSTOM
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# To be selected by arch, SoC or mainboard if it does not want use the normal
|
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# src/lib/bootblock.c#main() C entry point.
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bool
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|
2020-06-11 20:59:07 +02:00
|
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config MEMLAYOUT_LD_FILE
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string
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default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/memlayout.ld"
|
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|
help
|
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|
|
This variable allows SoC/mainboard to supply in a custom linker file
|
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|
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if required. This determines the linker file used for all the stages
|
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(bootblock, romstage, verstage, ramstage, postcar) in
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src/arch/${ARCH}/Makefile.inc.
|
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|
|
2016-12-15 23:05:37 +01:00
|
|
|
###############################################################################
|
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# Set default values for symbols created before mainboards. This allows the
|
|
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|
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# option to be displayed in the general menu, but the default to be loaded in
|
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# the mainboard if desired.
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config COMPRESS_RAMSTAGE
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default y if !UNCOMPRESSED_RAMSTAGE
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config COMPRESS_PRERAM_STAGES
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depends on !ARCH_X86
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default y
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config INCLUDE_CONFIG_FILE
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default y
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config BOOTSPLASH_FILE
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depends on BOOTSPLASH_IMAGE
|
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default "bootsplash.jpg"
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config CBFS_SIZE
|
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|
|
|
default ROM_SIZE
|
2019-06-08 08:59:02 +02:00
|
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config HAVE_BOOTBLOCK
|
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|
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bool
|
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default y
|
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|
|
config HAVE_VERSTAGE
|
|
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|
|
bool
|
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|
|
depends on VBOOT_SEPARATE_VERSTAGE
|
|
|
|
|
default y
|
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|
|
config HAVE_ROMSTAGE
|
|
|
|
|
bool
|
|
|
|
|
default y
|
|
|
|
|
|
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|
|
config HAVE_RAMSTAGE
|
|
|
|
|
bool
|
|
|
|
|
default n if RAMPAYLOAD
|
|
|
|
|
default y
|