We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.
BUG=b:223289882
TEST=boot Nipperkin and Dewatt and then verify the devbeep and gpio
values in kernel
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Change-Id: Id874421d7464b15be6e521576696bb97e6b22d6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Configure lcnt and hcnt directly to give the required frequency, tHIGH
and tLOW, instead of using rise and fall times. Aim for a frequency of
390 kHz to make sure it doesn't exceed 400 kHz on different boards.
BUG=b:227517802
TEST=Probe the clock line and check that it meets the requirements for
frequency, tHIGH and tLOW.
Change-Id: I4d4f877c1f0cd9aacd3fa152890b7ef82e059f78
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Create the craask variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:None
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CRAASK
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Icf03e3f18468d7dd207ab200fa2dcf96afd02f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fixes the following build error:
src/mainboard/google/brya/mainboard.c: In function 'variant_generate_s0ix_hook':
src/mainboard/google/brya/mainboard.c:157:40: error: parameter name omitted
void __weak variant_generate_s0ix_hook(enum s0ix_entry)
^~~~~~~~~~~~~~~
BUG=None
TEST=`abuild -a -x -c max -p none -t google/brya` now succeeds
Change-Id: Id578766e2a3b7647e920740dde3e356a7db39d4d
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Select the Bayhub LV2 driver, and implement power sequencing as per the
datasheet.
BUG=b:223304542
TEST=Check that connecting an SD card works as expected in the OS. Probe
the EN and RST signals and check the timing requirements are met.
Change-Id: Id1cca2024e06e5b2c7cefd22aa0b735bc542dc3b
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Based on the latest schematic, change MAX98360 AMP interface from I2S2
to I2S1 due to Intel BT offload concern.
BUG=b:202671753
BRANCH=firmware-brya-14505.B
TEST=dmidecode -t 11
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Change-Id: I9ee45dbceabdedd39a9befffb8002b8bc3d4bfb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for ADL-N boards, therefore disabling it.
BRANCH=NONE
TEST=Build and boot ADL-N RVP. Verify system is entering S0i3 state.
localhost ~ # cat /sys/kernel/debug/pmc_core/substate_residencies
Substate Residency
S0i2.0 0
S0i3.0 13196801
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I44651bf55df8e71a0a5a9a33ecbb8322ecd18575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
CB:63242 solves the missing dependency on _PRS.
The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.
BUG=N/A
TEST=Boot facebook FBG1701
Change-Id: I014a9078cb12908c515a978e4111ff9facc9e443
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
I225 doesn’t support ASPM, so disable it at the root port.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61fe3760c1cde60795c9b52c703e521ba4df504a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
romstage uses FSP and SPD before these are verified.
Verify the FSP and SPD binaries in bootblock and measure these in
romstage.
BUG=N/A
TEST=Boot Facebook FBG1701 and check log for FSP and SPD verified in
bootblock.
Change-Id: I061affa5111fb14d69a8459575e0c72f71b1a1aa
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63446
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2a5888e943c1ebf83a54f9b172f986f8b13d9b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To achieve low power consumption, we disable unused PCIe and SATA
pins at beadrix/overridetree.cb according to baseboard/devicetree.cb
and mainboard schematic. Original measured beadrix board's power
consumption is about 250 mW. After we disable unused PCIe and SATA
pins, as well as, enable the other low power MUX CL (3487086: USB
MUX: Update low power mode of MUX anx7447 used as MUX only |
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/
+/3487086), the measured power consumption achieves about 110 ~ 116
mW, as well as, meets Google battery life for 14 days in the suspend
state and Intel low power consumption about 116 mW.
BRANCH=dedede
BUG=b:204882915
TEST=on beadrix, measured power consumption meets Intel power
consumption.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I79ec524c5ce8f2a79da4aeba084786fb9dac17af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62776
Reviewed-by: Teddy Shih <teddyshihau@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable MKBP (Matrix Keyboard Protocol) interface for all guybrush family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.
BUG=b:227240985
BRANCH=guybrush
TEST=manual test on Dewatt:
Volume Up/Down and Power buttons, Tablet Mode switch
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ic9980f2b5bf10b12f2bd666212b5bce925dc323d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63394
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are currently two issues related to the WLAN power sequencing on
nereid:
- If the EN pin GPP_B11 is not high during cold boot, the SoC gets stuck
in S3.
- During warm reboot, if we only assert RST without pulling the power
low, then the kernel crashes.
As a workaround while we investigate these issues, we pull the EN high
in S5, then actively drive it low in bootblock and high in romstage to
make sure it goes low during warm reboot.
BUG=b:227694137, b:225261075
TEST=Cold boot succeeds, and there's no kernel crash during warm reboot.
Change-Id: I1ca46d9649eff3f96a0e77db594d87288b29a83a
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
BUG=None
TEST=evtest works:
Select the device event number [0-14]: 9
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 1
Properties:
Testing ... (interrupt to exit)
Event: time 1649153020.275201, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153020.275201, -------------- SYN_REPORT ------------
Event: time 1649153025.848689, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153025.848689, -------------- SYN_REPORT ------------
Event: time 1649153028.383195, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Event: time 1649153028.383195, -------------- SYN_REPORT ------------
Event: time 1649153080.869155, type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: time 1649153080.869155, -------------- SYN_REPORT ------------
Change-Id: I0d5134737fc758a43e1fff95e9f2a20200991bb1
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Some bytes in the descriptor need to be set differently for Type-C and
HDMI. To allow using a single firmware variant for both cases, update
the descriptor at runtime based on fw_config. This is a temporary
workaround while we find a better solution.
The byte values were determined by changing the following CSE strap and
comparing the generated descriptors:
Type-C: TypeCPort2Config = "No Thunderbolt"
HDMI: TypeCPort2Config = "DP Fixed Connection"
The default value before updating the descriptor is Type-C, but this was
chosen arbitrarily.
BUG=b:226848617
TEST=Type-C and HDMI both work on nereid with fw_config set correctly.
Change-Id: I2cc230e3bd35816c81989ae7e01df5d2c152062e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sam McNally <sammc@google.com>
FLASH is often used when accessing FMAP base and size from
fmap_config.h so it's handy to be consistent with all other boards.
Change-Id: Ibba938c72d42ac74dcea8e8e6478ddae510d8c03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Setting the clock source depends on clock request pin for WLAN/SD/SSD
device. Also turn off the unused (CLKREQ#3) clock sources.In skyrim,
clock source 0/1/2 are routed for WLAN/SD/SSD device.
BUG=b:227297986
BRANCH=none
TEST=Build
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I21fb912b69f59717eb4e84c379f706a0257a9ed1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The only purpose of mainboard_chromeos_acpi_generate()
was to pass cros_gpio array for ACPI \\OIPG package
generation.
Promote variant_cros_gpio() from baseboards to ChromeOS
declaration.
Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove the subsystem device ID for HDA devices, so that the correct
Intel [8086:xxxx] is used. This was an old workaround for Windows
that is no longer required with a new driver.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50c03a2df06af3ef1939afd0739e083a9056557f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The hob finding functions are never looped over so there is no point
for the 'next' inside their name.
Change-Id: I18e452d313612ba14edda479d43f2797f6c84034
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This field was never meant to be filled out by coreboot, because it
can't know what the right value for this will be by the time the OS
is running, so anything coreboot could fill in here is premature.
This field is only read by the chromeos-specific `crossystem` utility,
not by kernel code, so if one does not run through depthcharge there'll
be many more broken assumptions in CNVS anyway.
Change-Id: Ia56b3a3fc82f1b8247a6ee512fe960e9d3d87585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Motivation is to have mainboard_chromeos_acpi_generate()
do nothing else than fill ACPI \OIPG package.
Change-Id: I3cb95268424dc27f8c1e26b3d34eff1a7b8eab7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The value at offset 329 should be:
0x4B -> "K" not 0x48 -> "H" in ASCII code.
BUG=b:224884904
TEST=Build, confirm the part number is matched the corresponding parts
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I35dc5f036a29cdf4763389b6425df99ff63bbfa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special SPD files. This
commit overrides the default SPD files used for these parts
BUG=b:224884904
TEST=Verified that Dewatt SKU1 and SKU3 boot with changes
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ibd08f109765933640ea3d0ad442873c30fa14bc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
CB:63244 solved the missing dependency on _PRS
The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.
BUG=N/A
TEST=build facebook monolith and verify no IASL warning is reported.
Change-Id: I0d7c99e69d56aa8ebe08b52c91ef800390263185
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63245
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IASL reports warning on missing _SRS.
Devices have fixed configuration which is always enabled.
Remove _PRS for this fixed configuration.
BUG=N/A
TEST=built facebook monolith and verify no IASL warning is reported.
Change-Id: I554d3497255c1e50cdbe74b1cffc9f2c59fbae77
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63244
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No functional change, just refactoring to make room for CMT variant.
Built with BUILD_TIMELESS=1 and no config included before and after.
$ diff master.rom build/coreboot.rom
$
TESTED: boots to SeaBIOS on HP Z220 SFF
Flashed bios region internally, mainboard also has FDO
(flash descriptor override) jumper that allows r/w to whole flash.
Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
CB:63248 solves the missing dependency on _PRS
The config IGNORE_IASL_MISSING_DEPENDENCY can be removed.
BUG=N/A
TEST=Build portwell M107
Change-Id: I2ed9fdd541ba9431e59364a42dd03f60b54b6720
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63249
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IASL reports warning on missing _SRS.
Device has fixed configuration which is always enabled.
Remove _PRS for this fixed configuration.
BUG=N/A
TEST=build portwell m107
Change-Id: Idbc0a67136326c9231c168bfd8fadd2539da6745
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63248
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C parameters to make sure I2C1 and I2C7 bus speed is around 1MHz.
BUG=b:207333035
BRANCH=none
TEST=built and verified adjusted I2C speed around 1MHz
Change-Id: I09a9edf723bb1198bbf5d71248abc07276cd94ff
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63241
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Use dedicated ALERT pin to resolve NO_RESPONSE error/status while
getting target configuration.
* Configure the ESPI to operate at 16 MHZ since operating at 33 MHz
causes boot stall.
BUG=b:226635441
TEST=Build and Boot to OS in Skyrim. Ensure that EC <-> AP communication
is working fine through Host Command debug logs in EC console, ectool
version command.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I951afdada8ee4f917cdeba8e287e5a2ae77c97ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63286
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Found an issue where emmc and sd clocks were being misconfigured due
to using incorrect integer values when called instead of the defined
enums. Fixing by splitting the clock_configure_sdcc() function into
two (sdcc1 and sdcc2) as there was no commonality between the two
cases anyway. As a result, we can also get rid of the clk_sdcc enum.
BUG=b:198627043
BRANCH=None
TEST=build herobrine image and test in conjunction with CB:63289
make sure assert is not thrown.
Change-Id: I68f9167499ede057922135623a4b04202f4da9b5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The Dell OptiPlex 9010 uses a Q77 PCH, which is Panther Point. The only
difference is the definition of the `CROS_GPIO_DEVICE_NAME` macro, which
is not used for non-ChromeOS coreboot builds.
Change-Id: I7ad07b464aef24f7749c3fe9300b7f7dd865e47b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The PCH's PCIe ports do not support Gen3 speeds, only Gen1/Gen2.
Change-Id: I7df61af1953ec99000c6c501b017e553190a46b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It was enabled due to known compatibility issues with Qubes OS.
Since the release of R4.1.0, this issue is no longer present so
it can be disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iab6048dc93112b9365f0c2b46225569073eb32f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes
eSPI transactions. If the SMI interrupts an ongoing eSPI transaction
from the OS it will conflict and cause failures. Removing this call to
avoid conflicts. This can be re-enabled after refactoring
google_chromeec_get_mask to use ACPI MMIO.
BUG=b:227163985
BRANCH=gubyrush
TEST=No 164 errors detected during suspend_stress_test
/sys/firmware/log output after resume before change:
SMI# #1
ELOG: Event(B0) added with size 9 at 2022-03-31 19:52:51 UTC
GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000
ELOG: Event(9F) added with size 14 at 2022-03-31 19:52:51 UTC
Chrome EC: clear events_b mask to 0x0000000000000000
after change:
SMI# #6
ELOG: Event(B0) added with size 9 at 2022-03-31 19:50:19 UTC
GPIO Control Switch: 0xcf000000, Wake Stat 0: 0x00000000, Wake Stat 1: 0x00000000
ELOG: Event(9F) added with size 14 at 2022-03-31 19:50:19 UTC
Change-Id: I3320e3fb8bd9e9e0db84332e1d147a0af25f7601
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling rtd3 reduces power consumption when the SSD is idle.
Tested and verified on the StarBook Mk V (TGL), using PowerTop
on Manjaro 21.2.5 GNOME at 20% Brightness.
Signed-off-by: Stephen Edworthy <stephen@starlabs.systems>
Change-Id: I0d8aa185a322bb8d1aba51ccaab03c521cec2770
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
BUG=b:226848617
TEST=HDMI works on nereid
Cq-Depend: chrome-internal:4650256
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6a90d3d86b32f73ec0130e582539d1c5b045da62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
BUG=b:226848617
TEST=HDMI works on nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I039c30f95d959dba489b24b6938d08da937c5e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add support for ELAN trackpad on I2C0 bus.
BUG=None
TEST=Build and boot to OS in Skyrim. Perform evtest on Elan trackpad.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia1522af3f35ef131dda74c4aabecc4fa532dfbec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Removing unnecessary "czn" in variable name. Majolica is always a
cezanne.
TEST=Timeless build
Change-Id: I490111ecea84c934585d0bbd623486fba76eb7f1
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63261
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove "czn" from the variable names since chausie does not use cezanne.
TEST=Timeless build
Change-Id: I8cc854f4c60707c7fec5cd7fef1c4550883cd45a
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Turn off the NFC power which is controlled by GPP_D3 to save power in
S0ix states. For an USB device, the S0ix hook is needed for the on/off
operations to take place.
BUG=b:202737385
BRANCH=firmware-brya-14505.B
TEST=measure the voltage of GPP_D3 in S0ix states
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.
BUG=b:223936777
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
C0 has no redriver, so enable SBU muxing in the SoC.
C1 has a redriver which does SBU muxing, so disable SBU muxing in the
SoC. However, this also disables AUX biasing when the pins are
configured as NF6. So instead configure the C1 AUX bias pins as GPO.
BUG=b:227259673
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
Doesn't work:
- TPM interrupt on Linux [1]
- All EC related functions - EC driver is WIP
- WLAN/BT (PCIe) - gets detected but can't be enabled
- 3G/LTE (not powered without EC driver)
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Based on the latest schematic, agah will replace the Maxim 98390
speaker amps with Maxim max98360. This patch updates the
devicetree entries to reflect that.
BUG=b:210970640
BRANCH=brya
TEST=emerge-draco coreboot
Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support
fingerprint. This patch sets GPP_D0 to NC for matching schematic.
BUG=b:214025396
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
On platforms using UDK2015 select UDK2017 instead.
This allows to drop UDK2015 headers.
Tested using timeless builds: The produced binaries are identical.
Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
RF team comfirmed that SAR sensor is not necessary for MP,
therefore remove the corresponding entries from the devicetree.
BUG=b:202978964
TEST=Build pass.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I31faf18563848f8d6787fe70bfb28006efea8427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf
BUG=b:219891328
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We are using the second SPI pads for eSPI.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43713d7376a28ced2be635668836464ceec46392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the specific SPD hex file for the Samsung memory part with
updating the part number into the SPD table. The ABL needs to
identify the part by checking SPD data to do the proper tuning.
BUG=b:224884904
TEST=Build, validate the SPD data has been applied.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Update the GPP_D12 according to USB_C3_LSX_RX.
BUG=b:225081954
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The device can be recognized when it is attached in port3.
localhost /sys/bus/thunderbolt/devices # ls
0-0 1-0 1-0:3.1 1-3 domain0 domain1
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.
BUG=b:223289882
TEST=boot guybrush and verify the devbeep and gpio value in kernel
Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Move the verb table to variant directory to allow for different tables
for different variants.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rather than using `ite_`, use `ec_` so the same functions
can be called for different ECs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move WWAN power on sequence from OS to coreboot. This can save the
WWAN initial time about 10S. Another purpose is power resource be
removed because we don't power off the LTE in S0ix.
BUG=b:223490884
TEST=FM101-GL work as expected.
Enumerate time from
[ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module
[ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 17.760224] usb 4-2: SerialNumber: 9c88998f
to
[ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module
[ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 4.019762] usb 4-2: SerialNumber: 9c88998f
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for
ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake
A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is
locked in the production systems, so the Kconfig is deselected.
TEST=Build the coreboot for adlrvp
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Only enable the PCIe root ports that have corresponding DXIO descriptors
and also update the comments to have them match the actual hardware
configuration.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I378c620abb6e52de680669b6edd228874153e399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the DXIO descriptors to match the default PCIe lane mapping on
the chausie board. With this configuration and a board-level rework to
bypass the EC control of the NVMe SSD power supply rail, this
configuration results in the SSD being detected on the root port on bus
0 device 2 function 3 and usable as boot device. This was also validated
against the schematics revision B.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the Moli GPIO Table_20220324.xlsx to update it.
1.Set A15 as the default value.
2.Set A14, A19 NC.
3.Set C3, C4 as the default value.
4.Set D9 as the default value.
5.Set E5, E13 as the default value.
6.Set R4, R5 as the default value.
7.Update E14.
8.Set E12 as the default value.
9.Set D16 as the default value.
BUG=b:220821454
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia54256244111a99cb130b74f78c37815099a021a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
While adding this train of patches to program the dGPU power sequences,
I noticed some of the GPU GPIOs are incorrectly programmed in ramstage,
so this patch fixes the settings.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.
Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Configure GPIO according to b:224107199 comment#15.
- GPP_E19 from NF to NC.
BUG=b:224107199
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The Cherry follower projects may choose Max98390 for audio output
so we have to add a new config CHERRY_USE_MAX98390. Also, the
'dojo' device is the first one to use it.
BUG=b:204391159
BRANCH=cherry
TEST=emerge-cherry coreboot
TEST=Verify beep function through CLI in depthcharge successfully
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will setup the eSPI GPIOs in bootblock right before eSPI init.
BUG=b:226635441
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The eSPI CS function only exists on AGPIO30.
We will need to rework all boards to make eSPI function.
I also fixed the comments on the other eSPI pins.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add Skyrim DXIO descriptors using info from AMD and skyrim bouard
shematics.
BUG=b:225179599
TEST=Boots to OS on Skyrim Board
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Implement the GPIOs that have been changed from genesis.
- Connect scaler UART on pins C12/C13
- Connect the HDMI redriver I2C on C18/C19
- Connect the iMX8 signals on D1/D2/D3/D21/D22
- Connect the EC interrupt on D14 (same as on scout)
- Connect PCH_TYPEC_UPFB on E15 (same as on genesis)
- Configure as not connected the following unused pins: D23, E11, E12,
F11 -> F22, H0, H8, H9
BUG=b:200876872
TEST=moonbuggy boots
Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3
Signed-off-by: Pablo Ceballos <pceballos@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Using the GPP_F22 as mic mute switch based on the latest schematic.
BUG=b:223737606, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The mic_mute event is changed when the mic_mute GPIO pin is switched.
Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0
Event: time 1647939954.639995, -------------- SYN_REPORT ------------
Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1
Event: time 1647939954.648152, -------------- SYN_REPORT ------------
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently, we control the GPP_D0 in the flash_fp_mcu in order to
program the component's firmware. If we set this pin to NC, then we
can't control the GPP_D0 output low/high and that make the system fails
to program the component's firmware. This patch sets the GPP_D0 to GPO
to fix it.
BUG=b:204679292
BRANCH=firmware-brya-14505.B
TEST=program the component's firmware
Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Based on Brya EVT schametic, replace audio amp max98357 with max98360.
Add a new audio FW_CONFIG field to support ALC5682I+MAX98360.
BUG=b:224423056
BRANCH=firmware-brya-14505.B
TEST=dmidecode -t 11
Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use MOCK TPM in vboot, since TPM is not enabled in ADLN RVP.
BRANCH:NONE
TEST=build and boot ADL-N RVP. Verify no TPM errors in depthcharge.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ibc0112545dbd80921d89d48eff58c512729243af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This
commit assigns them exclusive IDs 9 and 11 to facilitate this.
BUG=b:224884904
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ABL generates memory training data whose size is ~80KiB. So increase the
RW_MRC_CACHE region size to accommodate that.
BUG=b:224618411
TEST=Build and boot to payload in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The separate FMD file for Kano is no longer required, as it was
only required for early prototype testers, and those devices will
be retired soon, therefore switch back to the original FMD file.
BUG=b:226018550
TEST=Build pass.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.
BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR] cr50_i2c_read: Address write failed
[INFO ] .I2C stop bit not received
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Precision is a Mid Tower chassis platform with very similar mainboard
to OptiPlex 9010. It has one more PCIe port and a PCI port. It also
incorporates C216 chipset instead of Q77 and enables DRAM ECC support.
Other changes are related to subsystem ID and fan control
initialization.
TEST=Boot Dell Precision T1650 and launch Debian 10.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4ec2013d5f53af36cab0d1def19272f5ef1a9516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
New boards like Dell Precision T1650 will be added as variants, in
subsequent commit. They share most of the code, except some EC
initialization tables, PCIe port configuration and subsystem ID.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Update the two load line slope settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD scale: 73331 -> 94623
VDD offset: 1893 -> 1847
SOC scale: 31955 -> 29904
SOC offset: 852 -> 756
BUG=b:217963719
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass AMD SDLE/Stardust test
Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Backlight GPIO was set to HIGH, when it should have been set LOW to
enable the backlight in the embedded display.
BUG=b:224618411
TEST=load on Skyrim proto1, observe backlight
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current behavior does not actually check if a device is present
before enabling the corresponding gpp_clkx_clock_request_mapping bits
which may cause issues with L1SS. This change sets the corresponding
gpp_clkx_clock_request_mapping to off if the corresponding device is
disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value
when devices are enabled/disabled, checked that physically removing a
device that is marked as enabled also disables the corresponding clk req
BRANCH=guybrush
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61259
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change settings according to thermal team test results
BUG=b:215033682
TEST=build and tested fan works normally on taniks
Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fix the HWM sequence matching to the chassis. HWM sequence for SFF
was incorrectly passed to MT chassis HWM initialization.
Vendor code also applies a fix-up for MT/DT chassis. This fixup was
missing one register read compared to the vendor code. Add the missing
read and guard the fixup depening on the returned value to match the
vendor code behavior. Not doing so resulted in increased fan speeds
on Dell Precision T1650 compared to Dell's firmware.
TEST=Boot Dell Precision T1650 and hear the fans are as silent as on
Dell's firmware
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Enable/disable LTE function based on LTE field of FW_CONFIG.
1. GPIO control
2. USB port setting
BUG=b:213582491
BRANCH=dedede
TEST=FW_NAME=beadrix emerge-dedede coreboot
Change-Id: Icea44992e2e3195d1fd9a888f5ce4650f82280bb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62801
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2.
BUG=b:224648680
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 2500 cycles passed on primus
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Commit 5a0ad1186 missed one chip config member that got converted to
snake case in commit 215a97ee1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie92106f0fee0bb18863b7063c07673e0f7995c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63005
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
init overridetree.cb based on the schematic adl_rfq_mb_20220310.pdf
BUG=b:220814038
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set the GPIO configuration of crota by bernadino 14 adl-p 20220112.pdf
BUG=b:219891328
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I164bc7a8b682eb8682f02b06708bc7c72a5c449a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Kinox is designed to 8-layer PCB. In order to reduce the length of
memory singals, the DDR4 is designed from interleaved to
non-interleaved.
BUG=b:210094309
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I03c6fcccf8b1646cec1a35cc1f9cbb1cfb942c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
GL9763e doesn’t support L0s state, so disable L0s at the root port.
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
The workaround causes the eMMC controller to not enter its L1
during the boot process
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
The APCB files that provide the firmware components running on the PSP
some mainboard-specific information like the DRAM interface
configuration. Those files aren't yet in the upstream 3rdparty/blobs
repository, so only add those files if they are present and print that
no APCB was added and the image won't boot if they aren't present.
TEST=Both cases behave as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1e8621901741b8b0531fe134273b47e85911e19f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
To have enough space in the A/B RW sections, increase those sizes to 4
MByte and decrease the RO section size to 6 MByte to free up the space
needed for that.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib107fd05cfb0ef7de95425abcce6c82b88a9835d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add WiFi SAR table
BUG=b:225285426
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I8fa833409bd69e080fda735c89015b9548252190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This was to merge PCIe ACPI code to WWAN device. Also, RTD3 devices are
add to overridetree.cb where WWAN is present for vell.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Change-Id: If27abcf31ed948899bfaecbe8ef494fe8a80609b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig which
updates PMC settings in the IFD for Alder Lake A0 silicon.
As Alder Lake A0 is intermediate stepping, and the IFD is locked in the
production systems, so the Kconfig is deselected.
BUG=b:190588098
BRANCH=firmware-brya-14505.B
TEST=Build the coreboot for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I81fe7c792dd82d9d547d318ebda55ee4a0f3ac96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Although the panel initializes fine and the fw recovery screen is
displayed without issues, the current power-on sequence of the
PS8640 violates the spec of the PS8640, which can be confirmed by
measuring it with an oscilloscope.
The sequence is:
- set VDD12 to be 1.2V
- set VDD33 to be 3.3V
- pull hign PD#
- pull down RST#
- delay 2ms
- pull high RST#
- delay more than 50ms (55ms for margin)
- pull down RST#
- delay more than 50ms (55ms for margin)
- pull high RST#
This flow will increase 110ms if firmware display is enabled in
krabby. For normal booting flow, the firmware will not be enabled,
so it will meet boot time requirements of Chrome OS. (Less than 1s.)
Datasheet name: PS8640_DS_V1.4_20200210.docx.
Chapter: 14.
BUG=b:222650141
TEST=show fw display normally in krabby.
TEST=result of waveform meets the spec.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7706c56dc7fc13ac84c0d52a6e534bc0988e8fd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, the PSPP policy will be switched to balanced again.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I85a06f322c4ddff25c3a858e2b79c84b36c48932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller.
BUG=b:222976965
TEST=emerge-dedede coreboot
Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Use GEN3 from enum dxio_link_speed_cap instead of the number 3.
TEST=Timeless build results in identical firmware image for guybrush
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Commit 215a97ee1c (soc/intel/adl/chip.h:
Convert all camel case variables to snake case) converted the camel case
used in the parameter name to snake case, but
commit bd529e2e20 (mb/google/nissa/var/
nivviks: Add TcssAuxori for nivviks) still used the old names which
breaks the upstream build. his patch is intended to be merged via
fast-path before the 24h are over to fix the tree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b9049553889c77bd8c59a2c4564d36d836a4eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62927
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable SBU orientation handling by SoC for both USBC port0 and USBC
port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver,
but that do not flip the data lines. Hence we need to set bits for both
the USBC ports.
BRANCH:None
TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on
nivviks board and verified USBC display is working on both the ports in
normal and inverted connections.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the latest schematic, replace amp max98357 with max98360.
BUG=b:224692387, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id265a4276c3f8b5553a0e5d7ed824b1d9a520d44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add wifi sar for galnat/galnat360
Use SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
galnat (sku id:0x140000)*
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
galnat360 (sku id:0x2B0000)*
BUG=b:222008376
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I868a7416a002732736cabea48ce80548ea75e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Volmar does not support Thunderbolt, therefore disable all of the TBT
devices in the devicetree. The volmar fit image had been disabled already, cf. chrome-internal:4459289.
BUG=b:2233193
TEST=Build and run on DUT.
Change-Id: Ic1bba80707b1d4a97c486e22f79feccf6241865e
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Configure GPIOs according to updated schematics.
- GPP_A21 from NC to TCP_DP1_CTRLCLK.
- GPP_A22 from NC to TCP_DP1_CTRLDATA.
- GPP_E22 from DDIA_DP_CTRLCLK to NC.
- GPP_E23 from DDIA_DP_CTRLDATA to NC.
BUG=b:214025396
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9d2d73820fbb191b682713e4e351c6375927ddf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This sets EPP value to be 45% for all Adl RVP variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Use C code to generate MS0X entry and provide variant hook.
BUG=b:207144468
TEST=check SSDT table has the same entry.
Scope (\_SB)
{
Method (MS0X, 1, Serialized)
{
If ((Arg0 == One))
{
\_SB.PCI0.CTXS (0x148)
}
Else
{
\_SB.PCI0.STXS (0x148)
}
}
}
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic36543e5cbaf8aaa7d933dcf54badc5f40e8ef02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This was to merge PCIe ACPI code to WWAN device. But, now use recent
_DSD generation changes in FM driver instead. PCie generic driver is
not used for WWAN at this time.
Also, RTD3 devices are moved to overridetree.cb where WWAN is
present.
BUG=b:221250331
BRANCH=firmware-brya-14505.B
TEST=
Check that _DSD is added to WWAN device in SSDT for the variants.
Check that RTD3 is added to WWAN device in SSDT for the variants.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia343c7545cf30bdbcd1de19e5eb84049dbb2977f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Follow thermal team design to update thermal table.
BUG=b:223492897
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5da776e7ae3368ce00cd29ec0ccdb5b7a725ff88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Follow the latest schematic change, gpio will match the baseboard.
Return the current table as override.
BUG=b:223677877
TEST=audio is functional on board_0.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I91dc2c9c8811d403c60a4b4f3a7c5ed8de4e527e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Move selects from Kconfig.name to Kconfig so that the configuration is
in one place and not distributed over two files.
Change-Id: I500f6422c1f8975de8b0bcc8b95cba2bcd4ebe27
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename `BOARD_HP_SNB_IVB_LAPTOPS` to `BOARD_HP_SNB_IVB_LAPTOPS_COMMON`
to indicate and to make it clear that this option serves as base for
others.
Built HP EliteBook Revolve 810 G1 with BUILD_TIMELESS=1 and also with
`INCLUDE_CONFIG_FILE` disabled. coreboot.rom remains identical.
Change-Id: Icadeb8a33ae0787d2cd5da460065a2ed15256d64
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
