Commit graph

5239 commits

Author SHA1 Message Date
Sumeet R Pawnikar
633e0f2264 soc/intel/alderlake: remove duplicate PL2 override
PL2 override value is already declared under common code in power_limit.h file.
Removing this duplicate PL2 override from soc specific header file.

BRANCH=None
BUG=None
TEST=Built and tested on brya

Change-Id: I1424f36fbe038d478f4b8f6257d78d4a3ede3258
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-04 15:03:44 +00:00
Tim Wawrzynczak
b1623f23c0 soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros
The usage of `pci_devfn_t` here is misleading, as these intentionally
store the `PCH_DEVFN_*` macros so they can be used across `smm` and
`ramstage` without requiring the device model. Update to `unsigned int`
instead, as `pci_devfn_t` implies the data is an MMCONF-compatible PCI
devfn offset.

Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52808
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 16:28:53 +00:00
Tim Wawrzynczak
93982c3a6e device: Switch pci_dev_is_wake_source to take pci_devfn_t
With the recent switch to SMM module loader v2, the size of the SMM for
module google/volteer increased to above 64K in size, and thus failed to
install the permanent SMM handler. Turns out, the devicetree is all
pulled into the SMM build because of elog, which calls
`pci_dev_is_wake_source`, and is the only user of `struct device` in
SMM. Changing this function to take a pci_devfn_t instead allows the
linker to remove almost the entire devicetree from SMM (only usage left
is when disabling HECI via SMM).

BUG=b:186661594
TEST=Verify loaded program size of `smm.elf` for google/volteer is
almost ~50% smaller.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4c39e5188321c8711d6479b15065e5aaedad8f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-03 16:28:42 +00:00
ravindr1
745965763b soc/intel/alderlake: Enable HWP CPPC support in CB
Kconfig change which enables the hwp cppc acpi support is to get the
maximum performance of each CPU to check and enable Intel Turbo Boost
Max Technology.

BUG=none
BRANCH=none
TEST=check GCPC and CPC generated in acpi tables for each CPU

Change-Id: I5d93774e8025466f1911cf77459910fe872bfcc8
Signed-off-by: ravindr1 <ravindra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:41:53 +00:00
Meera Ravindranath
a3f7debc89 soc/intel/alderlake: Fill FSPM UPDs for VT-d configuration
Update UPDs required for configuring VT-d.

TEST=Boot to kernel, load ChromeOS VM.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I96a9f3df185002a4e58faa910f867ace0b97ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51849
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-03 07:41:31 +00:00
Felix Singer
edca63e796 soc/intel/cannonlake/include: Drop unused code
`soc_vtd_resources` from the else-part is unused since Cannon Lake was
removed. Thus, drop it and that if-else-condition.

Change-Id: I21689d1eae6952a80c98096443e7506a1466c07e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-02 20:31:19 +00:00
Felix Singer
a32a57929b soc/intel/skylake: Remove useless help texts
Remove useless help texts since they don't add any more value.

Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02 19:43:32 +00:00
Felix Singer
38dc194485 soc/intel/cannonlake: Remove useless help texts
Remove useless help texts since they don't add any more value.

Change-Id: Id8a15681a98ceb648814662545f5a3bf0f14b95c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52777
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-02 19:42:50 +00:00
Timofey Komarov
756f51b662 soc/intel/skylake: Add Kconfig option for LGA1151v2
Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults
for the combination of a Union Point PCH with LGA1151v2.

As of the year 2021 it's common for motherboards with Z370, H310C
or B365 PCHs, which are meant to be paired with Coffee Lake CPUs.
Intel provides AmberLakeFspBinPkg to support this combination,
which implements Intel FSP External Architecture Specification v2.1.

Details:

1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects
PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and
SKYLAKE_SOC_PCH_H.

2) Add Amberlake FSP support.

If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead
of KabylakeFspBinPkg.

3) Enable Coffee Lake CPUs support.

If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select
MAINBOARD_SUPPORTS_COFFEELAKE_CPU.

4) Increase stack and heap size in CAR.

If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1),
update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values.

5) Update maximal number of supported CPUs.

If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16.

Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-05-01 18:03:18 +00:00
Timofey Komarov
7e7d27bf4b soc/intel/skylake: Add microcodes for Coffee Lake CPUs
The Z370, H310C and B365 PCHs use the same silicon as 200-series
PCHs and they are supported by soc/intel/skylake codebase
(not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired
with Coffee Lake CPUs, so add the corresponding microcodes.

Signed-off-by: Timofey Komarov <happycorsair@yandex.ru>
Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-05-01 18:02:59 +00:00
Patrick Rudolph
985009ad14 soc/intel/common/block/hda: Use azalia device code
The code is already compiled in on all platforms. Use it as it provides
the same functionality. Note that GCAP is no longer R/WO on these
platforms. However, select `AZALIA_LOCK_DOWN_R_WO_GCAP` just in case.
This will be dropped in a follow-up.

Tested on Prodrive Hermes, still detects and initializes both codecs.

Change-Id: I75424559b2b4aca63fb23bf4f8d5074aa1e1bb31
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50795
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 16:32:34 +00:00
Angel Pons
49c20c00e4 soc/intel: Add Z370, H310C and B365 device IDs
Intel document 335192-004 contains the PCI device IDs for Z370 and
H310C, but lacks the ID for B365. The ID appears on some websites:

https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc

Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:14:46 +00:00
Angel Pons
b45a769939 soc/intel: Add Kaby Lake PCH-U base device ID
Taken from Intel document 334658-003 (7th Generation Intel Processor
Family I/O for U/Y Platforms and 8th Generation Intel Processor Family
I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2).

Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:14:35 +00:00
Angel Pons
9f7e08be61 soc/intel/skylake: Shorten report_platform PCH-H names
For brevity's sake, just print the PCH model.

Change-Id: Ib9e96683e3cb0b63a11344f3b5383292bff88e13
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52701
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:13:27 +00:00
Angel Pons
f530e363d1 soc/intel: Rename 200-series PCH device IDs
The code name for these PCHs is Union Point, abbreviated as `UPT`. There
are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant
to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs,
and referring to them as `KBP` (Kaby Point, I guess) would be confusing.

Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical.

Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:13:20 +00:00
Angel Pons
0129393a6b soc/intel/skylake: Drop Lewisburg PCHs from report_platform
These PCHs are used with Xeon-SP processors, which use different code.

Change-Id: I05f67cd57aa9f867e2fab88cd49e0384073a0b20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52699
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28 14:11:28 +00:00
Angel Pons
a8753e9cbb haswell/broadwell: Replace remaining MCHBAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1
remain identical.

Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 18:39:58 +00:00
Tan, Lean Sheng
2ffa9c6f29 soc/intel/elkhartlake: Remove elog.c
Remove elog.c from EHL soc as EHL does not support chromebook and
hence does not need it.

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 08:32:20 +00:00
Tan, Lean Sheng
6e9d8067ca soc/intel/elkhartlake: Update GPIO communities
GPIOs are divided into different communities. Each community
consists of one or more GPIO groups. We need to configure the
groups in coreboot so that they are mapped properly.

GPIO communities should be properly configured in GPIO_CFG and
MISCCFG registers. GPP_* defines in gpio_soc_defs.h are configured
in GPIO_CFG register while the PMC_GPP_* in pmc.h.

GPIO communities in coreboot should match with the kernel gpio
communities also. Kernel reads the ASL file from coreboot. This
patch adds the proper community mapping in ASL code to match with
kernel code. In gpio_soc_defs.c file we are indexing the groups
correctly. In gpio.h file we define all the gpio devices as kernel
populates sysfs with separate gpio device for each community. This
patch is created based on Intel EHL PCH Datasheet with Document
number 614109 and Chapter 21.

Also update GPIO COM3 Port ID and 2 GPIO register values
(HOSTSW_OWN_REG_0 & PAD_CFG_BASE) respectively.

Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ifc609b3d6ab9ea2b807dc0f178ec99f95d2db4cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-04-26 08:32:13 +00:00
John Zhao
baecee1052 soc/intel/alderlake: Use device ID from pci_devs header file
This change applies device ID from the SoC pci_devs.h directly.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic5d2910ca53c02527aef0ad33ed52a35f2bdf7af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 08:27:54 +00:00
John Zhao
24ae31cdc6 soc/intel/alderlake: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I14c34ad66a5ee8c30acabd8fe5a05c22087f9120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26 08:27:46 +00:00
John Zhao
ae3f524a1f soc/intel/tigerlake: Use device ID from pci_devs header file
This change applies device ID from the SoC pci_devs.h directly.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0c3bd60c62664337429e6817d2cf54cf2e8d500b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26 08:27:34 +00:00
Marc Jones
b20d694622 soc/intel/xeon_sp/cpx: Add UPI locks
Add UPI locks as indicated by the Intel docs.

Change-Id: I9d1336e57f1776f3024883d6edcf0a855b1382c6
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23 14:52:14 +00:00
Marc Jones
456b7ba842 soc/intel/xeon_sp/cpx: Add IMC locks
Add IMC locks as indicated by the Intel docs.

Change-Id: Id5c43711e80f4e2112c305a9b48d0a4c8509e89b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23 14:51:44 +00:00
John Zhao
a66b816675 soc/intel/jasperlake: Remove TCSS setting from the DMAR table
The Jasperlake does not support TCSS. This change removes the TCSS
setting from the DMAR table.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I573e2038fd76ac66af88125117774b40cc80c704
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52575
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23 14:48:04 +00:00
Sumeet R Pawnikar
a2a90a3157 soc/intel/alderlake: Add DPTF HIDs for Alder Lake SoC
Add DPTF HIDs for thermal funcitonality for Alder Lake SoC.

BRANCH=None
BUG=None
TEST=Built and tested on adlrvp board

Change-Id: I8de58497fa800690d04abbdfe4d6abf1c0184334
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52268
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23 14:46:33 +00:00
Angel Pons
8122b3f612 soc/intel/xeon_sp: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

Change-Id: Ia5fedb6148409f9c72848c9e227e19bedebb5823
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23 14:44:27 +00:00
Michael Niewöhner
305b6488e4 soc/intel/cannonlake: set MSR LT_LOCK_MEMORY at end of POST
FSP does not set the MSR LT_LOCK_MEMORY when SkipMpInit=1. Therefore,
set LT_LOCK_MEMORY at end of POST, when native MP init is used, to
protect SMM in accordance to Intel BWG.

Test on clevo/cml-u: chipsec says LT_LOCK_MEMORY is locked.

Change-Id: Iaadd4996653c4f27d268b1c4773c1e2e86114912
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36356
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22 22:44:57 +00:00
Michael Niewöhner
348f2a6370 soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP init
FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0.
Thus, only set the lock when native MP init is used (SkipMpInit=1).

Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22 19:42:05 +00:00
Michael Niewöhner
6e64c1a4e0 soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per thread
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it
once.

Tested on Acer ES1-572 by checking chipsec results.

Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22 19:41:29 +00:00
Sugnan Prabhu S
50f8b4ebdd soc/intel/alderlake: Add enum for HDA audio configuration
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.

TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.

Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22 15:59:25 +00:00
Furquan Shaikh
c1c1ba5582 soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.

This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.

BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.

Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22 15:59:16 +00:00
Felix Singer
efa5a46350 soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore,
default to 512 in the SoC Kconfig and drop it from related mainboard
Kconfigs.

Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22 10:23:30 +00:00
Marc Jones
d77b97dc9a soc/intel/xeon_sp: Set PAM0123 lock
Set the PAM0123 lock as indicated by the Intel documentation.
This is set is finalize to allow any part of coreboot to update
the PAM prior to booting.

Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21 18:01:16 +00:00
Angel Pons
a590852313 soc/intel/broadwell/pch/acpi: Fix LPD0 and LPD3 methods
When using references to a FieldUnit, DeRefOf is not used when storing a
value into the referenced FieldUnit, only when reading its value.

Tested on out-of-tree Compal LA-A992P, Linux 5.11.15-arch1-2 no longer
spews errors like these in dmesg:

 ACPI Error: Needed type [Reference], found [Integer] 000000006cbcc5d8 (20201113/exresop-66)
 ACPI Error: AE_AML_OPERAND_TYPE, While resolving operands for [And] (20201113/dswexec-431)
 ACPI Error: Aborting method \_SB.PCI0.LPD0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)
 ACPI Error: Aborting method \_SB.PCI0.I2C0._PS0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)

Change-Id: I60c40452f8b5bdbec76264b578957396de8676ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-04-21 14:22:19 +00:00
Angel Pons
5d13e7fdcd soc/intel/alderlake: Drop unused PrmrrSize from devicetree
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:56 +00:00
Angel Pons
0c0d49229d soc/intel: Replace open-coded buffer length calculation
Use `sizeof(value)` instead of manually calculating the buffer size.

Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:44 +00:00
Angel Pons
73a22edcc8 soc/intel: Fix typo in comment
rotine ---> routine

Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 14:21:26 +00:00
Kyösti Mälkki
84d10cc5d3 ChromeOS: Use CHROMEOS_NVS guard
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).

This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.

Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21 09:27:31 +00:00
Rizwan Qureshi
307be997d1 soc/intel/alderlake: Enable PCIE RTD3 driver
Include the PCIE RTD3 driveri for Alder Lake SoC.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I4732e4663feff503b249b76aaf70ec142a888963
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21 09:20:07 +00:00
Rizwan Qureshi
a979460614 soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21 09:19:58 +00:00
Michael Niewöhner
3c20cba289 soc/intel/common/smbus: lock TCO base address on PCH finalize
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21 09:18:30 +00:00
Angel Pons
b48e6357e8 soc/intel/xeon_sp: Drop unused functions and prototypes
No definition exists for pmc_set_disb() and rtc_failure() is not called.

Change-Id: I3a68e1fc55c62193735a46caf9f70dd9ee0b7349
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21 09:18:09 +00:00
Angel Pons
6a2ece7bd1 soc/intel/xeon_sp: Align pmc.c and pmutil.c with Skylake
Move code that gets used in stages other than ramstage to pmutil.c and
only build pmc.c in ramstage. This is done for consistency with other
platforms.

Change-Id: Iefb4fc86f3995ee6f259b7b287e04f7f94d8d025
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2021-04-21 09:18:00 +00:00
Angel Pons
505e383ccb soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c
Commit 2c26108208 moved this function to
pmutil.c for Tiger Lake. Do this to all other platforms for consistency.
For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed.

With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc
accordingly, and drop ENV_RAMSTAGE guards from Skylake.

Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 09:17:40 +00:00
Angel Pons
f643b63c4d soc/intel/skylake: Move pmc_set_disb() to pmutil.c
To drop bad __SIMPLE_DEVICE__ usage and for consistency with newer
platforms, move pmc_set_disb() to pmutil.c and adapt it accordingly.

Change-Id: I1a137b5b3120c350a04273567b9cb18c9a42a543
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21 09:17:17 +00:00
Angel Pons
e4844ce7c9 soc/intel/skylake: Move acpi_sci_irq() to acpi.c
Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-21 09:17:01 +00:00
John Zhao
3062083d42 soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-21 09:16:08 +00:00
Angel Pons
62719a3797 {sb,soc}/intel: Use get_int_option function
Change-Id: I05f724785880089a513319d70dfd70fc2a6b7679
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21 09:00:18 +00:00
Julius Werner
c893197352 commonlib/region: Turn addrspace_32bit into a more official API
We had the addrspace_32bit rdev in prog_loaders.c for a while to help
represent memory ranges as an rdev, and we've found it useful for a
couple of things that have nothing to do with program loading. This
patch moves the concept straight into commonlib/region.c so it is no
longer anchored in such a weird place, and easier to use in unit tests.
Also expand the concept to the whole address space (there's no real need
to restrict it to 32 bits in 64-bit environments) and introduce an
rdev_chain_mem() helper function to make it a bit easier to use. Replace
some direct uses of struct mem_region_device with this new API where it
seems to make sense.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4c763b77f77d227768556a9528681d771a08dca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-21 02:06:26 +00:00
Felix Singer
b03e497ef1 soc/intel/cannonlake/romstage: Reuse device pointer
Reuse `dev` pointer for SmbusEnable configuration and remove `smbus`
pointer.

Change-Id: I7ad7cdeb632eb52ae02b60ca51e7d4845dffdb0d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20 19:13:09 +00:00
Felix Singer
2a3689f0e4 soc/intel/cannonlake: Deduplicate function declaration
Move the function declaration of parse_devicetree() out of the if-else
preprocessor condition.

Change-Id: I6974554711e4cc2bb944bff14fc057ef6945c888
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-20 19:13:02 +00:00
Felix Singer
0a6cf23ce7 soc/intel/cannonlake: Remove unnecessary function
parse_devicetree() just calls parse_devicetree_param(). To be aligned
with other platforms, remove it and rename parse_devicetree_param() to
parse_devicetree().

Change-Id: I1128ab709cfdb02bbdb505c3f22f5433a30cb3c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52488
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20 19:12:47 +00:00
Angel Pons
8f3e1192df soc/intel/skylake: Move SataTestMode to Kconfig
This option is not mainboard-specific, and should be user-visible.

Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-20 09:19:20 +00:00
Angel Pons
6b89746644 soc/intel/common/block/smm: Drop stale comment
This comment is most likely a copy-paste leftover from Braswell.

Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 14:50:35 +00:00
Angel Pons
0db4b27c7d soc/intel/baytrail/pmutil.c: Define __SIMPLE_DEVICE__
Change-Id: I0d5fa4451b356970cf9843a76d0fa4d2af4307da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:45:15 +00:00
Angel Pons
5595a20f39 soc/intel/braswell/pmutil.c: Define __SIMPLE_DEVICE__
Change-Id: I2caa9cbb812e17f041c15654aef756e41fb71398
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:45:06 +00:00
Angel Pons
6205e03828 soc/intel/common/block/pcr: Define __SIMPLE_DEVICE__
Change-Id: I06f9c623947e48a7213e42507f4da51c12b425d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:44:59 +00:00
Angel Pons
8a10aff35a soc/intel/cannonlake/elog.c: Define __SIMPLE_DEVICE__
Change-Id: Ie2f02b9934d843c29d17a72a6bf3b2bae91ce8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 10:44:53 +00:00
Angel Pons
fc8e997caa soc/intel/braswell/smbus.c: Define __SIMPLE_DEVICE__
Change-Id: Ic16fd74d4ddf96e29bcdada671dab0e590af74ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-04-19 10:44:40 +00:00
Angel Pons
24f4623384 soc/intel/common/block/smbus: Define __SIMPLE_DEVICE__
Change-Id: I93f7918763d87f8fb50f39f9469694e73aeff37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19 06:41:53 +00:00
Arthur Heymans
88407bcd9d cpu/x86/smm: Drop the V1 smmloader
Change-Id: I536a104428ae86e82977f2510b9e76715398b442
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19 06:36:28 +00:00
Furquan Shaikh
e206e2e7ff soc/intel/cnl and mainboards: Drop cnl_configure_pads()
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
done") introduced a workaround in coreboot for `soc/intel/cannonlake`
platforms to save and restore GPIO configuration performed by
mainboard across call to FSP Silicon Init (FSP-S). This workaround was
required because FSP-S was configuring GPIOs differently than
mainboard resulting in boot and runtime issues because of
misconfigured GPIOs.

This issue has since been fixed in FSP (verified with FSP v1263 on
hatch). However, there were still 4 boards in coreboot using
`cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u
and system76/lemp9 were tested to ensure that this workaround is no
longer required.

This change drops the workaround using `cnl_configure_pads()` and
updates all mainboards to use `gpio_configure_pads()` instead.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Tested-by: Angel Pons <th3fanbus@gmail.com>
(Tested purism/librem_cnl)
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
(Tested clevo/cml-u which is similar to system76/lemp9)
Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18 20:41:04 +00:00
Marc Jones
4681b2778b soc/intel/xeon_sp: Set SATA REGLOCKs
Set the SATA and SSATA REGLOCK as indicated by the Intel documentation.

Change-Id: I90e6d0e3b5a38bcd5392e26cbbb6dc4aa6a8304b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:34:24 +00:00
Marc Jones
64c6223759 soc/intel/xeon_sp: Set MSR locks
Set MSR locks as indicated by the Intel documents.
The following MSRs settings are locked:
 MSR_FEATURE_CONFIG AES enable/disable lock
 TURBO_ACTIVATION_RATIO_LOCK

This also adds PARALLEL_MP_AP_WORK to enable running on APs to set
each CPU MSR.

Change-Id: Iacf495f0880d42b378cb0d2c37940d50a511c430
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18 20:32:24 +00:00
Furquan Shaikh
d9ce2859a3 soc/intel/common/gpio: Implement GPIO snapshot/verify callbacks
This change implements `gpio_snapshot()` and `gpio_verify_snapshot()`
callbacks that are useful for debugging any GPIO configuration changes
across FSP-S. These can be utilized by all Intel SoCs that make use of
the common block GPIO driver.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I82a1f125c490b9d6e26e6e9527c2fcd55bb9d429
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-16 17:42:47 +00:00
Marc Jones
4fad28f4c1 soc/intel/xeon_sp: More PCU locks
Add the following locks as recommended by the Intel docs:

DRAM_POWER_INFO_LOCK
PCU_CR3_FLEX_RATIO_LOCK
TURBO_ACTIVATION_RATIO_LOCK
PCU_CR0_PMAX_LOCK

Change-Id: I8d8211977e87109a91790a4070454fc561aa761b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2021-04-16 06:56:13 +00:00
Marc Jones
352ca5b031 soc/intel/xeon_sp: Call SMM finalize
Call the SMM finalize SMI. Adds SMM_FEATURE_CONTROL setting to enable
MCHK on code fetch outside SMRR and the register lock as recommended
by the BWG.

Change-Id: Ie3b58d35c7a62509e39e393514012d1055232d32
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51651
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Rocky Phagura
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16 06:56:05 +00:00
Marc Jones
051bf5d332 soc/intel/common/block/fast_spi: Add flash PRR34 lock
Set the flash PRR3 and PRR4 lock to be set with SPI FLOCKDN.

Change-Id: I288eea3e0e853e5067c5af23e22eab79330c0f20
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51779
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16 06:55:55 +00:00
Maulik V Vaghela
6935350ad6 soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design

BUG=b:184653645
BRANCH=None
TEST=compilation works fine and value of UPD is getting reflected.

Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16 06:44:28 +00:00
Wonkyu Kim
0aeedd42ee src/*acpi: create acpi table for x2apic mode
Create acpi table for x2apic nmi, apic_ids

BUG=None
BRANCH=None
TEST=boot to OS and check apic mode
cat /proc/cpuinfo | grep "apicid"

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I9399d30b686b55d86806f5db4110bf4a80fe459b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-15 10:56:26 +00:00
Julius Werner
62fa9f3cf9 intel: mma: Use new CBFS API
This patch changes the Intel MMA driver to use the new CBFS API.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-04-14 01:03:33 +00:00
Tim Wawrzynczak
7f7c3882a6 dptf: Move platform-specific information to struct dptf_platform_info
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.

Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-13 08:22:49 +00:00
Angel Pons
a67a3227f8 soc/intel/alderlake: Drop unreferenced InternalGfx
This option is not referenced anywhere. Drop it.

Change-Id: Ie59de5399a9b1713109bf334d4ad1d7f7efb91f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52104
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-10 20:21:51 +00:00
Subrata Banik
8cbe43b8d7 soc/intel/alderlake: Skip D3Cold for TBT
Check TBT NVM FW Ready (INFR) bit to skip D3Cold for TBT when device
is in disconnected state.

Not adhering this recommendation is blocking the S0ix state transition.

BUG=b:183670327
TEST=S0ix state transition occurs with TBT disconnected.

Change-Id: Ib9b9ceee4393aeba37fdcb4e05d1b279a6ff72d2
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-10 12:00:33 +00:00
Tim Chu
58e1e0aee9 mb/ocp/deltalake: Override DDR frequency limit via VPD variable
Use VPD variable "fsp_dimm_freq" to select DDR frequency limit.

Tested=On OCP Delta Lake, DDR frequency limit can be changed via VPD.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I1232feae5090420d8fa42596b46f2d4dcaf9d635
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-04-09 06:16:42 +00:00
Michael Niewöhner
fc862dd7d2 soc/intel/dnv_ns: hook up new gpio device operations
This change hooks up the new gpio operations in DNV-NS.

Change-Id: I2179e641153da7230467c5766e4ded58fdb90292
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48618
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08 06:49:55 +00:00
Angel Pons
a3d33795f8 soc/intel/{cannonlake,icelake}: Drop unhooked SendVrMbxCmd
This option's value is not used anywhere. Remove it.

Change-Id: I0f30cddd30d459f48b51f377b111bbc04709c5f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-08 06:47:40 +00:00
Angel Pons
00f53a8d9e soc/intel/skylake: Drop unnecessary ignore_vtd option
It is zero for all mainboards. If one really wanted to ignore VT-d
support, a user-visible Kconfig option would be a better approach.

Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-04-08 06:47:15 +00:00
Angel Pons
3993d38ae6 soc/intel: Hook up SOC_INTEL_DISABLE_IGD to InternalGfx UPD
Commit 0591348833 introduced this Kconfig
option inside soc/intel/common scope. However, it was only hooked up in
commit d74cd60b81 for Alder Lake, and in
commit 99157c1f4a for Tiger Lake. Hook up
the `SOC_INTEL_DISABLE_IGD` Kconfig option to all other platforms which
have the `InternalGfx` UPD.

Change-Id: Icd1379a835b445a6d4b028ebde5a3e355ee5b67b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-08 06:47:02 +00:00
Shaunak Saha
82d5123e1c intel/tigerlake: Add Acoustic features
On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate

We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.

BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06 23:28:17 +00:00
Angel Pons
967753f0d8 soc/intel/common: Prevent SMI storm when setting SPI WPD bit
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMI handler, which results in a deadlock.

Prevent deadlocks by clearing the SPI synchronous SMI status bit in the
SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the
SMI_STS register is continously set until the SPI synchronous SMI status
bit is cleared. To not risk missing any other TCO SMIs, do not clear the
TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit
remains set when returning from SMM, another SMI immediately happens and
clears the TCO_STS bit, handling any pending events.

SPI can also generate asynchronous SMIs when the WPD bit is cleared and
one attempts to write to flash using SPI hardware sequencing. This patch
does not account for SPI asynchronous SMIs, because they are disabled by
default and cannot be enabled once the BIOS Interface Lock-Down bit in
the BIOS_CNTL register has been set, which coreboot already does. These
asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing
the SPI asynchronous SMI source should be done inside the SPI_STS SMI
handler, which is currently not implemented. All of this goes out of the
scope of this patch, and is currently not necessary anyway.

This patch does not handle eSPI because I cannot test it, and knowing if
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).

Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection
is on. Write protection will be enforced in a follow-up.

Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 18:57:30 +00:00
Maulik V Vaghela
afb143dadb soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
Added new LPC and IGD device IDs for Alderlake M.
Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c

TEST=Check if platform information print is coming properly in coreboot

Change-Id: If33c43da8cbd786261b00742e342f0f01622c607
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 07:51:05 +00:00
John Zhao
282e75b118 soc/intel/alderlake: Update variable SD3C to only track enabled devices
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.

BUG=None
TEST=Built Alderlake image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-06 07:04:26 +00:00
John Zhao
9922304b35 soc/intel/alderlake: Remove TCSS DMA _DSM method
The kernel does not need TCSS DMA's _DSM method. This change simply
removes this method.

BUG=None
TEST=Built Alderlake image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I313f9c8913bb8cf54581c5460ac3fb1597291ad5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-06 07:04:18 +00:00
Angel Pons
18571389d5 device/dram/ddr3: Rename DDR3 SPD memory types
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.

Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:37 +00:00
Angel Pons
afb3d7e7ec device/dram/ddr3: Get rid of useless typedefs
These typedefs are not necessary. Remove them, and rename some elements
to avoid any confusion with other DRAM generations, such as DDR4.

Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-05 13:01:29 +00:00
Sugnan Prabhu S
f040f759d9 soc/intel/alderlake: Enable logging of wake sources for S0ix
This change adds elog.c and xhci.c to smm-y for alderlake platforms to
enable the logging of wake sources in eventlog for S0ix.

BUG=b:183684923
TEST=Verified on Brya that entry/exit for S0ix are logged in eventlogs.
295 | 2021-03-29 10:31:48 | S0ix Enter
296 | 2021-03-29 10:31:58 | S0ix Exit
297 | 2021-03-29 10:31:58 | Wake Source | RTC Alarm | 0

298 | 2021-03-29 10:32:30 | S0ix Enter
299 | 2021-03-29 10:32:55 | S0ix Exit
300 | 2021-03-29 10:32:55 | Wake Source | Power Button | 0
301 | 2021-03-29 10:32:55 | EC Event | Power Button

305 | 2021-03-29 10:43:13 | S0ix Enter
306 | 2021-03-29 10:43:14 | S0ix Exit
307 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0
308 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0
309 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8
310 | 2021-03-29 10:43:14 | Wake Source | GPE # | 109

Change-Id: Icc836caa797d3bc4e782c6a51492de23e7b49b71
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51839
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30 15:37:18 +00:00
Arthur Heymans
83a55930dd soc/intel/xeon_sp: Prepare for CBnT BPM generation
To generate a working BPM, boot policy manifest for Intel CBnT the
tool that generates it, requires ACPI base and PCH PWRM base as input.
Therefore make it a Kconfig symbol, that can be used in Makefile.inc.

Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-30 11:46:23 +00:00
Sumeet R Pawnikar
77298c6820 soc/intel/alderlake: add processor power limits control support
Add processor power limits control support to configure values for
alderlake soc based platforms.

BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board

Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 16:08:02 +00:00
Tim Wawrzynczak
a603e443eb soc/intel/common/gpio: Add function to get GPIO index in group
The gpio_get_index_in_group function returns the index of the GPIO
within its own group

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-28 16:05:02 +00:00
Tim Wawrzynczak
5b90c0f158 soc/intel/common/systemagent: Add macros to access REGBAR space
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I97203aca377d4dd77e03b2c83fdd20a2874cc1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:54 +00:00
Tim Wawrzynczak
e2852579b8 soc/intel/tigerlake: Fix REG_BASE_SIZE
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space
in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2
indicates REGBAR is 16MiB in size, therefore update the constant to
reflect this.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-28 16:04:44 +00:00
Tim Wawrzynczak
5de0897671 soc/intel/common/tcss: Rename TCSS_DISPLAY
This name isn't very meaningful, rename the config option to
ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious.

Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:33 +00:00
Tim Wawrzynczak
eb6ebc025e soc/intel/tigerlake: Move TCSS code to intel/common/block
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-28 16:04:23 +00:00
Subrata Banik
2ccc0a4d9f soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.

An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.

Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.

TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)

With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)

Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:23:12 +00:00
Subrata Banik
299ee183c4 soc/intel/common/block/gpio: Fix typecasting issue
This patch fixes unsigned conversion from 'int' to 'uint8_t'
{aka 'const unsigned char'} changes value from '-256' to '0'
[-Werror=overflow].

Change-Id: Ifcc42e5a2ff06f0af0eb96bef4c6044cbcdbd94b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-27 04:22:31 +00:00
Subrata Banik
5558f7ba0f soc/intel/alderlake: Correct GPE DWx assignment as per EDS
List of changes:
1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG
register per GPIO Community.
2. PMC_GPP_* macros are also updated as per GPIO_CFG register
in PMC space.

BUG=b:183464235
TEST=Able to fix the TPM IRQ issue on SM.

Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-27 04:22:11 +00:00
Marc Jones
6efc764c04 soc/intel/xeon_sp: Move PCH PCI device defines
Move the PCH PCI device defines out of the SOC specific PCI defines
and into a common include. The PCH is common and doesn't need
duplicate definitions.

Change-Id: I1ca931e0f01e03c67f8f65ed7fd33c2c1d22183d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 19:14:51 +00:00
Subrata Banik
efe858b170 soc/intel/alderlake: Add provision to override Rcomp settings
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.

Mainboard users can pass required rcomp from memory.c file.

Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.

BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.

Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 04:53:18 +00:00