Mark TSEG as reserved, which is done on other platforms as well.
For some reason CorebootPayloadPkg crashes when using the region where
TSEG typically resides, which is basically RAM.
UefiPayloadPkg doesn't show this issue.
Change-Id: I3ae3659349d2a88bc3575fe9675433c054e28832
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Add Kconfig option to hide the Management Engine Interface device so
the OS doesn't try to access it, if the Management Engine is in an
inoperable mode, e.g. if me_cleaner is used.
- Also hide the MEI if the ME is in Soft Temp Disable mode.
Change-Id: Ie4a35bf5fc196e0a02b7591cdb8633d38f0c7f3e
Signed-off-by: James Ye <jye836@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39074
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes the bootblock and verstage changes for
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early romstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5f805baf42203306ff10e91a258d9117dd986c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:179100924
TEST=Measured the I2C bus frequency as 384 KHz, high time as 924 ns and
low time as 1680 ns.
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I1525ecbf5baf9ae169afd7ce59079f395a2a45a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add support for MP services2 PPIs, which is slight modification
over MP services 1 PPIs. A new API StartupAllCPUs have been added
to allow running a task on BSP and all APs. Also the EFI_PEI_SERVICES
parameter has been removed from all MP PPI APIs.
This implementation also selects the respective MP services PPI version
supported for SoCs
BUG=b:169196864
Change-Id: Id74baf17fb90147d229c78be90268fdc3ec1badc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change drops the config FSP_PEIM_TO_PEIM_INTERFACE.
FSP_PEIM_TO_PEIM_INTERFACE is used for:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
* Adding ppi to subdirs-y
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
and is selected by SoCs that want to enable MP PPI services.
Instead of using the indirect path of selecting MP PPI services, this
change allows SoC to select FSP_USES_MP_SERVICES_PPI directly. The
above uses are handled as follows:
* Auto-selecting FSP_USES_MP_SERVICES_PPI
--> This is handled by SoC selection of FSP_USES_MP_SERVICES_PPI.
* Including src/drivers/intel/fsp2_0/ppi/Kconfig
--> The guard isn't really required. The Kconfig options in this
file don't present user prompts and don't really need to be guarded.
* Adding ppi to subdirs-y
--> Makefile under ppi/ already has conditional inclusion of files
and does not require a top-level conditional.
* Setting USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI to y
--> This is set to y if FSP_USES_MP_SERVICES_PPI is selected by SoC.
TEST=Verified that timeless build for brya, volteer, icelake_rvp,
elkhartlake_crb and waddledee shows no change in generated coreboot.rom
Change-Id: I0664f09d85f5be372d19925d47034c76aeeef2ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50274
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was commented that the need for the delay was mainly related
to external displays and only with VBIOS execution. Move the
delay such that it is done only when we actually need to execute
the VBIOS aka option rom.
A delay is currently only defined for librem/purism_bdw in
its Kconfig. As the description of the issue sounds like it
would equally happen on other platforms when VBIOS is involved,
promote the Kconfig visible option to global scope.
Change-Id: I4503158576f35057373f003586bbf76af4d59b3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.
They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.
It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.
Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The offsets of ACPI_CPU_CONTROL and ACPI_GPE0_BLK match the ones from
the reference code, but not the PPR. I've submitted a change request for
the PPR, so this mismatch might go away in the future. The case for
HAVE_SMI_HANDLER will be implemented in a future patch. If that one ends
up being identical to the function in soc/amd/picasso, I'll move it to
the common AMD SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If80b841df12d351d5a0c1e0d2e7bf1e31b03447f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Make it clearer all the GPIO bank register programming
parameters originate from the same soc_amd_gpio entry.
Change-Id: I7aa6bd6996fd14dde4b1abcccbd2ae6ef933c87b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42691
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do this to reduce indentation a bit. Also it may be desireable
to group GPIO configuration such that some GPIOs are handled
outside program_gpios() call and would not be included in
gpio_list array.
Change-Id: I46cbe33f4d85cd9c7d70f96df82ee9b8ffe50a00
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42807
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8192 MCUs, replace LZMA compression with LZ4 to speed up boot
process. The loading (plus decompression) time of mcupm.bin and sspm.bin
is consistently reduced by 8ms, respectively.
BUG=b:177389446
TEST=emerge-asurada coreboot
TEST=Hayato booted up
BRANCH=none
Change-Id: Ida35e7f6e0572ad43082e53bcc69bc708cf7da44
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
First and last printk() log the same string.
Add done at end of function.
BUG = N/A
TEST = Build and boot faceboot FBG1701
Change-Id: I66a64c7473a65206c3a4c4396c8c8ecba1eb1a57
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Revise the following aspects to follow coreboot's coding style:
- Drop braces for single-statement condition and loop bodies.
- Use `__func__` to print the current function's name.
- Reflow pointer dereferences to fit in a single line.
- Adjust the `*` position in pointer variable declarations.
- Drop unnecessary `else` statements.
BUG = N/A
TEST = Build Compulab Intense-PC with secure oprom enabled
Change-Id: I780251d946d5bea97658476d61d25555ec768dfc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Now smbios type 4 max speed field will use the maximum speed of
processor itself if CPUID value can be accessed. However, this field
should be the maximum processor speed supported by the system. Here
we use smbios_cpu_get_max_speed_mhz only to get correct value.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Iae8e01a5e455709a57d60a840f279685c8aab80f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48636
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI support for battery, AC and lid.
I don't have MacBook Air 4,2 to test, but:
- I tested it on 5,2;
- I found decompiled DSDT for 4,2 and compared registers and bits,
they are the same as on 5,2.
So it should work.
Change-Id: I592cb4501c878fe46684a524e729d32fb1d7920c
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Refactor PCIE port config structure. Make it easier to map from
schematic. We don't have to convert the PCIE ports RP number and
CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This is what Lynxpoint does. It is equivalent, but simpler.
Change-Id: Ifdbb291a6cea0bb29b4e46c7a33c5abe61dbe86b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47045
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Move ACPI code for Apple MacBooks to a separate directory to avoid
its duplication in mainboards
- Add AC and lid implementations for newer generations
- Rewrite old code using the new ASL syntax
Tested on MBA 5,2, MBP 8,1 and MBP 10,1.
Change-Id: I3d4585aac8e3ebbfed6ce4d4e39fbc33ac983069
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the kracko variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:178092096
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_KRACKO
Change-Id: I7f8c7a4d4967e99896166ec9dd6b7381b7f6e5ed
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable this driver along with power saving.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a driver which puts the device into power-saving mode.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Idc1340b1a6fe7063d16c8ea16488d6e2b8b308cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This allows to compile FSP related tools (like the FSP loader) in
x86_64 mode, but it doesn't add support for properly running x86_32
FSP on x86_64. This is handled in a separate patch.
Change-Id: I0e3099fae1b70bfe9ec0abbdddb4231ab5e2f388
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This partially reverts:
- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e
It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.
Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Crash Data are collected and sent to the OS via the ACPI BERT.
BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. Add pl4 value
2. Change policies passive with sensor 0 and 1
3. Change granularity value with pl1 and pl2
BUG=b:178768749
TEST=make buildall
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:
- DeepSx
- USB power in S5
- Power state after G3
Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Hermes has an EEPROM with firmware configuration data. Add definitions
to read and verify the `board settings` from the EEPROM. Subsequent
commits will hook up these EEPROM settings.
Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The latest initial code is from BOE, the vendor.
BUG=b:179206650
BRANCH=kukui
TEST=Run long time aging test and the BOE LCD shows normally.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `_MASK` macros should be using the corresponding `_SHIFT` macros.
Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.
BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix booting with SMP enabled, when specifying more CPUs than supported
by the code.
Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a
new dependency within the file MemInfoHob.h. Adding required macros to
resolve the dependency.
BUG=b:178846328
Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.
Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.
Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot proper now has a single include for this file
with the guard around it already.
Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.
Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In the case of passing 32 as limit the code returned -1, but should have
continued, since 32 is a valid value here.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
USB2 ports assigned to type-C connector need to be configured properly
by the USB2_PORT_TYPE_C. and also modify the description of USB port.
BUG=b:177480902
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the typeC port function is normal by manual.
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level
Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add ACPI entries for AT24 NVM device.
BUG=b:169551066
TEST=Build and run for basic camera functions.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Define the 25th bit of the fw_config for the regular touchpad
and numpad touchpad selection.
BUG=b:174027837
BRANCH=firmware-volteer-13672.B
TEST=build pass
Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This fixes the fan always running at full speed on ProBook 6360b,
EliteBook 8470p and ProBook 640 G1 (because the fan control command was
not sent).
On the ProBook 6360b, the EC needs about 30 ms to process the first
command on a cold boot, but other models such as the ProBook 640 G1 need
more time.
Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.
BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
build Pass
And check the system can power off normally in recovery page
Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because ACM already does TPM initialization.
Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Use probe_resource instead of find_resource. This prevents
a call to die and instead returns NULL.
* Handle the case where BAR2 isn't present
* Don't hardcode legacy VGA when BAR2 is present. This fixes
graphic initialisation when the Aspeed isn't the primary GPU
and thus doesn't decode VGA cycles.
This makes the coreboot code more similar to the Linux kernel code.
Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 3f2467032e changed this in the APCI
code itself, but the change in the ACPI byte code generation in
pcie_gpp.c was missed and this patch fixes that.
TEST=Fixes the regression on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60de29581296101947336f70343d6206af97e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Iac8a6e386b708ae5c4dbf0677bfe05f1358bf8fd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49442
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Ife6611a11e5627d39d59e0e93af9aa2d87885601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50121
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Baytrail had (only) occurence of DwordMemory vs DWordMemory.
Braswell one had bogus comments about the PCI memory range.
The actual region details are dynamically filled in _CRS.
Change-Id: I8d1bf45c6e5520c0b7643602843c665bfb81f9da
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's assumed in ASL already that the banks appear one
after other in ACPIMMIO space. There is no need for
the separation of accessor functions by name.
Change-Id: I4c8c3f2028ca89dca5c7f0548fcd18e1045999d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
From the output of 'objdump -x dram.elf', the DRAM blob needs 222K
memory, but currently only 208K is reserved for it. Since MT8192 has 1MB
SRAM L2C, increase SRAM_L2C_END to 0x00300000, and reorganize regions in
SRAM_L2C to have larger DRAM_INIT_CODE (256K). The size of
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE is also increased to 252K.
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Asurada booted successfully
BRANCH=none
Cq-Depend: chrome-internal:3568265
Change-Id: I062f00739b72cf6b1bb7ac3318b91721fbe226cc
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
It is the same for all three mainboards.
Change-Id: Ic5786bcc29e2549d6fc935d60c699c1cab84b237
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50027
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).
ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).
Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the missing `GBB_FLAG_ENABLE_UDC` as a config in
vboot/Kconfig (just like the other GBB flags) and uses its value to
configure GBB_FLAGS Makefile variable. This is done to allow the
mainboard to configure GBB flags by selecting appropriate configs in
Kconfig.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b397713d643cf9461294e6928596dc847ace6bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50110
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BH720 PCR registers are accessed using an index/data register pair.
Introduce some helper functions to clarify the PCR register operations.
Change-Id: I1a48b10071af20dca61b7dd90c5a70bc9d1089b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable Acoustic noise mitigation for magolor and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:178678267
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: Idea2a801399bb5c7e0b8e59ee7a826c86a44f4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50099
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UPD PlatformDebugConsent field is not configured.
The config SOC_INTEL_ELKHARTLAKE_DEBUG_CONSENT is available but not
used. Use this config value for PlatformDebugConsent.
BUG= N/A
TEST= Build Intel Elkhart Lake
Change-Id: I697fb611dfb23e107fa8ef1543424b9797a7d027
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50108
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add device ID of Cannon Lake PCH-H Mobile HALO SATA controller
in supported device table.
Bug=N/A
TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully
completed
Change-Id: Ie1c2aa8273a53c47d7b3571394bcd85b59ab1142
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Add SATA controller ID for Cannon Lake PCH-H Mobile HALO
(see document number: 571182)
Add SPDX license header
Bug=N/A
TEST=Build of Intel Coffeelake H SO-DIMM DDR4 RVP11 successfully
completed
Change-Id: Ic7e6ace2a24b4278b04caa58be907d38f4d117cd
Signed-off-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If for a stage __CONSOLE_ENABLE__ is 0, then there would be no
prototype for a get_console_loglevel() definition.
Change-Id: I805078921a5cc1506685f8aada3af5c5241260b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50083
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is useful to know if MCU have been applied successfully.
On the start of MP init lines similar to:
"AP: slot 1 apic_id 1, MCU rev: 0x0700001d" will be printed.
The example is taken from the log of an ocp/deltalake.
Change-Id: Ia0a6428b41d07f87943f3aa7736b8cb457fdd15a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49840
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For SMBIOS type 3, add function to override number of power cords
Tested=Exectute dmidecode -t 3 to verify.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I7dee3a944a49ffcfdc2f4408d92a17aa39761bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Initiate peripheral buses based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ibf48aceca7ac8774b0353e31bd81e1880c4066ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change moves the selection of SOC_INTEL_CSE_LITE_SKU into Kconfig
under BOARD_GOOGLE_BASEBOARD_VOLTEER instead of requiring each
individual board to select it.
TEST=Verified that timeless build does not result in any changes.
Change-Id: I2d94931fdc3077794bed5cc51708b5a5d9e64972
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This variant never really got used and can be deprecated.
Change-Id: I5d59460c90266ba5f9c3bdb951f53a37ffae9e03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A new schematic revision indicates that the old wake pin is not used,
and brya will only use 1 IRQ pin from EC, routed to GPP_F17
BUG=b:178605367
TEST=Build test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia2bc5b1562ab30b4461fc7e3b1a4bc3e370db588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit f41645c34d.
In Dragonair, during the MP stage, one of the resistors needed
for this functionality has been removed. This results in the
privacy-switch not readable back by the system.
BUG=b:178458332
Change-Id: I0781f338d5ecd89fccee613fb13ea25c59385625
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1. These are common OCP/Facebook IPMI OEM commands, move from mainboard
into drivers/ipmi/ocp to avoid code duplication and provide better
reusability.
2. OCP Tioga Pass enables IPMI_OCP driver.
Tested=On OCP Delta Lake and Tioga Pass verify the commands still work
correctly.
Change-Id: Idd116a89239273fd5cc7b06c7768146085a3ed69
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Bus Master is not required and reference code does not set it.
Change-Id: I2f70486f96cf3dcaba74283293b93b9747cd0300
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.
Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
