a335402bec
serialize cpus for >2
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-03 20:54:43 +00:00
e089f00ad4
optimize read link bug fixed.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-03 20:00:36 +00:00
bf0ed60514
Dynamic RT with 4 ways test OK.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-03 19:54:47 +00:00
85e76c6af6
now rom_address is one of the resources
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27 17:53:45 +00:00
e7c26a70ec
remove unused options
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27 17:52:54 +00:00
af0cc3e1c4
start consolidate various borken vga support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27 17:52:05 +00:00
e8b1c9dbd1
clean up VGA and Expansion ROM support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-27 04:25:41 +00:00
5b772cca55
default link bug fix
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-24 04:42:59 +00:00
9a5b4962a7
Allocating resource for Expansion ROM
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More correct resource allocation for legacy VGA on K8
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-23 21:48:01 +00:00
a804a713a2
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-22 19:02:41 +00:00
e2b2006406
update broastcast table for K8 4p above
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-22 03:14:50 +00:00
6a5d99bde4
8 ways support changes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-22 00:58:50 +00:00
1de80941c2
amd k8 routing table creation dynamically support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-21 22:14:12 +00:00
2c956bbc19
non coherent ht chain setup automatically
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-17 21:08:16 +00:00
970990800e
btext fix
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-16 02:44:25 +00:00
42b37443ac
shame on me.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-15 16:09:06 +00:00
b14e851110
obviously broken
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-15 16:08:18 +00:00
140a3a11ad
add dump_pci_devices_in_bus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-14 01:56:55 +00:00
ec01aa98d0
- Fix the definition of the linuxbios table so all of the compilers
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will generate the struct lb_memory_range the same.
- Add a few pci_ids.
- Small readabiltiy clean ups to debug_dev
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-10 20:50:43 +00:00
6ac60f8dfe
get config tool satisfied.. let's see if we get this working..
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-09 00:37:03 +00:00
3a81285409
allocating resource for legacy VGA frame buffer, it is not 100%
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correct but it works anyway.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-03 22:39:34 +00:00
845e8df673
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-03 19:07:45 +00:00
7213d0f513
i2c mux support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-03 03:39:04 +00:00
57b6786168
Updates to raminit.c correcting for new version of smbus_read_byte.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-01 16:59:05 +00:00
e1bc97b078
Updated version of vt8231_early_smbus.c
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smbus_read_byte routine updated as per suggestion by rgm
addition reset & wait_until_ready to allow correct reading of first
byte on epia systems.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-12-01 16:57:37 +00:00
284c27f299
fixes to make adl855pc compile.
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fixes to emulator.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-28 04:39:45 +00:00
637b699865
new config file format - PMC no longer works
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 01:11:31 +00:00
5720da9d75
moved from ../sandpointx3_altimus_mpc7410
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 01:11:03 +00:00
31f6606aea
not used here
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 01:09:49 +00:00
08d2d5a5c2
PMC no longer works
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 01:08:16 +00:00
d12eca7273
../sandpoint contains X3 configuration
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 01:07:47 +00:00
92555b939d
make sure enable_resource called on children
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-26 00:46:39 +00:00
0493069aa9
update comment according to the new DOM
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-25 17:37:19 +00:00
f0ee1efcaf
marked debug device on LPC bus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-25 17:35:37 +00:00
d62a09c791
move pnp code
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:15:49 +00:00
d47d05bd0a
pci devices are all on the same bus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:14:06 +00:00
fb746a3fea
removed argument
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1794 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:13:03 +00:00
0bac237334
added comments
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:12:20 +00:00
f439250355
fixup debugging info
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:11:04 +00:00
c906c2918a
scan the static bus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-24 21:09:08 +00:00
e5c0ca30a2
pci_read using wrong device
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-22 21:36:46 +00:00
5697edee03
- Add the new files for the motorola mpc107
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18 22:39:43 +00:00
a9e632c2ac
- First stab at getting the ppc ports building and working.
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- The sandpointx3+altimus has been consolidated into one directory for now.
- Added support for having different versions of the pci access functions
on a per bus basis if needed.
Hopefully I have not broken something inadvertently.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-18 22:38:08 +00:00
bec8acedf1
- Comment on why optimize_link_read_pointers is safe on an Athlon64
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-15 17:01:05 +00:00
cb364958a0
- Don't force spew level debug messages on the kherpi
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- optimize_link_read_pointers compiles now on the solo so don't disable it.
- Start sorting out the confusion between and object and an initobject on the ppc ports
- Major bugfix release of romcc to support to remove preprocessor deficiencies.
The line and column numbers are computed are now correct. But watch out
the error messages sometimes report the location of the next token so things
are still a little skewed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1784 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-15 10:46:44 +00:00
f6f349828f
- Allow coherent_ht.c to compile uniprocessor
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-13 03:47:52 +00:00
3e9b52d554
ooops. sorry
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1782 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-12 21:00:29 +00:00
204f718fa3
fix a little more of ppc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 21:30:50 +00:00
8d41ad83be
in loglevel.h, if ASM_CONSOLE_LOGLEVEL is defined, don't try to set it.
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Set adl855pc ROM_SIZE to 1M
Other minor debug prints until we get this fixed.
We're almost as far along as we were before the Change :-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1780 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 14:04:25 +00:00
029517c77a
- Refactor the pc keyboard code so it will timeout if the hardware
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is not working instead of haning forever.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1779 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 11:56:00 +00:00
69afe2822a
mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a complex expression.
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crt0.S.lb: Modified so that it is safe to include console.inc
console.c: Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h: Only include limits.h if ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c: Remove work around for older versions of romcc
pci_ids.h: More ids.
malloc.c: We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
- Talk about nodes not cpus (In preparation for dual cores)
- Remove clear_temp_row (as it is no longer needed)
- Demoted the failure messages to spew.
- Modified to gracefully handle failure (It should work now if cpus are removed)
- Handle the non-SMP case in verify_mp_capabilities
- Add clear_dead_routes which replaces clear_temp_row and does more
- Reorganize setup_coherent_ht_domain to cleanly handle failure.
- incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop. It's more maintainable.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 06:53:24 +00:00
8d54bd4471
- Remove include of device/chip.h
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 03:31:16 +00:00
624252450f
- Delete unused funciton realloc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 20:13:35 +00:00
26e32760f9
- Remove unused start_stop.h
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This file died with the last round of cpu restructuring I just missed it earlier.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 20:11:15 +00:00
8bcb8a2ada
- Don't use e7501 root_complex
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1774 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 18:32:20 +00:00
ab49946a56
- Remove e7501 root_complex
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 18:31:31 +00:00
52c2277a1b
adl855pc support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 15:12:48 +00:00
12eb7bc5ad
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1768 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-08 21:16:16 +00:00
ad00d73998
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1765 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 22:14:33 +00:00
44b34e31a5
CONFIG_CHIP_NAME to control config chip.h without .name
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 22:03:37 +00:00
7a9c836f93
- How did I forget to cvs add this?
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1763 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 19:55:46 +00:00
692f2c7aed
- First pass at getting the powerpc ports to compile
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The static device tree is not built properly at all yet, but at least we get through it.
FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 19:55:06 +00:00
cd51e6ad90
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 18:09:46 +00:00
709850a21b
- Ensure every copy of Options.lb uses:
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CROSS_COMPILE
CC
HOSTCC
OBJCOPY
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 10:48:04 +00:00
41d0fa38af
- Modify all of the Opteron motherboards to have a separate logical
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chip for the amdk8/root_complex
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 07:26:56 +00:00
8bd555297e
- Add a new chip northbridge/amd/amdk8/root_complex
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- Moving the functionality around in northbridge/amd/amdk8/northbridge.c
to put the pci_domain and the apic bus on the root_complex.
Everything else remains with the individual northbridges.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 07:04:54 +00:00
7bf1b48bd4
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-05 03:44:01 +00:00
9562049df5
reformat
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 23:42:54 +00:00
b2d77282e0
debug device added
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 22:36:18 +00:00
652ae6f533
we decide not to enable BM DAM form them
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 21:48:39 +00:00
8085f032f8
SI Class code check
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 21:00:13 +00:00
2d2bdd3846
removed #if 0 #endif code
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 20:31:04 +00:00
f84926efca
tell people that the segment descriptors are different for ROMCC and
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GCC code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 18:36:06 +00:00
1995f1af35
removed the comment in the very beginning of hardwaremain(). I don't
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think it is relevant now.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 18:33:33 +00:00
23bc47db17
Add Options.lb to various motherboard ports
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1738 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:09:12 +00:00
018d8dd60f
- Update abuild.sh so it will rebuild successfull builds
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- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:04:33 +00:00
4403f60823
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03 00:47:40 +00:00
e507c85fe3
This hurts more than it helps. byebye
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-03 00:10:15 +00:00
e4932dc760
get qemu-i386 target building again
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 20:33:12 +00:00
bf8bb42d6a
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 18:05:22 +00:00
3974363f09
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 17:46:43 +00:00
9434c1b661
Tyan update for ROM_IMAGE_SIZE > 64K
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 02:34:28 +00:00
0979969732
fix solo
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-31 23:03:10 +00:00
432aa6a255
- Update console.c to have non-inline versions of functions
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- Add exception.c
Sorry for not including these ealier.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30 22:59:35 +00:00
f8a2dddb57
- To reduce confuse rename the parts of linuxbios bios that run from
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ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30 08:05:41 +00:00
0afcba7a3d
Changes to allow Via/Epia code to be compiled after recent code changes.
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New Files :-
src/cpu/via/model_centaur/Config.lb
src/cpu/via/model_centaur/model_centaur_init.c
Updated Files :-
src/arch/i386/include/arch/smp/mpspec.h
- make write_smp_table a define for non smp systems
src/cpu/x86/lapic/lapic_cpu_init.c
- change possible typo
src/mainboard/via/epia/Config.lb
src/mainboard/via/epia/Options.lb
src/mainboard/via/epia/auto.c
src/mainboard/via/epia/chip.h
src/mainboard/via/epia/failover.c
- updated after recent code changes
src/northbridge/via/vt8601/chip.h
src/northbridge/via/vt8601/northbridge.c
src/northbridge/via/vt8601/raminit.c
- corrections after recent code changes to allow compiling
src/southbridge/via/vt8231/chip.h
src/southbridge/via/vt8231/vt8231.c
- initial pass to allow compiling after recent code changes.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-29 16:16:43 +00:00
97035448f3
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1725 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-28 18:44:38 +00:00
79186eaecd
- Look for all 8 possible cpus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 18:54:13 +00:00
a58cd524fb
some more porting to the merge
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1723 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 17:27:10 +00:00
6e53f50082
sizeram removal/conversion.
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- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 08:53:57 +00:00
20fc678d65
spare 4s for restart
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 02:12:22 +00:00
63f2f721b4
- kill the broken and duplicate 855pm directory. Hopefully I have kept
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the least broken one.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:58:26 +00:00
dfde9bb649
- Actually enable the Pentium-M cpus
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:47 +00:00
3566b3d545
- Bug fixes to the P-III support
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- Initial Pentium-M support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:16 +00:00
eefdb03898
S2885 winbond Superio all resource set
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 00:37:30 +00:00
fb198640d8
ops and tsc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 19:55:30 +00:00
9cf950ca5a
s2735 minor changes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 19:49:50 +00:00
3f637906c4
added file
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 16:01:30 +00:00
7ae74b40bf
from Mark Wilkinson, some fixes.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 14:57:24 +00:00
8e2847c28e
- For now use port 0x80 based delays in for the e7501 memory initialization.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 03:00:02 +00:00
60216355d2
- With Xeon cpus it seems best to use the tsc calibrated with timer2 as
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the time source. The apic timer also has a variable time base.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 02:47:13 +00:00
720a8f57ef
- Update e7501 northbridge.c to work in the new structure.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 02:32:23 +00:00
8abb054c0e
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1709 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 00:05:22 +00:00
2560dbdd50
for S2735 support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:33:08 +00:00
e99433157b
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:03:26 +00:00
79cf1be9e4
*** empty log message ***
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 18:49:09 +00:00
ccf0bc01aa
s2735 half update
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 18:45:36 +00:00
a1653cfea5
- Better memory I/O space distinguishing in amd_mtrr.c
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This is way to much code duplication but for now things work.
- Fix the typo in amd8111_lpc.c
- Remove an unused macro, use continue instead of break in mtrr.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 04:41:53 +00:00
4f9265fdc6
- kill typo so resources are not mixed up in amdk8/northbridge.c
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- Enable resources on the lpc bus. PCI now longer do this by
default for their children unless they are bridges.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 02:33:51 +00:00
584e078231
adapt config files
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 20:52:53 +00:00
800a55bb5c
get solo building after last infrastructure changes
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 18:51:13 +00:00
a49f4161f5
update failover handling of some amd64 boards
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 17:06:49 +00:00
dbec2d4090
- Bump the LinuxBIOS major version
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- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 10:44:08 +00:00
f3aa4707d3
- Explicitly disable the fixed dram extensions bits.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 02:53:25 +00:00
29490a17ce
- We already know the cache is disabled so don't bother disabling it.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 02:43:15 +00:00
f19e2c766a
better support enable_dev for amd8111
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1695 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 01:52:21 +00:00
6014983bab
add Option.lb
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20 17:54:01 +00:00
6a61d6a4ae
Tyan update to work with new CPU Config
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-20 05:07:16 +00:00
abed01d81d
- Fix typo with reversing memory resources.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1692 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 23:35:53 +00:00
812688bf3c
change struct chip* to struct device*
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1691 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 17:49:32 +00:00
de24e61df7
- add support for socket 754
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- fix configuration creation for amd solo (doesn't compile yet)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1690 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 10:30:32 +00:00
a172d98233
- Fix bug with > 4GB of memory where PAE was left enabled.
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Why didn't this show up until I had > 4GB on one cpu?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-19 05:07:18 +00:00
04da1d35d1
- Bump MAX_LINKS to 4 I have actually found an i2c bridge that needs this
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- Fix the hdama Config.lb to not longer use the link keywords oops,
and instead to have it nest everything properly.
- Update config.g to not support the link keyword
- update config.g to not support northbridge/southbridge/cpu/pmc noise words
we can just use chip now.
- Remove old link handling from the code
- Detect and handle duplicate paths so we generate one device with multiple links
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 19:58:35 +00:00
858ac5c5cd
- Make all ports use config.h for if they have chip_config or chip_info structures.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 09:13:23 +00:00
92986807bb
- Cleanup the bugfix in elfboot.c
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- Add forgotten amd8111 chip.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1683 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 08:45:29 +00:00
f3ed1cfad7
- HDAMA boots!
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- Set the bootstrap processor flag in the mptable.
- Implement 64bit support in our print statements
- Fix the reporting of how many cpus we are waiting to stop.
It is the 1 less than the actual number of cpus running.
- Actually enable cpu_initialization.
- Fix firstsiblingdevice in config.g
- Add IORESOURCE_FIXED to all of the resources set by config.g
- Fix the apic_cluster rule to add an apic_cluster path not an apic path.
- Add a div64.h to assist in the 64bit printf.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 08:38:58 +00:00
7003ba4a88
- First stab at running linuxbios without the old static device tree.
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Things are close but not quite there yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 06:20:29 +00:00
216525d1fd
- Fix config.g and the hdama config so everthing builds again.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 02:48:37 +00:00
e2ad5ce697
fixed function prototype for die()
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 23:05:08 +00:00
3287f0b9a1
- Change broken usage of get_resource to find_resource.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1674 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 23:02:00 +00:00
448bd635c0
- Finish interrupted merge
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:52:15 +00:00
e5ac2959bb
oops.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1672 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:44:26 +00:00
119e00e2e1
- Fix fat fingered merge
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:35:23 +00:00
3614eebc13
- Update so we no longer require console.inc
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:29:26 +00:00
1944680bfd
- Sync up northbridge/amd/amdk8
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 22:06:29 +00:00
297b06e6f9
- Update the header files in reset_test.c
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:55:53 +00:00
73f2282ea1
- Add a generic device that does nothing
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:43:24 +00:00
4b93394872
more breakage, thanks to Ron
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:40:58 +00:00
03acab694b
- Updates for 64bit resource support, handling missing devices and cpus in the config file
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1664 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:25:53 +00:00
992cd008f1
- Update the device header files
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 21:10:23 +00:00
b78c1972fe
- First pass through with with device tree enhancement merge. Most of the mechanisms should
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be in place but don't expect anything to quite work yet.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1662 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:54:17 +00:00
cadfd4c462
- Add arch/cpu.h
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:52:22 +00:00
65186ce66c
- remove old cpu header files
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- Update cpu.h for the new cpu initialization scheme
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:15:40 +00:00
c84c1906b7
- Renamed cpu header files
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 20:13:01 +00:00
b84166e8e5
- remove deprecated directories
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:39:27 +00:00
fcd5ace00b
- Add new cvs code to cvs
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:29:29 +00:00
02fa3b2743
epia-m support
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06 17:33:54 +00:00
4fa89208a1
f'ing thing still won't work.
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-06 17:19:49 +00:00
ed9f18d545
mods for i855pm that don't seem too wrong. ha!
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30 22:50:13 +00:00
a4779e80c3
digital logic stuff, fixes for the smbus code in 82801dbm
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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-09-30 16:37:22 +00:00
Yinghai Lu