Not all platforms need to generate power resources, but the code does
not get optimized out at build time because the devicetree gets
compiled into a linked list. As this code pulls in some heavy ACPI
dependencies that is even implemented with weak empty function it
makes sense to optimize out this code using a Kconfig constant.
This saves 1.5K in ramstage size on gigabyte/ga-945gcm-s2l.
Change-Id: I82289aa7e6e82318417f3b827b86182891dfc2a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58657
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the AMD SDLE stardust test fails with incorrect VDD/SOC
scale/offset value, it needs to update the two load line slope
settings for the telemetry.
AGESA sends these values to the SMU, which accepts them as units of
current. Proper calibration is determined by the AMD SDLE tool and the
Stardust test.
VDD scale: 92165 -> 73457
VDD offset: 412 -> 291
SOC scale: 30233 -> 30761
SOC offset: 457 -> 834
BUG=b:200194315
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: If53c173000a276a80247ccb08736280a25948939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
EN_PWR_FP is used to enable power to the FPMCU. This frees up GPIO_32
for other uses.
This move applies to all board except:
* Guybrush
* Nipperkin board version 1
Add callbacks for variants to override fpmcu shtudown gpio table and
fpmcu disable gpio table.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure fingerprint
still works.
Change-Id: I4501554da0fab0cb35684735e7d1da6f20e255eb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GSC_SOC_INT_L gpio is used by Google Security Chip (GSC) to interrupt
SoC when the SoC is in S0 state. Hence use GPIO_85 which is in S0 domain
and save the GPIO_3 in S5 domain for other use-cases. This move applies
to all board except:
* Guybrush
* Nipperkin board version 1
Update the GPIO configuration, device tree configuration accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush and Nipperkin. Ensure that the SoC
<-> TPM communication is working fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I019f10f2f457ab81bcff77ce8ca609b2b40cb2ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIO overrides are defined for verstage. But the overrides are neither
enabled nor applied during verstage. Enable the overrides and apply them
during verstage.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/stress, warm and
cold reboot cycling for 10 iterations each. Ensure that all the PCIe
devices are enumerated fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I510313bf860d8d55ec3b04a9cfdfa942373163f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:200918380
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I83cc1a5d80bf23d052e83c9791ef866966a3d9b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58626
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015941
TEST=run part_id_gen to generate SPD id
Change-Id: I78ec575d354a5ae7c014a6050364d0a5214e4e92
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. H54G46CYRBX267
BUG=b:204023388
BRANCH=firmware-keeby-14119.B
TEST=FW_NAME=driblee emerge-keeby coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I1b40e24faf8d85f32839a3d44fd936ca7ee7e09f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
In-band controls work to enable/disable the WWAN module. Hence
WWAN_DISABLE_GPIO is not critical and can be marked as not connected.
BUG=b:188415287
TEST=Build and boot to OS in Guybrush. Ensure that the WWAN module is
enumerated on boot and reboot.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7fefba3de9c749971911b21ed4712e950cef5a6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
On all upcoming variants and board versions of existing variants,
SD_AUX_RESET_L signal moves from GPIO_69 to GPIO_5. This means all
boards except:
* All board versions of Guybrush
* Nipperkin Board Version 1.
Also in Nipperkin, LCD_PRIVACY_PCH signal moves from GPIO_5 to GPIO_18.
Configure the gpios accordingly in baseboard, guybrush and nipperkin
variants accordingly. Also update the DXIO port descriptor for SD PCIe
engine with the corresponding AUX reset GPIO.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush & Nipperkin. Ensure that the SD
Controller and SD Card are enumerated fine. Ensure that the enumeration
is successful after a suspend/resume cycle.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If28810747e6b4eaae2a693a98e1adc830f80bcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The baseboard enables PCIe RPs 6, 8 and 9, but kano doesn't use
these. Having them enabled will occasionally cause suspend
attempts to fail, therefore disable them in the overridetree.
BUG=b:203389490 b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie2b82cff6d910c961eeb56704dcbae2bdc2a8c53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On
Nipperkin board version 1, pen is not stuffed and instead the GPIO is
used to control LCD Privacy settings. On upcoming Nipperkin board
versions and other variants, GPIO_5 is not used. Configure GPIO_5
accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Guybrush. Ensure that the configuration is
retained on existing boards.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The `SMBIOS_PROVIDED_BY_MOBO` Kconfig option is already selected through
the `SECUNET_DMI` option. So, there's no need to select both of them.
Change-Id: I784df87893043a011906af8808aff27d636c7626
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58625
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I43df98d84c6a274d6f96c8818ce6acff9337d8d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Micron MT53E512M32D1NP-046 WT:B
Hynix H54G46CYRBX267
Samsung K4U6E3S4AB-MGCL
BUG=b:204015944
TEST=run part_id_gen to generate SPD id
Change-Id: Icf2f7352a4bd6a58e3e7abdcaac823b863984732
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).
BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia3813306f8c7b69fe5cf0e188c55256b68d329ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch set disables the external voltage rails since kano
board doesn't have V1p05 and Vnn bypass rails implemented.
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia1f3f4b2ada0154c716aedd521d4151124411ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: Ife48aafcec43555175aad44f8b6307beeaea9184
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58592
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to have an overridetree with a single board variant.
TEST=Compare static.c and observe only device order has changed.
Change-Id: I2097e247c27d5d0c5479cb533b477cd490a4c827
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
turn off WLAN ASPM L1.1/L1.2 as a short-term w/a for WLAN AP probe failure.
BUG=b:198258604
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
AP is able to be probed by wlan module
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ic7be523626b0ff6e4b1c66ba6af13b15061ef4cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.
Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
For SMP operation IOAPIC needs to be configured.
For a build with MAX_CPUS=1 emulation might still decode
the IOAPIC MMIO window, it does not really matter to have
it always reserved.
Change-Id: Ia340fc418cd9ceda56a2a10972e130d9f289c589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Each CPU/SoC checks the return value of the mp_init_with_smm and prints
the same error message if it wasn't successful, so move this check and
printk to mp_init_with_smm. For this the original mp_init_with_smm
function gets renamed to do_mp_init_with_smm and a new mp_init_with_smm
function is created which then calls do_mp_init_with_smm, prints the
error if it didn't return CB_SUCCESS and passes the return value of
do_mp_init_with_smm to its caller.
Since no CPU/SoC code handles a mp_init_with_smm failure apart from
printing a message, also add a comment at the mp_init_with_smm call
sites that the code might want to handle a failure.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I181602723c204f3e43eb43302921adf7a88c81ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using cb_err as return type clarifies the meaning of the different
return values. This patch also adds the types.h include that provides
the definition of the cb_err enum and checks the return value of
mp_init_with_smm against the enum values instead of either checking if
it's non-zero or less than zero to handle the error case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibcd4a9a63cc87fe176ba885ced0f00832587d492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Correct GPIO GPP_R6 and GPP_R7 setting to NF2 (DMIC_CLK1 and DMIC_DATA1).
BUG=b:202913826
TEST=FW_NAME=kano emerge-brya coreboot and verify it builds
without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ibf8ff0e48c4bab435d082dee27bcd53bc85b088d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:197385770
TEST=emerge-brask coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia7e5c7b1a2194d53d98865d33cf1bc6111572876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SOC_PEN_DETECT_ODL, SOC_SAR_INT_L and WWAN_AUX_RESET_L are not connected
in nipperkin. Override those GPIO configurations.
BUG=None
TEST=Build and boot to OS in Nipperkin.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7e497f83593472ecf4927e5379e1dd7786e77e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
WWAN_AUX_RST_L is asserted during S0i3 entry. But it needs to be
de-asserted before PCIe link training during S0i3 resume. Otherwise the
concerned gpp_bridge_2 PCIe device is not enumerated on Soi3 resume.
This change feeds in the WWAN_AUX_RST_L GPIO in the DXIO descriptor so
that SMU de-asserts this reset on S0i3 resume.
BUG=b:199780346
TEST=Build and boot to OS in Guybrush. Perform suspend/resume cycles for
500 iterations. Ensure that the PCIe devices enumerate fine.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I588c490bf3f8a7beffefc3bfd8ca5167fcbcb9a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Instead of a const port descriptor, make it configurable. This will help
to avoid adding duplicate tables for every minor configuration updates.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform suspend/resume, warm and
cold reboot cycles for 10 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: If616a08ba54fddab25e5d0d860327255dfd43cbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the CnviBtAudioOffload UPD and program the corresponding
BT VPGIOs.
BUG=b:202913826
TEST=emerge-brya coreboot and verify it builds without error.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id81cba82742f552c098ec3719a0b453b752dc5c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds LTE power off sequence for bugzzy.
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I6be0e23b9c2c2bed9745011920394006fdaabae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable/disable LTE function based on DB_PORTS field of FW_CONFIG.
- GPIO control
- USB port setting
BUG=None
BRANCH=dedede
TEST=FW_NAME=bugzzy emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I8363f8e7052ff9cfa423063a7e8f5a0f9ce1df2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Support Parade ps8640 as the second source edp bridge for some trogdor
board variants/revisions.
BUG=b:194741013
BRANCH=trogdor
TEST=verified firmware screen works on lazor rev9
Change-Id: Iae5ccd8d9d33d60e4c37011ecffdd7a05af59ab2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_ADLRVP_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: If68c118f22579cc0a3db570119798f0f535f9804
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56221
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These changes include ELAN touchpad to ACPI tables and configure GPIO's.
BUG=None
Test=Boot board, touchpad should be functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I78e5e133f7d3af47395819a79638a90fee4fd19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Anahera has 4 thermal sensors, so add the missing sensors settings.
BUG=b:203187535
TEST=build and verified by thermal team.
Change-Id: I0e5c0d9c09c88cc95fdfd77b96800a0f4929d7d2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Because of a change in the chromium OS kernel machine driver for
the MAX98357A, a _HID that matches MAX98360A has to be used.
(https://chromium-
review.googlesource.com/c/chromiumos/third_party/kernel/+/3070268/)
BUG=b:200778066
TEST=FW_NAME=anahera emerge-brya coreboot
Change-Id: Ic68373920d9135e614ff792149079de451ec6e60
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Based on the latest schematics, change eMMC CLKREQ from CLKREQ#2 to CLKREQ#6
BUG=b:197850509
TEST=build and boot into eMMC
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc87c864b62a37fc3fa7a4a9a7722bf286c007b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I0720a51336f374f709c392c4bae4ad3e4c580a2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=None
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I91183f33b92569dd49967ef866d58043d79c287b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ALC5682-VD/ALC5682-VS load different kernel driver by different _HID.
Update the _HID depending on the AUDIO field of fw_config.Define fw
config bit 5-7 in coreboot for codec.
BUG=b:202913837
TEST=FW_NAME=taeko emerge-brya coreboot
Change-Id: I635b173e0fe4c46d28f2c29fecee1998b29499b1
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_JASPERLAKE_RVP_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig that the configuration
is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: Ic7552195ed5a3ae6ab8e456d7d38d5539a052009
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_KBLRVP_COMMON`, which is used as base for each
variant.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: I2a9c12a15c098fcb64c006a707c94a1aed93d73a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Rework Kconfig file that each variant has its own config option with
their specific selects / configuration and move common selects to
`BOARD_INTEL_COFFEELAKE_COMMON`, which is used as base for each
variant.
Also, move selects from Kconfig.name to Kconfig so that the
configuration is at one place and not distributed over two files.
Built each variant with `BUILD_TIMELESS=1` and all generated
coreboot.rom files remain identical. Excluded the .config file by
disabling `INCLUDE_CONFIG_FILE` to make this reproducible.
Change-Id: I3b3d3cff5ea7a3f4d1c4ddd911240763e4891e06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:192137970
TEST=FW_NAME=kano emerge-brya coreboot and boot to OS.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I20bf5ca66c6d05229c6d72058c5a73f38a58be3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.
BUG=b:189177538
Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds sub-regions to SI_ME in chromeos.fmd. These are
required to support stitching of CSE components.
BUG=b:189177538
Change-Id: I4da677da2e24b0398d04786e71490611db635ead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make the `get_cst_entries()` function provide a read-only pointer. Also,
constify the actual data where applicable.
Change-Id: Ib22b3e37b086a95af770465a45222e9b84202e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As long as there is only one PCI segment we do not need
more complicated MCFG generation.
Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Retimer FORCE_PWR GPIO is a debug GPIO, that has to be set LOW, to allow Retimer LC Domain
to toggle during a switch from DP Alt to TBT Alt modes.
Contrary to DS specifying it may be left unconfigured, hence floating, there are instances
seen during boot, where it stays HIGH (adlmrvp) or LOW (adlprvp).
Hence configure it to LOW.
Branch=none
Bug=none
Test=Boot to OS, connect TBT dock which enumerates in DP Alt,
Login, TBT dock enumerates in TBT Alt
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I0ff58823785a31c70535ad9c913c06a653884a2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
All boards with DRIVERS_GENERIC_IOAPIC select it.
Presumably the related configuration of routing IRQ0 when
IOAPIC is enabled should be always done to provide i8259
legacy compatibility for payloads.
Change-Id: Ie87816271fa63bba892c8615aa5e72ee68f6ba93
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use the common ACPI code to reduce code duplication.
After this change, `PSS_MAX_ENTRIES` is honored correctly in P-state
table generation (as of commit c2540a9) and the number reduces from 10
to 7 entries.
Also, remnants of P_BLK support missed in CB:58096 will vanish.
Tested on google/fizz: no errors in dmesg, ACPI tables remain the same
(except PSS, as mentioned above).
Change-Id: I1ec804ae4006a2d9b69c0d93a658eb3b84d60b40
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Switch to common GNVS. No additional fields to those being present in
common GNVS are used by any SKL/KBL device. Thus, they're dropped
completely.
Change-Id: I87ab4ab05f6c081697801276a744d49e9e1908e0
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The `IRQ_SLOT_COUNT` value is only meaningful when generating a PIRQ
table. None of these boards do it, so specifying this value achieves
absolutely nothing. Drop it to prevent further useless copy-pasting.
Change-Id: I2d63b850c03fc1471c0eef180e8b621311b2c336
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base
addresses of the I2C controllers, so align Stoneyridge with this. The
ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now
since this might change behavior in the OS and would also change the
resulting binary of a timeless build.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the spec to correct the WWAN poweron and powerdown sequences.
BUG=b:195625346
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I232d283a9d6093f5da64fcdce44e5cb640e3df0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58319
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support GL9763E as a eMMC boot disk
BRANCH=none
BUG=b:202192686
TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taeko.
Cq-Depend: chromium:3153210
Signed-off-by: Kevin.Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I5db2b229ce1bbea54efe15f5288f13f8d4656899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
The definition of those bits changed between Picasso and Renoir/Cezanne
so add a comment where those bit definitions are used as well.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If1cf4b06fc35f94cbd482f2869fcc64739e7d272
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The writes were originally added due to being part of the initialization
sequence in the reference code, but coreboot already has those registers
cleared by the time we reach this part of the code, so we can drop these
redundant writes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43344460e5355664841d77daf1df3fd386e047e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
I2C_BASE_ADDRESS is the beginning of the MMIO space that contains the
I2C controllers MMIO. I2C[ABCD]_BASE_ADDRESS are the base addresses of
the 4 I2C controllers, so use I2CA_BASE_ADDRESS instead here.
TEST=Timeless build results in identical image for Google/Treeya.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie8d6a438f76cd33929f5070f9ec6b2f280f471a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This reverts commit 6260bf712a.
Reason for revert: This CL did not handle Intel GPIO correctly. We need
to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel
SoC.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure I2C high / low time in the device tree to ensure Touchpad
I2C CLK runs accurately between 380 kHz and 400 kHz.
Measured I2C frequency just as below after tuning:
Touch Pad CLK: 389.2 KHz
BUG=b:202787528
TEST=Build and check after tuning I2C clock is between 380 kHz and 400 kHz
Change-Id: I0f9d062fc611de0062a39849aee1174268391682
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig
does not exist in the coreboot tree (including submodules), drop it.
These files should be stored in the `site-local` subdirectory and the
paths specified for each board in `site-local/Kconfig`. For example:
config VGA_BIOS_FILE
default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200
Note that this is just an example. There are better ways to structure
one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option
would be one of them, though variants may still need special handling.
Also, update autoport to not generate `VGA_BIOS_FILE` defaults.
Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is
enabled. On some variants, this engine is used by storage controllers.
Fix it by adding a weak override that returns no PCIe WWAN by default.
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is
enumerated on boards where it is stuffed.
Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Scout only uses I2C 1, 2, and 3 in DVT units. This removes extraneous
I2C configuration copied from Puff.
BUG=b:202195805
TEST=Boot scout, verify no more errors due to missing I2C devices
Change-Id: Ide70a53e83b3e14540873062e3bef24d1134d2e1
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
S3 is not currently functional on Guybrush. Remove support from ACPI.
BUG=b:202401767 b:181766974
TEST=Boot Guybrush
Confirm 'deep' is not in /sys/power/mem_sleep
Confirm S0ix suspend/resume still works
BRANCH=None
Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the PCH serial IO settings, suitable for this mainboard.
Change-Id: I3c9915b2d52fbc6a15ac1e68c77bfb3983f7b1cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Correct the USB settings, suitable for this mainboard.
Change-Id: I691d91d2a76e27b8efdc18eeae737a78e9ae38fa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard has its own coreboot ready LED. The LED is switched
on via GPIO GPP_F20.
Change-Id: I3570d691e90d2cb6e11b856b876f0327da118522
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Init overridetree based on the schematics.
Refer to brya0/overridetree.cb to update the settings of the devices
including DPTF, WIFI, NAU8825 and etc.
Refer to kano/overridetree.cb to update the SSD settings (pcie4_0).
TODO: DPTF and USB positions will be further updated later.
BUG=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently override speed config is applied only for non EM100 cases.
For EM100 case, override speed board version defaults to 0 leading to
"comparison of unsigned expression >= 0 is always true" error. Fix this
error by defining the override speed config for both EM100 and non-EM100
use-cases.
BUG=None
TEST=Build Guybrush for both EM100 and non-EM100 cases.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No need for dynamic config (and the additional RAM training time)
on a Chromebox; always use high power/high performance mode.
Change-Id: I0295bac619af45a0d82da2bf39985c8bdcb77d5e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
No need for dynamic config (and the additional RAM training time)
on a Chromebox; always use high power/high performance mode.
Change-Id: I8ad773d1c616b746235ec67b98b83c5910464140
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add support to override SPI fast speeds based on board version from both
bootblock and verstage. Overrides apply for Guybrush only and SPI speed
is overridden from 66 MHz to 100 MHz starting board version 4. This will
help to improve the boot time on board version by ~60 ms and still allow
the old boards to boot with 66 MHz.
BUG=b:199779306
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Some poppy variants did not select a system type, which led to the
default desktop type being set. Select the best fit enclosure type
for each variant.
Alphabetize the variant-specific options for improved readability.
Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since the DRAM population is fixed to both channels on all mc_ehl boards
there is no need to have this 'half_populated' variable at all.
Simply use a fixed 'false' in the call of 'memcfg_init()' and delete
this variable here.
Change-Id: I783c17e6d92322a8b0c094cce803108e718011fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The preferred location for the SPD data on mc_ehl based boards is the
HW-Info data structure. Inside this structure there is a field of 128
bytes available for the SPD data. So in order to use it construct a
buffer in memory which is 256 bytes long (as FSP requests minimum 256
bytes for the SPD data) and where the upper 128 bytes are taken from
HW-Info holding the needed timing parameters for LPDDR4.
If there is a case where HW-Info is not accessible or where the
contained SPD data is not valid (by checking the CRC in HW-Info SPD)
fall back to fixed SPD data set in CBFS.
Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
1. Samsung K4U6E3S4AB-MGCL
BUG=b:202480992
TEST=emerge-dedede coreboot
Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com>
Change-Id: I811f32defd50a940a09f238d38c962d2caf42855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Update MAX98360 ACPI HID from "MX98357A" to "MX98360A"
BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.
Cq-Depend: chromium:3195465
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: I8a1155848856db0cc4f42cfee0d914f8d1186b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can
remove the clearing of that bit. This is split off from the previous
patch to be able to use timeless build to verify that the previous patch
didn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.
BUG=none
TEST=Timeless build for guybrush results in identical binary.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fizz's USB ACPI code is intended to allow the OS to control port
charging power, but since Fizz's ports are dumb (vs smart), it
controls power to the port itself. The end result is that active
ports become disabled when rebooting from Windows (10/11), and
power is not restored until the device is powered down (a warm
reboot is not sufficient).
Subsequent Chromebox models (eg, Puff-based variants) don't bother
with EC-controlled USB port power, so just drop it since it's
problematic and provides no benefit.
Test: boot Windows 10/11, reboot, observe active USB ports still
functional (eg, USB KB still works)
Change-Id: I2c13d49b3ce8de8b0a38512db3c57d0c8ecbf0ad
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Caroline uses a Wacom digitizer, so adjust the ACPI HID
so that the proper drivers attach under Windows/Linux.
Change-Id: I732b09001dc41a91a32a5f9260abdab435b28b8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Before attempting another commit 6260bf71 (vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main), ensure that guybrush programs
GPIO_EC_IN_RW (GPIO_91) as an early GPIO so that it can be read from in
verstage.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: Ia6dcb225bbca89f3a873aad75a7d67625cdd3742
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. Fix PCIe slot capabilities not being really read from an IIO root
port device. The Hot-Plug capability of IIO root port cannot be
enabled due to FSP limitation (v2.1-0.2.2.0), but the code should
reflect the true capabilities by reading the root port device's CSR.
2. Initialize the characteristics flags to 0 in the for-loop to fix the
issue of the flags values persists to the next iterations.
Tested=On OCP Delta Lake, dmidecode -t 9 shows the expected results.
For example without the fix it shows 'Hot-plug devices are supported'
but in fact it's not:
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Hot-plug devices are supported
Bus Address: 0000:00:1d.0
With the fix it shows the correct result:
Handle 0x0016, DMI type 9, 19 bytes
System Slot Information
Designation: SSD1_M2_Data_Drive
Type: x4 PCI Express 3 x4
Current Usage: Available
Length: Short
ID: 1
Characteristics:
3.3 V is provided
PME signal is supported
Bus Address: 0000:00:1d.0
Change-Id: Iea437cdf3da5410b6b7a749a1be970f0948d92d9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58100
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason, we have to adjust the PIR8
register (0x3150) which is responsible for PCIe device 25h. The bridge
is connected to PCIe root port 7.
The following routing is required:
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB#
TEST:
- Boot into system software
Change-Id: Id6bb8d00458c4d1e3fefd01ac3848078355868d9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In upcoming patches, we need mainboard specific adjustments.
Change-Id: Icf9d829b19b2d26a39ad34be4658064083e9da6d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Enable LPC ComB on this mainboard.
TEST:
- Boot Linux and check with 'dmesg | grep tty'
Change-Id: I7ec58685a723c177df18144011934b206e6425d0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard uses an eSPI-to-LPC bridge for console output. For this
reason, the internal LPSS UART must be disabled.
Change-Id: I86777cf719def331f4d257ddd94e9a87125ebce8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Set the GPIOs according to the circuit diagram for this mainboard.
Change-Id: I19dc24a16ee9f533b45879bf60fb441e24018cc8
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard has only SATA Port 1 available with no device sleep
feature.
Change-Id: I338833f2f9bcb407599cfc676ead0b8a9d7379bd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This mainboard has SD slot available and therefore it should be enabled.
Change-Id: I0c97e2dc589bf6b89713a473925e42a20278f457
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board has the RTC RX6110SA connected to the I2C2 instead of SMBus
as in mc_ehl1. Set the bus speed for I2C2 to 100 kHz, since this RTC
only supports the standard speed.
TEST:
- Console Log shows no errors for RX6110SA during I2C2 init
- Finalize device for I2C 00:32 shows correct date and time
Change-Id: I679c6397fa0d213a25eebaf8a9e0bda9941acd26
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since this variant uses different DDR4 devices compared to mc_ehl1 in a
memory down configuration, the SPD data file must be adapted.
In a first configuration we use Micron MT53D512M32D2NP modules.
Following values were adjusted according to this board characteristic
and with help of Serial Presence Detect (SPD) for LPDDR3 and LPDDR4
SDRAM Modules JEDEC Spec and the Specification for this Micron modules
itself:
- SPD Byte 4 - only 4Gb density instead of 8Gb for mc_ehl1
- SPD Byte 5 - different Row and Column Address Bits
- SPD Byte 29/30 - 4Gb LPDDR4 needs 130ns tRFCab
- SPD Byte 31/32 - 4Gb LPDDR4 needs 60ns tRFCpb
Change-Id: Icb25f418952f0c96117140863d0d9c897d814ac5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add ALC5682-VS codec support in corori.
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO field of ssfc.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:201372531, b:194436265
TEST=ALC5682-VD/ALC5682-VS audio codec can work.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2f3edb0b594066714b42050a411103a215e68b12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
nipperkin has different H/W topology to guybrush that the eMMC device
is on a different GPP:
guybrush: GPP3
nipperkin: GPP2
Hence we need to enable RTD3 for nipperkin additionally which refers
to this one:
https://review.coreboot.org/c/coreboot/+/54967
BUG=b:200246826
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
run suspend test on eMMC sku
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I1dca8f9e4739514d2d024374d8686f27b25582a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Before attempting another commit 6260bf71 ("vboot_logic: Set
VB2_CONTEXT_EC_TRUSTED in verstage_main"), ensure that brya's variants
all program EC_IN_RW as an input GPIO in bootblock so that it can be read
from in verstage.
Change-Id: I6b1af50f257dc7b627c4c00d7480ba7732c3d1a0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
This patch enables eNEM flow for ADL-M
TEST=Able to build and boot ADL-M RVP using eNEM mode.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I69959f4c53f4073e6e8b51491747d8358b4c907b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Enable SATA power optimizer as recommended by Intel. Tested, a SATA SSD
is still detected correctly by SeaBIOS (version 1.14.1).
Change-Id: Ia6d29de08583dfc0c2d38e8395adcaa2c540ec7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
BT offload hardware design is using only i2s0 pins. Need to disable
i2s2 pins which are not used. As per the hardware spec there is an OR
operation between vgpio and physical gpio pins related to i2s2. During
BT offload configuring the i2s2 pins to its native function is causing
offload issue on proto 2 boards.
BUG=b:201736222
TEST=Verified BT offload on brya on proto 1 and proto 2.
Change-Id: Ifbc53848c6ad12e537216cac3c2871088c094f3d
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
As we checked the panel doesn't display firmware screen if we hold
GPP_D5(TOUCHSCREEN_RESET) low on bugzzy. It's because of that bugzzy
uses the built-in touch screen on the panel, the panel seems like
under reset state by the TOUCHSCREEN_RESET signal.
This change sets default GPP_D5 level to high for bugzzy.
BUG=b:None
BRANCH=dedede
TEST=built and verified bugzzy showed firmware screen
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I53e4fc52ceb14ba23c22d3c105f65634b09029f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Doan <edoan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch adds the setting of PsysPmax to 145W according to
the brya board design.
BUG=b:195615830
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: I996a11f76fdc0c8babe0037219f5b43e45e459dd
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SHRM is a system hardware resource manager. It is used to manage run time
DDRSS activities. DDRSS stands for DDR subsystem.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
by trying DDR clocks which through SHRM RSI command.
Change-Id: I44484573a829eaefbd34907c6fe78d427506a762
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
GPIO PM was disabled for brask to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.
TEST=Boot brask to OS, ensure no TPM errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b66b5526d8b80775cb7588ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
GPIO PM was disabled for adlrvp to evaluate if longer interrupt pulses
are required for ADL. Since ADL requires 4us long pulses (EDS:626817),
GPIO PM can be enabled. This change drops the GPIO PM override and
re-enables dynamic GPIO PM.
TEST=Boot adlrvp to OS, ensure no TPM timeout errors.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7b66b5525d8b80775ab7578ce6b12181af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.
Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.
Add a new section RW_SPD_CACHE to fmd for caching SPD data.
The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.
BUG=b:194055762
BRANCH=None
TEST=build pass
Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Correct OVTI2740 information for Kano:
MIPI camera CIO port, HID and Link Freq
BUG=b:200974074
TEST=Build and boot on Kano
camera driver is not probed before,
and it can now be probed properly
after this change.
Signed-off-by: Lai, Jim <jim.lai@intel.com>
Change-Id: I4612c9d42cd59cba0991b763224f77b7af33770b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1. The original algorithm for I2C speed cannot always make the
timing meet I2C specification so a new algorithm is introduced
to calculate the timing parameters more correctly.
2. Some I2C buses should be initialized in a different speed while
the original implementation was fixed at fast mode (400Khz).
So the mtk_i2c_bus_init is now also taking an extra speed
parameter.
There is an equivalent change in kernel side:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1
BUG=b:189899864
TEST=Test on Tomato, boot pass and timing pass
at 100/300/400/500/800/1000Khz.
Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com>
Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PL4 value dynamically for adlrvp board based on CPU SKUs
which is detectable at runtime. These values are based on
platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
On 682:
Overriding power limits PL1 (4000, 28000) PL2 (64000, 64000) PL4 (140000)
Change-Id: I9c0c418e2548cc7f9aa647a5ad98123b33e9f9b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move MILLIWATTS_TO_WATTS macro in power_limit header file
so all other files can use the same macro.
BUG=None
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: Ic7ecba06b0e0a47546f7307cbfbc3ce0fc634bc3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set power limit values dynamically based on CPU TDP and PCI ID of SKU.
These values are as per platform design specification.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I8ba901fe7c978aad43b85a860c71b33bfbff2ff5
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I508f7e21888cc1938aa9a6f0066c17029773974b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
Follow up commit 658d7c5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I494e0edc135d730cf7bb437f0196cdf233d970d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There are currently two variants for mc_ehl where different UARTs are
used for the console. Move the Kconfig switch UART_FOR_CONSOLE to the
Kconfig of the variant and select the matching value there.
Change-Id: I7152013a0e32ff151b92932a47953705e591dc0d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58052
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new variant of the mc_ehl board called mc_ehl2. This patch just
copies the files and renames things where needed.
Following patches will adapt the needed features for this new variant.
Change-Id: I3ec3c091017fd66fe6a09216203cdc7c9e833846
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Update to recommended Rcomp drive strength value for DDR4 as per
MRC team's input.
Additionally, add space around the `targets` array.
Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
M.2 spec describes PERST# should be sequenced after power enable.
BUG=b:201512872
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie164ddb29f947e190fa87b31165e3c84b07926e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58034
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In CB:52662 when MIPI display support was added, we accidentally changed
the code flow for eDP displays such that i2c_init() will no longer be
called when display_init_required() is false. This is a problem because
on this platform, i2c_init() does not just prepare the I2C controller
for firmware use, it also loads firmware to the controller that makes it
behave like an I2C device in the first place -- a step that the kernel
cannot later do on its own if the firmware didn't already do it.
Skipping this initialization means the I2C controller becomes unusable
to the kernel.
This patch fixes the issue by making the i2c_init() unconditional again.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie4546c31d87d91113eeef7dc7a18599a87e6d6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58026
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initializing SAR sensor (QUP2, address 0x988000)
BUG=b:198456205
BRANCH=None
TEST=Boot into kernel and make sure no i2c errors for 0x988000 in
dmesg
Change-Id: I75b0e9173d4c49b5e7308158a678964d6637b225
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For Herobrine variants that include a finger print sensor, we will
need to power sequence it. We are using the same FP sensor as
trogdor, so we will follow the timings used for trogdor from
CL:2695676.
BUG=b:198474942
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_HEROBRINE -x -a -c max -B
Change-Id: Ica6eafc47cf1b95eeb8d94c6e0a8c88519665e3f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58021
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ID "10029836" for machine driver, "RTL5682" for ALC5682I and "MX98357A" for MAX98360.
BUG=b:198716348
TEST=Build nipperkin, codec is functional with new machine driver.
Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Change-Id: Iab9d11adb7cd08effa2a9b6a627832bd89cb3cb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define SSFC bit 9-11 in coreboot for codec within ec.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:193694180
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Iba91b51cbbe7adc502372c9a026867de61d8035d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The voltage rail discharge times have been measured, so therefore
the boot time on a cold boot when the CSE must go through a global reset
and thus a trip to S5 can be optimized. Select the lowest applicable
value for each PchPmSlp UPD that can be used with these measurements.
This is programmed in the baseboard because the measured discharge times
leave (what should be) plenty of margin for variants to also not violate
any power sequencing guidelines from the PDG.
BUG=b:184799383
TEST=verified time in S5 during a global reset is ~1s instead of 4s
Change-Id: Ia373c47b3967d68ddac21707c6eb4565d9d6519e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I2c4fb1933eda2eb75bfe9181f13e189ec66cadf9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that taeko can successfully
boot into OS with non-serial coreboot.
BUG=b:199969366 & b:200711149
TEST=Build FW and test with non-serial FW reboot 20 times pass.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I032c5b90fb2148c4075d6ead3e4161c0cc659b20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add wifi sar for magma.
Due to fw-config cannot distinguish between magolor and magma.
Using sku_id to decide to load magma custom wifi sar.
BUG=b:192423859
TEST= emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Iac15e958e61be6e3c136fb9be18b4695823ad1c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update PL1 min and max values to 6 W for Galith/Gallop systems.
BUG=b:201010771
BRANCH=None
TEST=Build and verify on Galith/Gallop system
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I0dfda3c2c830a2ce203668431f396859e782aa3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
For the next build phase, modify the HID of the speaker amp to
MX98360A.
BUG=b:199098681
BRANCH=none
TEST=build coreboot without error
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0c318464fca7d35bbffd7ea0f5694b83acedff0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Refactor DPTF section of code under the kracko overridetree. This makes kracko override dptf section of dedede/baseboard, because the DPTF tool's CRT, PSV and TSR3 settings are different than expected.
BUG=b:187482019
BRANCH=dedede
TEST=Built and tested on dedede system
Change-Id: Iacc543f961a7f4652ee8583920b1794f916c7ec9
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move max98373 amp ACPI info to I2C0 according to kano's schematics version KANO_MLB_Proto_0811.
BUG=b:192370253
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8f7a7938dd407666e0104ba64b22da85216a145f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.
BUG=b:199822704
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update the DPTF parameters received from the thermal team.
BUG=b:188596619
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I081963b97ed2dae0f5d026f6443c954b52347a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57919
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clevo indicated that DIMMs running at 2933 MHz are not supported on a
number of processors used for this model.
Change-Id: Iadf611a64de664c783696e51cfe858ca95903936
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Match the behavior of the other TGL-U boards.
Change-Id: Ida962255f7a2435319d739d59eb2dc58fe342ae8
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Setting srcclk_pin only works for PCH PCIe devices. Disable them on the
CPU RP and add a TODO.
Change-Id: I32db116feb33a8448eb8586fe9e882b8879489d4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I7255ac1ec6c43dd4b21325ae60e117458bea956d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I375ab879dd95d6a7a20644dc36312a1e62f58226
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I4e5be60d2784d003a388c52254514d0ab4d002b0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: Id26d9dfc3822b9120360fc2cb2ced8d67345a659
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
guybrush does not have a light sensor, do not include ACPI0008
ACPI device (Light sensor that will be managed by acpi-als IIO
kernel driver).
BUG=b:200823325
TEST=Check on Guybrush360 the sensor is not presented.
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Change-Id: Id1dcb3a01ee43f780e4b118d88a0351e4c543f5a
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This change config the DRAM speed to 3733 for primus.
BUG=b:200752480
BRANCH=none
TEST=Verified that `dmidecode -t17` shows the correct
configured memory speed
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2f3a9489dddcf102b0ffc71eb9cdab6ad38d1391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change replaces the device tree walks with device pointers by
using alias for dptf_policy device.
Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change replaces the device tree walks with device pointers by
using alias for following devices:
1. audio_rt5682
2. xhci0_bt
3. xhci1_bt
4. acp_machine
5. i2c2
Change-Id: I56921ab54716e4d771d9de1a479f191ca5657eba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
AMD Firmware tool allows configuring the directory table level in which
the binaries have to be added. This helps to achieve space and boot time
savings.
BUG=b:195329409
TEST=Build and boot to OS in Guybrush. Achieve a boot time savings of
~75 ms and space savings of ~600 KB per RW section.
Change-Id: Idc212b8c4f8aacfb0132983a8055f1e97af42983
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Due to the vGPIO is not set correctly, without setting those pins for PEG60,
CPU cannot communicate with PCH about the clkreq state.
BUG=b:200886824
TEST=FW_NAME=kano emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6adf73103ecb02c67d9a199e13d2ead9b8b2276f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.
This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
