Commit graph

1071 commits

Author SHA1 Message Date
Michael Niewöhner
056d552357 soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default
Fsp configures the USB over-current pin and overrides the according pad
configuration to NF1, regardless of the port being configured as disabled.

Thus, set the OC pin to 0xff ("disabled") in this case to prevent this.

This allows us to skip setting USBx_PORT_EMPTY in the devicetree for
disabled USB ports.

Change-Id: Ib8ea2ea26c0623d4db910e487b37255e907b299d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45112
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06 14:26:33 +00:00
Aaron Durbin
aa902036d0 elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE
The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.

BUG=b:159947207

Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-18 15:57:40 +00:00
Benjamin Doron
2875df1c9e soc/intel/skylake/acpi.c: Name devices on secondary bus
Naming a device allows an ACPI _ROM method to be written for it. GPUs
may require this to make the configuration data contained within
available to an OS driver. This may be required for GPUs that do not
contain their vBIOS, or perhaps the drivers require it in this form/fashion.

Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully
obtains the vBIOS via ACPI (kernel 5.7.11).

Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-17 07:12:46 +00:00
Benjamin Doron
c5fb088d0e soc/intel/skylake: Call mainboard ACPI sleep methods
Skylake mainboards also can implement ACPI functionality surrounding sleep.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-17 06:08:10 +00:00
Felix Singer
e32fa4e152 soc/intel/skylake: Refactor PEG configuration
Simplify some if-blocks which are used for the configuration, enablement
and disablement of the PEG devices.

This changes the logic of the code, since it configures PegxEnable
before the if-blocks, where x is the number of the PEG device, and the
further configuration of the PEG devices depends on the enablement of
PegxEnable.

Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-08-14 21:57:09 +00:00
Felix Singer
736de9f246 soc/intel/skylake: Factor out unnecessary if-else-block
Move InternalGfx config option out of the if-else-block and replace the
left over config option IgdDvmt50PreAlloc by a ternary expression. Also,
adjust related code comments to fit the new logic of this code.

This changes the logic of the code, since InternalGfx is configured
first and IgdDvmt50PreAlloc depends on its value. The negation in the
ternary expression is removed to improve the readability.

Change-Id: I89ff17f4574a7ade228c1791f17ea072fb731775
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-14 21:00:33 +00:00
Felix Singer
4e9687c416 soc/intel/skylake: Use PEG definitions from pci_devs.h
Change-Id: I7114deed35f25e74ac508f08e9c85653a7fe39ed
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-14 20:59:33 +00:00
Felix Singer
e1528fe358 soc/intel/skylake: Add PEG device definitions to pci_devs.h
Change-Id: Ib2453425f44e2b4abd5566f454ae68b704dbc33e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-14 20:59:12 +00:00
Felix Singer
e104934a23 soc/intel/skylake: Refactor ternary expressions
To be consistent with the rest of the tree, replace all left ternary
expressions, which are used for device enablement / disablement,
with `dev && dev->enabled`.

Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-13 17:40:04 +00:00
Felix Singer
e21866781f soc/intel/skylake: Enable CIO depending on devicetree configuration
Currently, CIO gets enabled by the option Cio2Enable, but this
duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the CIO controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Cio2Enable setting, and missing entries
were added.

Change-Id: I65e2cceb65add66e3cb3de7071b1a3cc967ab291
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08 16:32:41 +00:00
Felix Singer
4d5c4e069c soc/intel/skylake: Enable SA IMGU depending on devicetree configuration
Currently, SA IMGU gets enabled by the option SaImguEnable,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SA IMGU controller.

All corresponding mainboards were checked if the devicetree
configuration matches the SaImguEnable setting, and missing entries
were added.

Change-Id: I293a20a321c75f82a57cbd5339656d93509b7aa6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-08 12:01:18 +00:00
Felix Singer
88264ef30b soc/intel/skylake: Add IMGU definitions to pci_devs.h
Change-Id: Iee7393ae7e2aca94151c242894c64ac902f4d437
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-08 12:00:39 +00:00
Felix Singer
52919523c1 soc/intel/skylake: Enable SDXC depending on devicetree configuration
Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-08 12:00:23 +00:00
Felix Singer
9c1c00968c soc/intel/skylake: Enable thermal subsystem depending on devicetree
Currently SA thermal subsystem gets enabled by the option Device4Enable,
but this duplicates the devicetree on/off options. Therefore depend on
the devicetree for enablement of the SA thermal subsystem controller.

All corresponding mainboards were checked if the devicetree
configuration matches the Device4Enable setting, and missing entries
were added.

Change-Id: I7553716d52743c3e8d82891b2de14c52c6d8ef16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44026
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-07 21:30:02 +00:00
Felix Singer
c787a246f9 soc/intel/skylake: Add SA thermal subsystem definitions to pci_devs.h
Change-Id: Ic83cfbe2a715db317d94c2b9c6cdd8c58a43612f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-08-07 21:29:21 +00:00
Subrata Banik
b7db12bf7e {nb,soc}/intel: Use get_current_microcode_rev() for ucode version
This patch removes all redundant read microcode version implementation
from SoC directory and refer from cpu/intel/microcode/microcode.c file.

TEST=Able to get correct microcode version.

Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05 15:36:38 +00:00
Elyes HAOUAS
5ba154a597 src: Use space after 'if', 'for'
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-05 11:37:00 +00:00
Angel Pons
96a80133e1 soc/intel/skylake: Add RMRRs after all DRHDs
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:

 BIOS implementations must report these remapping structure types in
 numerical order. i.e., All remapping structures of type 0 (DRHD)
 enumerated before remapping structures of type 1 (RMRR), and so forth.

So, update the corresponding code to adhere to the specification.

Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-08-04 21:43:45 +00:00
Felix Singer
048d9b5cba soc/intel/skylake: Enable HDA depending on devicetree configuration
Currently HDA gets enabled by the option EnableAzalia, but
this duplicates the devicetree on/off options. Therefore use
the on/off options for the enablement of the HDA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableAzalia setting.

Change-Id: Id20d023b2f286753fb223050292c7514632e1dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43866
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 21:04:24 +00:00
Felix Singer
91dfb92038 soc/intel/skylake: Enable HECI3 depending on devicetree configuration
Currently HECI3 gets enabled by the option Heci3Enabled, but
this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the HECI3 controller.

I checked all corresponding mainboards if the devicetree configuration
matches the Heci3Enabled setting.

Change-Id: I4f99d434dfee49a9783e38c3910b9391d479cb83
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43864
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 20:58:58 +00:00
Felix Singer
aff69be254 soc/intel/skylake: Enable eMMC depending on devicetree configuration
Currently eMMC gets enabled by the option ScsEmmcEnabled, but this
duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the eMMC controller.

I checked all corresponding mainboards if the devicetree configuration
matches the ScsEmmcEnabled setting.

Change-Id: I3b86ff6e2f15991fb304b71d90c1b959cb6fcf43
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:57:39 +00:00
Felix Singer
87aecf811d soc/intel/skylake: Enable TraceHub depending on devicetree configuration
Currently TraceHub gets enabled by the option EnableTraceHub, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the TraceHub controller.

I checked all corresponding mainboards if the devicetree
configuration matches the EnableTraceHub setting.

Change-Id: Idcd1e5035bc66c48620e4033d8b4988428e63db9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43847
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29 20:57:21 +00:00
Felix Singer
ffe90c528b soc/intel/skylake: Enable SMBus depending on devicetree configuration
Currently SMBus gets enabled by the option SmbusEnable, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SMBus controller.

I checked all corresponding mainboards if the devicetree configuration
matches the SmbusEnable setting.

Change-Id: I0d9ec1888c82cc6d5ef86d0694269c885ba62c41
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:47:56 +00:00
Felix Singer
57c8143350 soc/intel/skylake: Enable LAN depending on devicetree configuration
Currently LAN gets enabled by the option EnableLan, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the LAN controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableLan setting.

Change-Id: I36347e8e0f0ddba47aec52aeb6bc047e3c8bfaa4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-29 20:45:53 +00:00
Felix Singer
0901d03085 soc/intel/skylake: Enable SATA depending on devicetree configuration
Currently SATA gets enabled by the option EnableSata, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement of the SATA controller.

I checked all corresponding mainboards if the devicetree configuration
matches the EnableSata setting.

Change-Id: I217dcb7178f29bbdeada54bdb774166126b47a5a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
2020-07-29 20:45:29 +00:00
Patrick Rudolph
0f82309562 Revert "src: Remove unused include <cpu/x86/smm.h>"
This reverts commit 6f739184dd.

Fixes compiling the SMMSTORE driver.

Change-Id: I3b4d4063ded50529bea48f8d865c1689fe9e26d1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-28 06:05:20 +00:00
Martin Roth
c25c1ebd9e src: Update bare access to BOOL CONFIG_ vals to CONFIG()
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:21:03 +00:00
Kyösti Mälkki
c731788929 cpu,soc/intel: Drop select SMP
Implicitly selected with MAX_CPUS != 1.

Change-Id: I4ac3e30e9f96cd52244b4bae73bafce0564d41e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 20:59:52 +00:00
Angel Pons
a634dab1a6 skylake boards: Factor out copy-pasted PIRQ routes
Put them in common code just in case something depends on the values.

Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 20:54:32 +00:00
Elyes HAOUAS
6f739184dd src: Remove unused include <cpu/x86/smm.h>
Found using:
diff <(git grep -l '#include <cpu/x86/smm.h>' -- src/) <(git grep -l 'SMM_DEFAULT_BASE\|SMM_DEFAULT_SIZE\|SMM_BASE\|SMM_ENTRY_OFFSET\|SMM_SAVE_STATE_BEGIN\|APM_CNT\|APM_STS\|apm_control\|set_smm_gnvs_ptr\|set_acpi_mode_on_exit\|io_trap_handler\|southbridge_io_trap_handler\|mainboard_io_trap_handler\|southbridge_smi_set_eos\|smm_southbridge_clear_state\|global_smi_enable\|global_smi_enable_no_pwrbtn\|cpu_smi_handler\|northbridge_smi_handler\|southbridge_smi_handler\|mainboard_smi_gpi\|mainboard_smi_apmc\|mainboard_smi_sleep\|smramc_dev\|smramc_reg\|run_smm_relocate\|smm_is_really_enabled\|is_smm_enabled\|smram_open\|smram_close\|smram_lock\|smm_open\|smm_close\|smm_lock\|_binary_smm_start\|_binary_smm_end\|smm_runtime\|smm_module_params\|smm_handler_start\|smm_get_save_state\|smm_handler_t\|smm_loader_params\|smm_setup_relocation_handler\|smm_load_module\|backup_default_smm_area\|restore_default_smm_area\|smm_region\|SMM_SUBREGION_HANDLER\|SMM_SUBREGION_CACHE\|SMM_SUBREGION_CHIPSET\|SMM_SUBREGION_NUM\|smm_subregion\|smm_list_regions' -- src/)|grep '<'

Change-Id: Id96ddad974a1460a6e6580cee1e45c863761af06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 18:45:00 +00:00
Felix Singer
4e58ce1535 soc/skylake: Configure SATA options only if SATA is enabled
Change-Id: I2860375c8ec4f9cda7709ee26db4c132a3b252b9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
2020-07-26 12:53:33 +00:00
Elyes HAOUAS
04071f43bc src: Use ACPI macros
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21 18:26:47 +00:00
Angel Pons
12a4d05b9e src: Report word-sized access for PM1a_EVT
According to the ACPI specification, version 6.3:

    Accesses to the PM1 status registers are done through byte or word
    accesses.

The same is said about the PM1 Enable registers. Therefore, reporting
dword-sized access is wrong and means nothing anyway. Since some other
platforms use word-sized access, use word everywhere for consistency.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:33:32 +00:00
Angel Pons
79572e4f32 src: Make HAVE_CF9_RESET set the FADT reset register
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.

To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20 13:23:13 +00:00
Angel Pons
3eb8dbaee2 src: Drop useless cache flush settings in FADT
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20 13:22:44 +00:00
Angel Pons
a208c6ce73 src: Never overwrite fadt->flags
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:22:03 +00:00
Angel Pons
1b5a7dec43 src: Drop useless PM1b settings from FADT
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):

 If the PM1b_EVT_BLK is not supported, its pointer contains a value of
 zero in the FADT.

 If the PM1b_CNT_BLK is not supported, its pointer contains a value of
 zero in the FADT.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:16:05 +00:00
Angel Pons
77653e3bce src: Drop useless GPE1 settings from FADT
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:

 If a generic register block is not supported then its respective
 block pointer and block length values in the FADT table contain zeros.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:15:45 +00:00
Angel Pons
c3c7ef3ec2 soc/intel/skylake: Move acpi_fill_fadt to fadt.c
Intel southbridges do this.

Change-Id: I8ecf3c0b0c822185ca66bae1bd65b0cf24512a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-14 22:34:03 +00:00
Elyes HAOUAS
06a5e854e1 src: Drop unused <cpu/x86/tsc.h> include
Found using:
diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<'

Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14 16:14:33 +00:00
Angel Pons
6ab28b465a src/**/acpi/smbus.asl: Drop dead code
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.

Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-06 23:11:08 +00:00
Angel Pons
d9dea65615 soc/intel: Drop unused #include <reg_script.h>
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.

Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-06 19:29:07 +00:00
Edward O'Callaghan
ed31024d1d soc/intel/skylake: Update ASL syntax in xhci.asl
Use some defines as well for clarity.

Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42898
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-01 05:21:09 +00:00
Kyösti Mälkki
0c1dd9c841 ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.

Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-30 09:19:10 +00:00
Sumeet R Pawnikar
360684b41a soc/intel/common: add TCC activation functionality
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.

BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.

Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-28 21:47:52 +00:00
Angel Pons
a23aff3651 src: Report byte-sized access for GPE0
According to the ACPI specification, version 6.3:

    OSPM accesses GPE registers through byte
    accesses (regardless of their length).

So, reporting dword-sized access is wrong and means nothing anyway.

Tested on Asus P8Z77-V LX2, Windows 10 still boots.

Change-Id: I965131a28f1a385d065c95f286549665c3f9693e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42671
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-24 11:50:50 +00:00
Kyösti Mälkki
c3c55210ee ACPI: Replace smm_setup_structures()
Except for whitespace and varying casts the codes were
the same when implemented.

Platforms that did not implement this are tagged with
ACPI_NO_SMI_GNVS.

Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-24 11:49:15 +00:00
Kyösti Mälkki
000d91af00 soc/intel,chromeos: Fix EC RO/RW status in GNVS
For baytrail and braswell, explicitly initialise
it to ACTIVE_ECFW_RO without ChromeEC.

For broadwell and skylake, fix it to report actual
google_ec_running_ro() status.

Change-Id: I30236c41c9261fd9f8565e1c5fdbfe6f46114e28
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42389
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-18 12:51:09 +00:00
Kyösti Mälkki
eadd251bf7 cpu/x86: Define MTRR_CAP_PRMRR
Followups will remove remaining cases of PRMRR_SUPPORTED and
SMRR_SUPPORTED in the tree.

Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:05:16 +00:00
Kyösti Mälkki
040c531158 soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:03:44 +00:00