Provision the configuration of the Fintek F71869AD Hardware Monitor's
configuration by way of devicetree.cb. Make use of this in the
jetway/nf81-t56n-lf board to properly control fan's.
Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5580
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.
Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.
Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
ITE Super I/O's make use of this method to enter and exit in and out of
their PNP configuration. Provide functions for use in ram stage
component.
Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5666
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.
Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Convert the serial init to the generic romstage component and
corresponding boards using this sio.
Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Convert the serial init to the generic romstage component and
corresponding boards using this sio.
Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The romstage of Fintek Super I/O's is identical, leading to replication
of essentially the same code prone to bitrot. Herein we consolidate the
early pre-ram UART initialisation code into fintek/common, rather we
leave the exceptions to be implemented under model/.
More precisely we provide a well documented version of early_serial.c
under fintek/common and select by way of Kconfig as a generic romstage
component to Super I/O support. We leave future Super I/O's the option
to implement `non-standard` initialisation code should such a (unlikely)
need araise. A primary advantage is that new support for romstage serial
is now trival to add. We also provide some Kconfig documentation while
here.
Change-Id: I3c62561558a62ece944a167ba302fb7076bba001
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove some redundant includes. Fix repetitiveness in include guards and
strip some misplaced tabs for whitespaces.
Change-Id: I1f0bf6951cc6714f63e88b323754515fb02c089c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5572
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This super io support is poorly implemented and would not work for all
boards since it hardcodes values. Since there are no users of it, remove
for now pending a fresh reimplementation from scratch.
Change-Id: I818a9f4d2ab106b989824e49cee49d79acd6041a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5566
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Following the same reasoning as:
HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr
Removing hard coded magics and expose sio pnp api in romstage.
Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5565
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Rewrite early_serial.c implementation to honour a passed base address in
device_t, removing any hard coding of values. We also expose early sio
init functions as romstage symbols to avoid falsely #including
"early_serial.c" in romstage.c of board support.
Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5561
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Try to conform to some kind of standard/consensus for prototype
location. Correct headers while here.
Change-Id: Ie99b1801fa42ddefb9f25d54f326ba7131bd7089
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5499
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.
Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.
Removes:
CONSOLE_SERIAL_UART
HAVE_UART_IO_MAPPED
HAVE_UART_MEMORY_MAPPED
Renames:
CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO
CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM
Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.
Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.
Change-Id: I14c438968bfed917977862efd8a393ec48cb04c9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.
Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5417
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5437
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5436
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: I863c16634873224c17e43100271e9b91419724d0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5434
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
We should not be #include .c files, instead link early_serial into
romstage and provide a prototype.
Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5416
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The ASL compiler warned about "Control Method should be made Serialized
(due to creation of named objects within)". This commit eliminates the
warnings by changing those NonSerialized into Serialized.
Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5189
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There were ASL compiler warnings about "Size mismatch". This commit
eliminates the warnings by changing the ASL declarations of those
fields.
Change-Id: If851ed4892ef6c96acbff861abd7001ab67d9d66
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5190
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The asrock/imb-a180 mainboard is the first mainboard to use this
w83627uhg/nct6627UD sio. The default h/w clock setting is 0. Adding
the SIO in the mainboard Kconfig made the builder complain that the
set_uart_clock_source() wasn't being used. So the calls to that function
were uncommented.
Change-Id: Iedba035237c5c0fa230b02ff4799bb8c1b7bbd4a
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/4573
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Properly build the super i/o .c files. This prevents including
the .c file directly in romstage, which is generally bad practice.
Adding a Makefile and a .h file to include.
Change-Id: I0be66e94d3062a2c4a445cee2f12ec249598dc8b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4014
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move the floppy drive enumeration from _INI() and PROB(),
which stored the enumeration results into _FDE into _FDE().
_INI is called by any ACPI-capable OS on boot while _FDE
is rarely used. So it's better to run the enumeration when
requested rather than unconditionally.
Change-Id: Icf1e2a551806592faa8ba8d80fa8d02681602007
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The parallel port of the W83627HF can be configured on any port
between 0x100 and 0xFFC with 4 byte alignment for traditional modes
and 8 byte alignment for EPP mode. As the ACPI specification says
that the maximum acceptable starting address has to be a multiple
of the alignment granularity, correct the maximum starting address
from 0xFFC to 0xFF8.
Change-Id: I272e09d091149791f2867b1d06e4fc27bc1bb2cd
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/2942
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
As Nico noticed for the W83627DHG, the power management bits to power down
individual logical devices on Winbond superios are named counterintuitively
and need to be set when the logical device should be powered.
This corrects the power management methods for the W83627HF.
Change-Id: I98bccd550a0513c62bfa9480275f88c566691bc8
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3605
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is the first of a series of patches to provide support
for a new mainboard, Gigabyte GA-B75M-D3V.
This patch provides early serial for the superio and has been
tested on this mainboard. The code is based on IT8718F superio.
Change-Id: I5636199b49314166ed3b81e60b41131964dd44ff
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/3794
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The enumeration results are stored as five DWORDs in one 20 byte buffer.
Bytes 3, 7, 11 and 15 were used to set the lowest bit of each DWORD.
ACPI uses little endian, so 1, 4, 8 and 12 are the correct indices.
Change-Id: I793225cb1bb62fd148ecfa1e61e02f5d7be62cdb
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3602
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The PnP's logical device activation normally resides at 0x30. This might
have been overlooked as 0x29 looks very close to 0x30 in human eyes.
Change-Id: Id5d5a92f2683ebe1808b943f686c062151d216da
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The enumeration method tried to evaluate an one-byte OperationRegion
instead of a field in this OperationRegion, which resulted in an
AE_TYPE error at runtime.
Indexing the OperationRegion with a single field fixes this error.
Change-Id: I15dd7aa6ecafb3a215d165d2b721003446815025
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3603
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The W83627DHG has some power managements bits to power down individual
logical devices. These are called `* Power Down`. Counterintuitively and
in contrast to `Immediate Power Down` (bit to power down the whole chip),
these bits are set when the respective logical device is powered.
Unfortunately, our ACPI code set them wrong which led to disabled
devices after a S3 suspend/resume. Adding an option how to set the PM
bits and setting them to zero for the W83627DHG, corrects it.
Tested with kontron/ktqm77.
Change-Id: I8a472d480d4277721bd17c9f7c2ce44fa84e8ae2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3590
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add comments in PAR0._PRS explaining which dependent resource
descriptor puts the parallel port into EPP or SPP mode.
Change-Id: If4e224dbaf6f9105cde88d995d2e7c74fbf14502
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/3495
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
The SPI logical device on the W83627DHG uses the second i/o port
register pair but not the first one. So we have to also set `io1`
(the second io_info struct) and not `io0` in the pnp_info structure.
Setting the PNP_IO1 flag without a mask in `io1` caused coreboot to
hang in pnp_enable_devices() until commit aeead274 which added a
check for an unset mask.
Change-Id: I027d279b4641fecd88afb14d40fbe1c0bfbf81bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3391
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Find all the (ramstage) implementations of enter()/exit() functions
for the configuration state, register and call them through the new
struct pnp_mode_ops. As our standard PnP functions are aware of the
pnp_mode_ops, it's not necessary to call enter()/exit() around them
anymore.
Patch generated with the cocci below. It's not perfect. The movement
of the enter()/exit() calls is somehow fragile. So I checked the
remaining calls for sense, and changed some empty lines. Also a
duplicate insertion of pnp_conf_mode_ops had to be removed.
/* Try to find enter and exit functions by their outb() structure and
their usage around calls to our standard pnp functions: */
@ enter_match @
identifier enter;
identifier dev;
type device_t;
@@
void enter(device_t dev)
{
<...
outb(..., dev->path.pnp.port);
...>
}
@ exit_match @
identifier exit;
identifier dev;
type device_t;
@@
void exit(device_t dev)
{
<...
outb(..., dev->path.pnp.port);
...>
}
@ pnp_match @
identifier op;
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
identifier enter_match.enter, exit_match.exit;
type device_t;
identifier dev;
@@
void op(device_t dev)
{
...
enter(dev);
...
pnp_op(dev);
...
exit(dev);
...
}
/* Now add enter/exit to a pnp_mode_ops structure: */
@ depends on pnp_match @
identifier enter_match.enter;
identifier exit_match.exit;
identifier ops;
@@
+static const struct pnp_mode_ops pnp_conf_mode_ops = {
+ .enter_conf_mode = enter,
+ .exit_conf_mode = exit,
+};
+
struct device_operations ops = {
...,
+ .ops_pnp_mode = &pnp_conf_mode_ops,
};
/* Match against the new structure as we change the code and the above
matches might not work anymore: */
@ mode_match @
identifier enter, exit, ops;
@@
struct pnp_mode_ops ops = {
.enter_conf_mode = enter,
.exit_conf_mode = exit,
};
/* Replace enter()/enter() calls with new standard calls (e.g.
pnp_enter_conf_mode()): */
@@
identifier mode_match.enter;
expression e;
@@
-enter(e)
+pnp_enter_conf_mode(e)
@@
identifier mode_match.exit;
expression e;
@@
-exit(e)
+pnp_exit_conf_mode(e)
/* If there are calls to standard PnP functions, (re)move the
enter()/exit() calls around them: */
@@
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
expression e;
@@
-pnp_enter_conf_mode(e);
pnp_op(e);
+pnp_enter_conf_mode(e);
...
pnp_exit_conf_mode(e);
@@
identifier pnp_op =~ "^pnp_((alt_|)enable|(set|enable)_resources)$";
expression e;
@@
pnp_enter_conf_mode(e);
...
+pnp_exit_conf_mode(e);
pnp_op(e);
-pnp_exit_conf_mode(e);
@@
expression e;
@@
-pnp_enter_conf_mode(e);
-pnp_exit_conf_mode(e);
Change-Id: I5c04b0c6a8f01a30bc25fe195797c02e75b6c276
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3482
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current default implementation of pnp_enable() only disables devices
- if set so in the devicetree - but does not enable them. Enablement takes
place in pnp_enable_resources(). Yet, many PnP chips implement their own
version of pnp_enable() which also enables devices if set in the devicetree.
It's arguable, if enabling those devices makes sense, before they get
resources assigned. Maybe we can't write the resource registers if not,
who knows? The least we can do is providing a common implementation for
this behavior, and get rid of some code duplication.
Used the following cocci:
@@
expression e;
@@
+pnp_alt_enable(e);
-pnp_set_logical_device(e);
(
-pnp_set_enable(e, !!e->enabled);
|
-(e->enabled) ? pnp_set_enable(e, 1) : pnp_set_enable(e, 0);
|
-if (e->enabled) { pnp_set_enable(e, 1); }
-else { pnp_set_enable(e, 0); }
)
Change-Id: I8d695e8fcd3cf8b847b1aa99326b51a554700bc4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3480
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most PnP drivers align the initialization of their `device_operations`
with spaces. Unify this, so next autogenerated patches always match the
alignment.
Change-Id: I3f6baef6c8bb294c136354754125ea88c07a61a1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3479
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is loosely based on Christoph Grenz' ACPI code for the W83627HF
and makes use of the PnP super i/o ACPI framework.
Change-Id: I5e1cd09b83c0041f440562d2a1b73e4560589cb7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3288
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I'm trying to make writing ACPI code for super i/o devices more
comfortable.
pnp.asl hosts some general cpp macros.
The other four files are to be included in dsdt trees. They are
controlled by cpp macros which should be defined/undefined before
inclusion.
Work was inspired by Christoph Grenz' ACPI code for the W83627HF.
Change-Id: Idb55332ba9bc788c98964d30a450e0d734cf28ec
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3286
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
[1] http://review.coreboot.org/2424
Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Added in new support for Nuvoton NCT5104D LPC device.
Change-Id: I0af8c5e3e46fdd0a549475b30917897ae9e144a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/3072
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Put the ASL snippet for inclusion in the DSDT under the `acpi/`
folder as it is done for the other Super I/O devices.
$ find src/superio/ -name *asl
src/superio/ite/it8772f/acpi/superio.asl
src/superio/smsc/mec1308/acpi/superio.asl
src/superio/smsc/sio1007/acpi/superio.asl
src/superio/winbond/w83627hf/devtree.asl
As there are no users of this file yet, no other adaptations need
to be made.
Change-Id: Id10cd8897592b780c9fd3bd6b45ada4cf1fcf33e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2937
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Pins 78-85 are set to GPIO after power on or reset. To enable
UART B the pins must be redirected to it.
Look at W83627DHG databook version 1.4 page 185 Chip
(global) Control Register CR2C.
Change-Id: I12b094a60d9c5cb2447a553be4679a4605e19845
Signed-off-by: Wolfgang Kamp <wmkamp@datakamp.de>
Reviewed-on: http://review.coreboot.org/2626
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs. However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds. A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.
We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice. The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.
This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).
Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
This is the smallest possible change to make early_serial.c
compile when included from romstage.c.
early_serial could be reworked to be built as separate unit
(romstage-y), but that should be done for all SuperIOs,
not some individual outlier.
Change-Id: I90ee66b43c9677b86b1b5d6fcc8febfbe58d80dd
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1686
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
this function is used on serial output of tyan s8226
Change-Id: I5f7fa535b922b224e381886f1bea64623fa549ef
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1494
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Not all users use both functions, so add __attribute__((unused))
to prevent compiler errors.
Change-Id: I8485bb9150b04d1f9fdc231152a43bcd6fc713a7
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/1193
Tested-by: build bot (Jenkins)
Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Newer versions of IASL didn't like our IO constructs. Use
FixedIO instead, it's also shorter.
Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/934
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
early_serial and some ACPI needed for compilation
Change-Id: I5dd970676488697156e0630392884f31149ac85b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/824
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This includes only early serial support for now.
Change-Id: I9a2a439e1d17a989428033fdb4a4b813553dab6d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/823
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
1. Stop include c file.
2. W83627dhg Pin 89, Pin 90 are multi function pins,
add support to select them to I2C function.
Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/565
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
When CONFIG_EXPERT is set, compilation fails with:
src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors
This function isn't used in the code, so just remove it.
Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/533
Tested-by: build bot (Jenkins)
make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused
Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix multiple copy&paste errors and some other bugs in
devtree.asl. Redesign ENCM method to enter configuration mode
and set LDN by parameter. Reordered and commented some
statements to make the code a bit more readable. Add an ifdef
to enable never showing the keyboard controller as disabled,
which seems to cause bugs at least with some Linux kernels.
Remove keyboard controller IO regions from PS/2 mouse device
as e.g. Linux infers them from the keyboard controller device.
Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO
to appear as child of the root device.
devtree.asl then needs to be included at a reasonable position inside
the \_SB device tree.
Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/298
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a method WAKS to devtree.asl which returns the wake-up source register
to simplify retrieving the wake source e.g. in \_WAK.
Change-Id: Ia258f8fc9ff79b18391c55464da73863889e2255
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/297
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Correct a typo in devtree.asl which causes AML processors to fail executing
the DSDT with AE_NO_MEMORY or (in case of acpiexec) Divide By Zero.
Also removes an superfluous item in the register IndexField and removes
unneccessary _PR0 definitions which could confuse AML processors.
Change-Id: I02cb9ce4e8f2101cfff8cec4abba7e070fd66364
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/296
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
A mainboard may require configuration of the superio pins to fully
support some features. Things like A20# gate, leds, fans, infra-red
and bootstrap jumpers may be configured and controlled through the
logical PME device.
Change-Id: I6e77ff0295806ba3dff339013f73d99c2961388f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a ACPI Source Language snippet to superio/w83627hf which maps the
SuperIO and most of the logical devices to PnP devices, exposing
configuration options and chip power management to the OS.
Written using the Winbond W83627HF/F datasheet.
Change-Id: I1108d29b341ef78fe7f1e574f98b680aada39daf
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/223
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
only the serial port is tested, keyboard/mouse are gonna
to be tested later, it may also need some more patches
to make it work completely.
Change-Id: Ie9464d01c5d5760ebc800b3cd15a4ab2bad2e09f
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/204
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.
Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.
Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
See discussion at
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html
config->com1, devicetree.cb cleanup and init_uart8250() removal
will follow once this patch is comitted
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Updated to drop com1, com2.... from config structure and devicetree.cb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
superiotool.
WPCM450 is more like an EC. SuperIO is just a part of multi-features.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Instead of enable the device the device gets disabled. However after some time the serial line gets back, most likely some "enable resources" might fix it.
I'm attaching patch which somewhat fixes the problem and changes the function to look same in all superio code. Some boards even did not convert the dev->enabled to 0,1 values.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6373 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6349 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Corrects "index 98 has no mask" error at runtime.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This adds support for the NSC PC87392 Super I/O. It is used in Lenovo
Docking Stations as Super I/O chip.
v2 because of:
- skip some empty files
- missing newlines in Kconfig and Makefile.inc
- add the Kconfig option in sorted order
Thanks to idwer on irc for pointing that out.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch adds support for NSC PC87382 Super I/O. It is used in many
Lenovo Notebooks as Docking LPC Switch.
v2 because of:
- Skip some empty files
- Fix newlines in Kconfig and Makefile.inc
- chip.h missed uart8250.h include
- add the Kconfig option in sorted order
Thanks to idwer on irc for pointing that out.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Mostly done according to initial file creator.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
W83627DHG:
- Add proper "virtual LDN" handling for the LDNs that need it (i.e., those
that don't have their "enable" bit in bit 0 of the 0x30 register).
- Fix various I/O masks in the pnp_dev_info[] array as per
datasheet. Add missing PNP_IRQ0 to the W83627DHG_ACPI LDN.
W83627EHG:
- Similar to W83627DHG, improve the "virtual LDN" setup a bit (it was
mostly implemented already, though).
- Add missing PNP_IRQ0 to the W83627EHG_ACPI LDN.
Also: Fix up devicetree.cb of all boards using W83627DHG/W83627EHG to adapt
for the virtual LDNs.
include/device/pnp.h: Add comment that 'function' (which refers to the
LDN and should probably be renamed later) has to be at least 16 bits
wide. In theory LDNs could use u8, but due to the virtual LDN info being
encoded in the "high byte" of 'function' it must be at least u16.
asrock/939a785gmh/romstage.c: Drop unused GPIO6_DEV.
ibase/mb899/romstage.c: Use DUMMY_DEV instead of a specific LDN (serial
port 1 in this case) to avoid confusion. The global registers
manipulated there are accessible from any LDN.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6140 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The only difference is that the "G" version is in a Pb-free package, which
is not relevant from a programmer's view.
We keep W83627THG (and drop W83627THF) because:
- The W83627THF had a CIR device / LDN which doesn't actually exist.
- The W83627THF had no GPIO2, GPIO3 LDNs (were commented out).
- The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards.
This also fixes an issue on MSI MS7135's devicetree.cb:
device pnp 4e.6 off end # XXX keep allocator happy
The line above can be (and is) removed, as it was only needed due to the
incorrect CIR LDN in the W83627THF.
In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Random coding style, whitespace and cosmetic fixes.
- Consistently use the same spacing and 4-hexdigit port number format
in the pnp_dev_info[] arrays.
- Drop dead/unused code and less useful comments.
- Add missing "(C)" characters and copyright years.
- Shorten and simplify some code snippets.
- Use u8/u16/etc. everywhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The pc_keyboard_init() function no longer takes any base addresses
since r5152 (passed in via res0/res1 variables previously), so drop them.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6063 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- i3100_early_serial.c:
- Split out enter/exit functions as the other Super I/Os do.
- Make i3100_enable_serial() take a device_t as usual, and convert
it to use the standard pnp_* function instead of open-coding
the same functionality by hand.
- Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
we do the same in various other Super I/Os, e.g. ITE ones.
- Add some #defines for register / bit values and some comments.
- Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
marked as "READ ONLY, WRITES IGNORED" in the datasheet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace, coding style, and typo fixes.
- Drop unused/obsolete "#config chip.h".
- Use u8/u16/etc. everywhere.
- Use pnp_read_config()/pnp_write_config() instead of open-coding them.
- Use pnp_set_logical_device() instead of open-coding it.
- W83627EHG: Fix incorrect enable_hwm_smbus() code comment.
- Use ARRAY_SIZE.
- w83627hf/superio.c: w83627hf_16_bit_addr_qual(): Bugfix, the code was using
'dev->path.pnp.port >> 8' as config port, which is incorrect in superio.c
(which has a "real" device_t struct, in contrast to *_early_serial.c which
uses "unsigned" as device_t where 'dev >> 8' is required).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6057 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- it8661f_enable_serial() is now in the usual format, using pnp_* functions.
- Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode().
- Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz.
- Factor out it8661f_enable_logical_devices(), might not be needed though.
We leave it here until it's confirmed on hardware that it's not needed.
- Move some #defines to it8661f.h.
- Drop no longer used it8661f_sio_write().
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Drop some of the less useful / outdated / duplicated comments.
- Simplify and streamline some code to look like the other Super I/Os.
- Use u8/16/etc. everywhere.
- ITE IT8718F: Add missing GPIO LDN.
- Add missing braces around SIO_DATA #defines, potential bug even.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6047 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- VIA VT1211:
- Add missing LDNs and respective code to handle them.
- Add some TODOs for other stuff that needs fixing.
- Use VT1211_SP1 instead of hardcoding the LDN number (2).
- Fixup pnp_dev_info[] as per datasheet, but some TODOs remain.
- Various coding style fixes and changes to u8/u16/etc.
- Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6030 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
"To enable configuration, the entry key 0x87 must be written to
the index port"
"
-o 4e 87
-o 4e 87 (enable configuration)
-o 4e aa (disable configuration)
"
This piece of text appears in most of the datasheet of fintek superio.
It doesnt say it quite clear, but it seems that the 0x87 should
be written twice. I tried on f81865, which is not in the coreboot tree
yet. If the 0x87 is only written once, you can only R/W the index/data
port once. All the subsequent RW will fail. Writing twice will be ok.
Plus, in the superiotool, the function enter_conf_mode_winbond_fintek_ite_8787
also write 8787.
The fintek superio chips seem to enable the UART automatically when the
power is on. So I didnt find it failed to access.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Drop commented out "config chip.h" and a duplicate link to a datasheet.
- F71805F -> F71805F/FG, to mention all variants.
- Use u8/u16/ etc. everywhere.
- Add a missing (C) line.
- Fix up a bunch of pnp_dev_info[] structs according to the datasheets.
- Fintek F71889: Drop res1/PNP_IO1 from KBC, there's no 0x62/0x63 register
pair on this Super I/O.
- Fintek F71863FG: This Super I/O _does_ have a keyboard/mouse LDN, add the
respective code in superio.c. Also: Add missing LDNs to f71863fg.h.
- i3100: Add some more comments and datasheet infos.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6020 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Untested, but should work mostly (even though some TODOs remain).
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6017 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Original patch was
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Updates to accomodate changes in coreboot are
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
notices. Getting it into the tree so people can get to it.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After lots of testing, the SuperIO LDN 7, register 0xEF is the key to the
problem. This patch adds a function which stops dual bios mainboards from
rebooting, when called.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This fixes serial console on GIGABYTE GA-6BXE.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c files in mainboards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
files using prototypes is the way to go I think. It would make our life a lot
easier should we ever decide to move (some mainboards) over to not #include
all those .c files in romstage.c anymore.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.
The 1000 ways of how the AMD code waits for the cores to be started up
are a real pain for the brain.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rename amd64_main to stage1_main..
copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only some assembler files still have \r\n ... Can we move that part to C
completely?
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Edward O'Callaghan