No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)
Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/658
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree ck804-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/657
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix issues reported by new lint test.
Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
No in-tree cx700-using board has it not selected, so move
selection from boards to northbridge.
Change-Id: Ifa79954a48cf99b5f7e49960eafce805401e571c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree 82801dx-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: I69671cb6411a6cd9c791059ae9546dff3aff702c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/655
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Dinar mainboard is an AMD evaluation board for
Orochi Platform family15 model 00-0f processor.
The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
16 cores InterLagos Opteron processor are supported.
Windows 7 are verified on this platform.
Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/564
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is based on the commit 94fa3db366
(AMD Mahogany Fam10 ACPI table fixes.)
Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/636
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans,
they are controled by a separate W83795G Hardware Monitor chip.
This patch adds Nuvoton W83795G/ADG HWM support.
Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/569
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
1. Supermicro H8QGI mainboard update to support both family10 Revison D
processor and family15 model 00-0fh processor in one binary image.
2. RD890/SR56X0 IO hub CIMX wrapper support.
3. SP5100/SB700 southbridge CIMX wrapper support.
Both 8 cores and 16 Cores InterLagos Opteron Processor are
tested on this platform.
Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.
Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/567
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
1. Stop include c file.
2. W83627dhg Pin 89, Pin 90 are multi function pins,
add support to select them to I2C function.
Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/565
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.
Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.
Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Driver components are conditionally included in the build using the
Kconfig options.
Change-Id: I05417ee263a5b82e947600482dfb68f7a3f52d58
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Pcie device connected to Hudson/sb800 southbridge GPP training can works,
by applying this mainbaind specific GPIO PCIE De-Assert setting.
Change-Id: I563b2e6354a958a28f5d0162e7a4d60aa437fb9b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/543
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.
Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Fix ordering of power/reset/undock procedure to prevent
crashes seen with the old code. Also call dlpc_init()
only once.
Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/597
Tested-by: build bot (Jenkins)
This makes resume from S3 work.
Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/591
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html
On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.
On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.
The SLFRCS register is documented on page 197 of
Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006
which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).
The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.
Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.
Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.
This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.
Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Value required to get 115200 is actually 0, not 5.
Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/592
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Coming changes to abuild require that VENDOR_ and BOARD_ names have
common suffixes.
Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Make changes MPtable to match ACPI tables.
Change-Id: I387f301370582fcb5e0d348d793333a919d2f373
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.
Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.
Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This line was unnecessary and was duplicated on several mainboards.
Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/541
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The #define REQUIRED_CALLOUTS is no longer used on these platforms.
Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.
At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.
Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.
The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.
The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.
Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes
Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Added the default ID to the mainboard Kconfig.
Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.
Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.
This fixes a small copypasta.
This is an updated patch set.
Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This pulls it all together and adds the real board-specific code.
Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write
Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53
Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.
Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Without that fix the linux kernel cannot change the frequency
of the CPUs with cpufreq.
Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This mainboard is very similar to the M4A785-M, but it has
DDR3 instead of DDR2.
That's why most of the code was copied or included from
the m4a785-m directory
Notable changes between the two mainboards include:
* the selection of the last microcode (mc_patch_010000b6.h)
which made it pass the CPU init.
* the selection of DDR3 which made it pass the ram init
This change was tested with the Trisquel 5.0 GNU/Linux distribution
which uses the linux-libre version 2.6.38-12-generic
The mainboard boots fine, however some special care is required for
the onboard sound CODEC, and the onboard video chip:
* the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
is the same than the ASUS M4A785-M mainboard:
It causes a flood of interupts which prevents booting
* The internal video chip currently requires pci=nocrs, else
the graphics are frozen as soon as the radeon module loads,
and dmesg would print the following(the card only has 256M,
and the mainboard was equiped with 2G of RAM):
[ 3.674762] [drm] radeon: 3584M of VRAM memory ready
[ 3.679863] [drm] radeon: 512M of GTT memory ready.
instead of :
[ 45.876088] [drm] radeon: 256M of VRAM memory ready
[ 45.876089] [drm] radeon: 512M of GTT memory ready.
* The screen(both VGA and HDMI) flickers at high resolution
* Sometimes the computer freeze while changing the resolution
(even the serial console stops responding)
The following peripherals were tested:
* The ath9k PCI wireless card was tested
* The SATA hard disk works fine
* the USB keyboard and mouse work fine
* htop see 2 cores
* serial port works under coreboot and GNU/Linux
* power off and reboot works
CPU frequency cannot be changed yet, this is addressed
in a new commit.
More detail are available here:
http://www.coreboot.org/ASUS_M4A785T-M
dmesg is available here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
The mailing list thread on the graphic problem is here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.
Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
AMD unionstation Reference Design Kit is Designed for hd settop box application.
This platform using family14 APU, SB800 southbridge.
Vgabios is required, can download vgabios from AMD NDA website.
Verified Feature:
HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
optical fiber digital audio output.
Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
AMD southstation Reference Design Kit is designed for NAS application.
This platform using family14 RevC0 processor, SB850 southbridge.
Vgabios and Promise RAID Option ROM is required for hardware RAID support,
can retrieve from the AMD NDA website.
Verified feature:
HDMI, LAN, usb and mini-pcie slot.
RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.
Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Code style fixes for the hp/dl145_g1 system board code.
Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Using RAMINIT_SYSINFO should be beneficial for this platform.
It is also more clean/safe to put data in struct mb_sysconf_t.
It's more consistent with other MB's and I've tested it
thoroughly on my DL145.
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
Reviewed-on: http://review.coreboot.org/236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).
Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No romstage is supposed to use usbdebug functions/defines
directly, so remove all those includes. The usb code is now
called and setup from console code.
Change-Id: I9b1120d96f5993303d6b302accc86e14a91f7a9f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/354
Tested-by: build bot (Jenkins)
We added some new flag for certain AMD boards after support for
this board was submitted. Also integrate the mptable refactorings
that happened in the meantime.
Change-Id: I50cf50f343a740832fd1a14a2a1ef5b903315675
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/353
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
it's a AMD 880+800 mainboard. I port the code
based on the AMD reference code.
update: 1.use CIMX instead of pmio
2.fix some whitespace
3.fix subsystemid of devicetree.cb
Change-Id: I9725ccdbb25365c4007621318efee80b131fec29
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/205
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Linux 2.4 is happier that way
Change-Id: I016609ae1e004ec856e8223893352dcdd061b291
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/346
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
called from console code, no need to call it here.
Change-Id: I4c34f89c82cc2478db8de4e98584e69d7ab0ca82
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/350
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Linux 2.6.11 seems to require a certain order in CPUs listed in mptable,
so enforce it. This was only done on arima/hdama, but now is generic.
Unfortunately this is somewhat slow.
Change-Id: I85715ebae8a009cb816bc9ffd6372708f246bf66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/280
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Used by power management code to enable Cx powersaving modes.
Change-Id: I02c6b10762245bc48f21a341286236e203421de0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/322
Tested-by: build bot (Jenkins)
It is safe to enable this setting on these Boards.
Change-Id: Iaa7377117743d18a95c496c25abf9fb4a1b20ad9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
muting is handled by h8 code, no need to do it here.
Change-Id: I3f152e99f30701cd032b03105cbe3ae778865305
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.
Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Those modules have basically the same Super I/O capabilities as
the Docking station. Unfortunately, the Super I/O in the module
shares the same I/O address as the Docking station, so we're not
allowed to connect the LPC Docking Bus if such a module is present.
To be able to detect this device and use it as early console for
coreboot, we have to initialize the GPIO Controller before, as
this device is detected via GPIO06.
Change-Id: If7c38bb6797f76cf28f09f3614ab9a33878571fb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/282
Tested-by: build bot (Jenkins)
This makes the power_on_after_fail NVRAM option work correctly.
Change-Id: I96f05f82d7f133b343cf8d4ef09db50a3db7a83d
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/292
Tested-by: build bot (Jenkins)
After a lot of experimentation this commit improves some hardware
features that were not recognized or incorrectly configured before.
The only thing not tested is SCSI-option board (I dont have one).
Misleading errors in comments have been corrected.
(Note BTW that the DL145 G1 mainboard is identical to AMD Serenade
which was supported in early versions of coreboot but was dropped
for some reason.)
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ibbd97fafad22196b1e18d0b257731490339f113e
Reviewed-on: http://review.coreboot.org/237
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
- move int15 handler out of the generic code into the mainboard directories
of those mainboards that actually use it.
- move vbe headers to vbe.h
- move function prototypes used in native oprom code to x86.h
Change-Id: Idfff5e804ea328f7b5feebac72497c97329320ee
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/255
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
That function broke SMP on Linux 2.4, now it works.
Change-Id: I4ddd25fef57bed64877959ca96cca68170042bca
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Each variable is essentially unused or incorrect.
Change-Id: I4d2a10c9b45306ac6e6026a31765d3b912fd855c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/242
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.
Coccinelle script:
@@
identifier mc;
@@
(
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
|
-mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
-mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-return smp_next_mpe_entry(mc);
+return mptable_finalize(mc);
)
Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
We copied pretty much the same code for generating mptable entries for
local interrupts (with some notable exceptions).
This change moves these lines into a generic function "mptable_lintsrc"
and makes use of it in many places.
The remaining uses of smp_write_lintsrc should be reviewed and replaced
by mptable_lintsrc calls where possible, and smp_write_lintsrc made static.
This patch was generated using Coccinelle:
@@
expression mc;
expression isa_bus;
@@
-smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, isa_bus);
@@
expression mc;
expression isa_bus;
@@
-smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x0);
-smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, isa_bus, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, isa_bus);
@m@
identifier mc;
expression BUS;
@@
-#define IO_LOCAL_INT(type, intr, apicid, pin) smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, BUS, (intr), (apicid), (pin));
...
-IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
+mptable_lintsrc(mc, BUS);
Change-Id: I97421f820cd039f5fd753cb0da5c1cca68819bb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/244
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Use the SSDT autogen infrastructure to support the automatic reserved resources,
automatic P-state generation and automatic _CRS PCI0 method.
Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
So the missing sb800 USB3 devicees was add to the mainboard devicetree.
Because of no physical usb connector connected to USB3, the USB3 device setting was off.
Change-Id: If060ccb43df7fbe88bafc61e9e600a9120575437
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/232
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/230
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.
Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
LXBIOS and LXB-DSDT are not used in other parts of the tree.
Make names consistent across the tree.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I91caeac09fd2401a36e53bd061d249b236a48e43
Reviewed-on: http://review.coreboot.org/224
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Change-Id: Ic960fe09fbed2c8a31c7c9ac2c54f6c88efebed3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/219
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
Tested-by: build bot (Jenkins)
Change-Id: Ibd87422680350c112eabe1bb73b237031c3e9d6b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/220
Tested-by: build bot (Jenkins)
Reviewed-by: Frank Vibrans III <frank.vibrans@amd.com>
These are the changes for the AMD Persimmon mainboard
required to support the update of the AMD Family 14
cpu to rev C0. There are many warning fixes; the agesa-
wrapper.c file has been changed to fix the amdinitlate
and amdlaterunaptask routines, and more.
Change-Id: I6de43379a2819cea5169db5f21d4841f9a4942a7
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/137
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
These changes update the Inagua platform. The changes
include modifying the Kconfig to suggest video bios
and ahci rom implementations, changing the dimm spd
code to use the correct bus addresses, cleaning up the
makefile a bit, and fixing a duplicate definition
warning associated with the BIOS_SIZE value.
Change-Id: Idab88dda48f08877dbbd2de3136bdf0e54e31247
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/136
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.
Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This updates the E350m1 Agesa wrapper code to fix an
issue with AmdLateRunApTask. It now passes the function
parameter through to the Agesa routine. There is also
a change to the platform_cfg.h file that makes the
definition of BIOS_SIZE dependent on whether or not
it was defined earlier.
Change-Id: I19942c7d3ecd229a13ef0a69fa7e5b1ea0b909bf
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/139
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.
Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238: acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239: printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);
Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Disable bus 0 dev 3 PCI bridge, ma78gm-us2h does not have this slot.
Change-Id: Ia355ee385fd0f37793b4bdf1815c033670823eaa
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/187
Tested-by: build bot (Jenkins)
Remove dead code, copy and pasted from
tilapia's mainboard.c file into various
asus mainboard.c files
Change-Id: Ic715ccaad8ac0210401d4a99ecb11e943f6afe58
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The nuvoton WPCM450 code is compiled for all boards regardless of
whether or not they use it. Compile it only for boards needing it.
Change-Id: Iaf4cf2c479eb3238863f0771be799f02a8cc3421
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/129
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Change-Id: I64a74d3dc0ea2d006ed4b25657d531fb243c2993
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/140
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: Ib6cd82badeb6401e065ee14c2a04c78f61a87dd4
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/130
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.
Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This set adds support for the SuperMicro H8QGI mainboard.
It is a publicly available 4 socket board using AMD Family
10 cpus and AMD SR5650 and SB700 bridges.
Change-Id: I196704f79db4c45382559c5ee0619dc8d96ff140
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/108
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
We use LDTSTOP# to trigger the FID/VID change on K8M890, because the
FID/VID SMAF is blocked by not yet configured internal VGA.
The memory controller is enabled later, nor the workaround makes any
harm to non-affected CPUs.
This update unbreaks compilation by declaring the tmp variable.
Change-Id: Icf5d126b8c8cd9ece6af41d3129315a777c8cef2
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/69
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.
Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Finally the SMI routines are in good shape on AMD, lets enable this and later
implement ACPI on/off SMI commands.
Change-Id: I9848a7be908780353eead30c16fd2df8ea48f77e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/83
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
ec byte 0x03, bit 2 seems to be only used on the X60s for USB switch
initialization. Don't touch it on T60.
Change-Id: Icb89a514757a0e06ccea200fde62a778fa8c268e
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/92
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.
From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.
Also tested & working with Linux.
Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.
Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.
Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.
Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.
Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SMM code already makes sure this register is saved and restored,
so we don't have to do it.
Change-Id: I078e1227de4436fba9c5fb3879a564c981cb0f9a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/65
Tested-by: build bot (Jenkins)
If power is unplugged/lost, we should undock the docking station.
The power loss can also be caused by the fact that the user removed
the thinkpad from the docking station without pressing the Undock button/hotkey
first. Without undocking it on this event, the thinkpad LPC switch will still
connect the Docking connector, which causes crashes when docking it again.
Change-Id: I9ed783e491827bde20264868eab2b3a79c232922
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/62
Tested-by: build bot (Jenkins)
EC events 0x50-0x5f are never triggered by the EC. Instead they
can be generated by writing the wanted events to register 0x2a.
Change-Id: Ifd7ce991ee094cb16e8425ed670b6b45cffe3907
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/61
Tested-by: build bot (Jenkins)
We missed a few bits, i.e the battery and some hotkey events.
Change-Id: Ia5561532f421eb3b40225301f0af639112abc3cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/60
Tested-by: build bot (Jenkins)
Committing Scott's e350m1 changes (svn r6585):
Move SB800 clock init earlier,
Fixes problem where initial serial port output is garbled.
Change-Id: If05aa37726b962e8994ee69bf1882fcfae56aa19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/32
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.
Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Requires Scott Duplichan's patch for NIC support.
Enables required PCIe port for USB3 - does not interfere
with normal operations on non-USB3 model.
Change-Id: I451bb1b4f799d6485e75fa949933e25e821b65f9
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/45
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
