Commit graph

5672 commits

Author SHA1 Message Date
Arthur Heymans
5db043f0d6 apple/imac52: add mainboard
Add Imac5,2 based on macbook2,1 port.

Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-02 19:06:55 +02:00
Nico Huber
a90c7859d9 mb/kontron/ktqm77: Let suspend LED flash slowly in S3/S4
Change-Id: Idb37abea01831631aadba66ecd42bc7df03aa857
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16727
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 22:30:55 +02:00
Antonello Dettori
97c460a2d1 biostar/am1ml: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/biostar/am1ml.

Change-Id: Iba2fff5617c62152355b54e446517ad36108aa31
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16688
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-01 17:38:50 +02:00
Sumeet Pawnikar
62a193899c mainboard/google/reef: Update DPTF policy temp. values for CPU
This patch increases the CPU specific passive temp. trip point
and critical temp. trip point value for DPTF policy.

BUG=chrome-os-partner:57903
TEST=Built, booted on reef and verified this passive and
critical temp. trip points with heavy workload.

Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16766
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
2016-10-01 17:38:16 +02:00
Aaron Durbin
c6452bb8c5 mainboard/google/reef: unconditionally set MAINBOARD_FAMILY
For all mainboard variants use the "Google_Reef" family by default
which is populated in SMBIOS tables. A variant can provide their own
value if needed, but "Google_Reef" can reside as the family without
having to add conditions for each variant when MAINBOARD_FAMILY
have to be overridden.

BUG=chrome-os-partner:56677

Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16813
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-10-01 17:37:43 +02:00
Elyes HAOUAS
08449eb583 mainboard/amd/serengeti_cheetah: Use tabs for indents
Change-Id: If47f0c072399fe8291bd8e41920d828f649ec49f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16817
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-10-01 09:11:10 +02:00
Elyes HAOUAS
75b2237473 mainboard/*/*/*/usb.asl: Use tabs for indents
Change-Id: Id46a0c4ca59dc7224c2eedd674ea3a5486509de1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16824
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:38:34 +02:00
Elyes HAOUAS
728273eebf mainboard/gigabyte/m57sli/romstage.c: Use tabs for indents
Change-Id: Ib439e5d96543790d17934bd477af62d39a5958b6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16815
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:47 +02:00
Elyes HAOUAS
b4d8257dff mainboard/jetway/j7f2: Use tabs for indents
Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16825
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:24 +02:00
Elyes HAOUAS
c3d490cc24 mainboard/winent/mb6047: Use tabs for indents
Change-Id: Iaf5ad440cfc2bbe08ea9f6c545e5e314645c8893
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16823
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:35:03 +02:00
Elyes HAOUAS
bbcb8bc971 mainboard/kontron/ktqm77: Use tabs for indents
Change-Id: I3040dc9a2534a77087805ee61c4f91d1bdb4d509
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16822
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:34:45 +02:00
Elyes HAOUAS
075ff736f6 mainboard/digitallogic/msm800sev: Use tabs for indents
Change-Id: I39ad6606869f059b2ef0c45d6741b844b3791655
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16821
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:34:28 +02:00
Elyes HAOUAS
dae8fe747c mainboard/gigabyte/ga-b75m-d3v: Use tabs for indents
Change-Id: I36011719f79da4a9ab2aaeb92ffb0506b4373143
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16816
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:33:51 +02:00
Elyes HAOUAS
cb6b120e93 mainboard/gigabyte/ga-b75m-d3h: Use tabs for indents
Change-Id: I038e5cea654d1760ddb2c403c651d8f75e021251
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:33:28 +02:00
Elyes HAOUAS
cf81bd3002 mainboard/samsung/stumpy: Use tabs for indents
Change-Id: I1ffee53a04df6874f658feb3d6ce7d5c7b922837
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16818
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:33:16 +02:00
Elyes HAOUAS
117fd8d645 mainboard/kontron/986lcd-m: Use tabs for indents
Change-Id: Ibeb0da2f75b4aec32f5238e5634bc1f1d8220b84
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16820
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-01 08:32:39 +02:00
Martin Roth
80fa9d899c google/reef: Fix default values in Kconfig
These default values weren't being set with the default
keyword so were ending up with different values.

from the default generated config file before this change:
CONFIG_DRIVER_TPM_I2C_BUS=0x9
CONFIG_DRIVER_TPM_I2C_ADDR=0x2
CONFIG_DRIVER_TPM_I2C_IRQ=-1

Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30 23:57:12 +02:00
Martin Roth
311fb696cf Kconfig: Prefix hex defaults with 0x
Because these variables had "non-hexidecimal" defaults, they
were updated by kconfig when writing defconfig files.

Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16827
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-30 23:57:02 +02:00
Elyes HAOUAS
48a0129d97 mainboard/google/stout/romstage.c: Use tabs for indents
Change-Id: I2402648b8c0b9dcc730ce7f099e1e4ccef3b79fc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-30 20:27:55 +02:00
Arthur Heymans
0b9ecb5831 mb/intel/d945gclf: Allow use of native graphic init
Add PCI device id to native graphic init and add the Native graphic init
option in Kconfig.

Change-Id: I136122daef70547830bcc87f568406be7162461f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30 17:12:36 +02:00
Lee Leahy
31f5c130b1 mainboard/intel/galileo: Make FSP 2.0 the default
Switch from FSP 1.1 to FSP 2.0 as the default build.

BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2

Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16810
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30 01:17:41 +02:00
Lee Leahy
e1654235fd mainboard/intel/quark: Add FSP selection values
Add Kconfig values to select the FSP setup:
* FSP version: 1.1 or 2.0
* Implementation: Subroutine or SEC/PEI core based
* Build type: DEBUG or RELEASE
* Enable all debugging for FSP
* Remove USE_FSP1_1 and USE_FSP2_0

Look for include files in vendorcode/intel/fsp/fsp???/quark

BRANCH=none
BUG=None
TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2

Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-30 01:15:44 +02:00
Elyes HAOUAS
127b5d1270 mainboard/asus/kfsn4-dre_k8/romstage.c: Use tabs for indents
Change-Id: If6b36ebef49dd2733d272f990bb7c6623d4ab1b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16785
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29 23:52:13 +02:00
Elyes HAOUAS
0c31a677b0 mainboard/via/epia-m850/romstage.c: Remove unnecessary whitespace
Change-Id: Ic5359f794c64a9a67ec9e059af337a65073baff4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16784
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
2016-09-29 23:51:48 +02:00
Elyes HAOUAS
aabd7203a8 mainboard/lanner/em8510: Use tabs for indents
Change-Id: Ib6191c590144438d7d9d6772d792a83e92d5516a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29 23:51:19 +02:00
Elyes HAOUAS
0e505f1bfe mainboard/iwill/dk8_htx: Use tabs for indents
Change-Id: I303270a45171dda88b7661e3797fd3724e3b055f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29 23:51:01 +02:00
Elyes HAOUAS
129c26e5ea mainboard/gigabyte/ga_2761gxdk: Use tabs for indents
Change-Id: Ie752fe0a74acd4b79711596e56fc5ebf83884a0d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16779
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-29 19:23:26 +02:00
Yuichi Ito
4951677b16 mainboard/elmex: Add new board pcm205401
pcm205401 is CPU board equipped with T40R of AMD. We used SeaBIOS and
Windows Embedded Standard 7 to test pcm205401.

In comparison to pcm205400, only VGA PCI ID is changed and board
identifier strings in SMBIOS / DMI.

Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155
Signed-off-by: Yuichi Ito <yui.corebt@gmail.com>
Reviewed-on: https://review.coreboot.org/15930
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29 15:56:58 +02:00
Yuichi Ito
c4ddfe45a8 mainboard/elmex: Add new board pcm205400
pcm205400 is CPU board equipped with T56N of AMD. We used SeaBIOS and
Windows Embedded Standard 7 to test pcm205400. I disable the port5,
6, and 7 of the PCI-e in elmex/pcm205400/PlatformGnbPcieComplex.h.
I disable the audio capabilities at the 236th line of
elmex/pcm205400/platform_cfg.h. Coding style is modified to avoid the
error and warning that occur when I commit.

Change-Id: I77cb76903fe3c1b500a306426f5399936382695b
Signed-off-by: Yuichi Ito <yui.corebt@gmail.com>
Reviewed-on: https://review.coreboot.org/15929
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29 15:56:39 +02:00
Yuichi Ito
b31c3d1b92 src/mainboard: Add vendor ELMEX with a board
Add board with amd/persimmon as template.

Change-Id: I263b54e0f49b6f1ba730c7f87de41f990ba8fe67
Signed-off-by: Yuichi Ito <yui.corebt@gmail.com>
Reviewed-on: https://review.coreboot.org/15926
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-09-29 15:55:15 +02:00
Duncan Laurie
6d16e1ff87 google/reef: Mark touchpad and touchscreen as probed devices
Add the 'probed' flag to the touchpad and touchscreen devices so they
are probed by the kernel before being loaded, in case they do not exist
or are replaced with another vendor.

BUG=chrome-os-partner:57686

Change-Id: I0a61964e6874cd99fab0c21fa404a43548fc8ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-28 22:17:57 +02:00
Elyes HAOUAS
eeabb75e8c mainboard/amd/rumba: Use tabs for indents
Change-Id: I005e607faa2a6c527584ba9cdcad92f4517a15e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16778
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:15:40 +02:00
Elyes HAOUAS
39aa6309ba mainboard/supermicro/h8dmr/romstage.c: Use tabs for indents
Change-Id: I008ccc5fa9d96e52ee59a4562d81e4f7c1d1a6ac
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:15:04 +02:00
Elyes HAOUAS
6da74da345 mainboard/sunw/ultra40/romstage.c: Use tabs for indents
Change-Id: I9b7be74625dfcb6317a1cdb61d0dc77d7f359462
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16776
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:13:58 +02:00
Elyes HAOUAS
8f372d031b mainboard/technexion/tim5690: Use tabs for indents
Change-Id: Icd1f145b3575c6d95dacceb9c0426fbdedcdd686
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16777
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:11:54 +02:00
Elyes HAOUAS
c6317e0c95 mainboard/supermicro/h8qme_fam10/romstage.c: Use tabs for indents
Change-Id: I6ca564294ff3d8eaeae21c0e2c008401aa3f32ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16774
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:09:32 +02:00
Elyes HAOUAS
497b5fe87a mainboard/asus/dsbf/romstage.c: Use tabs for indents
Change-Id: I74d4ef76b8166c8567b1b855c6bc963b4312df77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16773
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-28 22:09:06 +02:00
Elyes HAOUAS
499ccbe41c mainboard/intel/emeraldlake2/gpio.c: Use tabs for indents
Change-Id: I369c2063a5e57d1fd33d3c6bf7c715c22970fc32
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16772
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:08:24 +02:00
Elyes HAOUAS
1a657e9334 mainboard/intel/eagleheights/debug.c: Use tabs for indents
Change-Id: I4d2d876d48e018c247e7f365f7c237a4d8ced332
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16771
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:07:59 +02:00
Elyes HAOUAS
d9ceae5f20 mainboard/broadcom/blast: Use tabs for indents
Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16745
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-28 22:07:19 +02:00
Elyes HAOUAS
a6b863a2bc mainboard/msi/ms9185/resourcemap.c: Use tabs for indents
Change-Id: I30b5830442da65ae3ddd35e8bca67795c34e9020
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16737
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-27 20:31:18 +02:00
Elyes HAOUAS
99a92ac722 mainboard/msi/ms9185/romstage: Use tabs for indents
Change-Id: I101462105da31654032ac7e6abd3f9423ad7a7ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16736
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27 20:30:46 +02:00
Elyes HAOUAS
bf97ca42cd mainboard/msi/ms9185/mb_sysconf.h: Use tabs for indents
Change-Id: Ib2ab95b26c3bb1cbd58aafb1fafd1b285d6a5ba8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16738
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-27 16:37:37 +02:00
Aaron Durbin
91fa9d7696 mainboards,ec: provide common declaration for mainboard_ec_init()
Add a header file to provide common declarations that the
mainboards can use regarding EC init.

BUG=chrome-os-partner:56677

Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16734
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
2016-09-26 23:53:12 +02:00
Aaron Durbin
59cf5028a8 mainboards/google/reef: use chromeec's ASL lid switch implementation
Defer to the lid switch implementation provided by the chromeec.

BUG=chrome-os-partner:56677

Change-Id: Ida451dc29c8cf55fb88015e48a9e0bca3740f645
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16733
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-09-26 23:52:53 +02:00
Aaron Durbin
c64a6d63ed soc/intel/apollolake: provide power button ACPI device
Instead of having each mainboard provide the power button,
uncondtionally provide the power button ACPI device on behalf
of each mainboard.

BUG=chrome-os-partner:56677

Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16731
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-26 23:52:32 +02:00
Elyes HAOUAS
b87a734771 mainboard/*/*/dsdt.asl: Use tabs for indents
Change-Id: Idef587d8261784e916e8d50f4336cbcfca39b9b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16730
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:38:46 +02:00
Elyes HAOUAS
8da96e57c8 mainboard/*/*/mptable.c: Improve code formatting
Change-Id: I341293cd334d6d465636db7e81400230d61bc693
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16723
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:32:21 +02:00
Elyes HAOUAS
f4df9d1156 mainboard/*/*/irq_tables.c: Use tabs for indents
Change-Id: Idc29373cb01f4304d22ae315812bd40f0aaa94c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:22:39 +02:00
Elyes HAOUAS
57a3cd21f1 mainboard/lippert: Use tabs for indents
Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16686
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-26 13:22:23 +02:00
Andrey Petrov
c2586db790 intel/amenia: Remove Amenia mainboard
The mainboard is not being worked on anymore, not available outside of
Intel and thus has litle practical use. Remove mainboard code completely.

Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16725
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-24 04:24:54 +02:00
Elyes HAOUAS
d4c89e40c0 mainboard/lippert/frontrunner-af: Use tabs for indents
Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:46:04 +02:00
Elyes HAOUAS
62d4b0062b mainboard/lippert/toucan-af: Use tabs for indents
Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16684
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:45:51 +02:00
Elyes HAOUAS
e4cf954f52 mainboard/nvidia/l1_2pvv: Use tabs for indents
Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16687
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-23 20:45:47 +02:00
Patrick Georgi
8aa20193a6 google/enguarde: Adapt to current tree
Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator

Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/16683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-21 16:48:36 +02:00
Matt DeVillier
1ba3432301 google/enguarde: Upstream Lenovo N21 Chromebook
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.

original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]

TEST=built and booted Linux on enguarde with full functionality

blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)

Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 13:59:55 +02:00
Duncan Laurie
401bd31b2d mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage.  The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.

BUG=chrome-os-partner:53336

Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16673
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:47:02 +02:00
Martin Roth
8ea06512e6 Makefiles: update cbfs types from bare numbers to values
These values are found in util/cbfstool/cbfs.h.

Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 09:36:11 +02:00
Elyes HAOUAS
a5aad2ed68 src/mainboard/lenovo-winent: Add space around operators
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:55:12 +02:00
Elyes HAOUAS
531b87ac4e src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:54:45 +02:00
Shunqian Zheng
386f084f97 gru/kevin: Decrease voltage for little cpu 1.5G to 1.15v
In kernel side we set 1.1v for 1.5G, even for coreboot RO,
a higher voltage could be safer, 1.2v now seems too high.

BRANCH=none
BUG=chrome-os-partner:56948
TEST=bootup

Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab
Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/380896
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:52:06 +02:00
Daisuke Nojiri
2b7a6019f2 Veyron: Increase bit-per-pixel to 32
This enhances gradation of some icons on vboot screens.

BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted Jerry

Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166
Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376884
Reviewed-on: https://review.coreboot.org/16581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:51:28 +02:00
Julius Werner
f52288f935 google/gru: Fix up PWM regulator ranges
We did yet another small adjustment to the PWM regulator ranges for
Kevin rev6... this patch reflects that in code. Also rewrite code and
descriptions to indicate that these new ranges are not just for Kevin,
but also planned to be used on Gru rev2 and any future Gru derivatives
(which as I understand it is the plan, right?).

BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted my rev5, for whatever that's worth...

Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9
Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/379921
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16580
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:51:10 +02:00
Daisuke Nojiri
dd6ab34d5b Gru: Increase bit-per-pixel to 32
This enhances gradation of some icons on vboot screens.

BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted kevin-tpm2

Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c
Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376883
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16579
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:50:51 +02:00
Julius Werner
b6bf1ddb91 gru: Add watchdog reset support
This patch adds support to reboot the whole board after a hardware
watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to
Veyron.

From my tests it looks like both SRAM and PMUSRAM get preserved across
warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that
makes it easier to deal with in coreboot (PMUSRAM is currently not
mapped as cached, so we don't need to worry about flushing the results
back before reboot).

BRANCH=None
BUG=chrome-os-partner:56600
TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30
seconds. Confirm that system reboots correctly without entering recovery
and we get a HW watchdog event in the eventlog.

Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098
Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/375562
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16578
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 21:50:39 +02:00
Elyes HAOUAS
6350a2e43f src/mainboard/a-trend - emulation: Add space around operators
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-09-20 19:06:28 +02:00
Duncan Laurie
9d4b11c26a Revert "mainboard/google/reef: Enable cr50 TPM interrupt"
This reverts commit 24de342438.
2016-09-19 19:19:57 -07:00
Duncan Laurie
24de342438 mainboard/google/reef: Enable cr50 TPM interrupt
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage.  The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.

BUG=chrome-os-partner:53336

Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19 19:05:10 -07:00
Julius Werner
1c8491c3ab gru: Add USB 2.0 PHY tuning for Kevin
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.

BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.

Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck@chromium.org>
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://review.coreboot.org/16265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20 00:32:13 +02:00
Vaibhav Shankar
767009aeab mainboard/google/reef: Configure WLAN as wake source
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.

BUG=chrome-os-partner:56483
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.

Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19 19:33:31 +02:00
Rizwan Qureshi
c33f08b672 kunimitsu: Remove incorrect dereferencing of pointer
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.

Change-Id: I08677976792682cc744ec509dd183eadf5e570a5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19 19:31:32 +02:00
Aaron Durbin
fec0328c5f mainboard/reef: add variant support to ASL code
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.

BUG=chrome-os-partner:56677

Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15 23:33:45 +02:00
Fabian Kunkel
629ca43859 mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3
This patch disables the SataSetMaxGen2 flag.
This flag is a power saving option,
which forces the SATA to GEN2.
Payload SeaBIOS 1.9.1, Lubuntu 16.04, Kernel 4.4.

$ dmesg | grep ahci #before patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
$ dmesg | grep ahci #after patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode

Change-Id: I48361190969e6d38ddb5692f5e54b016b359fbb1
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15906
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15 02:37:37 +02:00
Alexander Couzens
13d880fd37 lenovo: add ps2 spinup timeout to all H8S based boards
The h8s needs around 3s to respond to ps2 commands

Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15 02:34:10 +02:00
Werner Zeh
91bba828fc camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODE
In commit 4f2754c
'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode'
the default operation mode of SERIRQ was changed from continuous to quiet.
Set the mode to continuous for this mainboard to keep the behavior unchanged.

Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15 02:28:57 +02:00
Shaunak Saha
b599919495 google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15 01:20:06 +02:00
Shaunak Saha
563de15b8a intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-09-15 01:19:50 +02:00
Rizwan Qureshi
5ff7390fcd kunimitsu: Add FSP 2.0 support in romstage
Populate mainboard related Memory Init Params i.e, SPD
Rcomp values, DQ and DQs values.

Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16316
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 01:15:27 +02:00
Vaibhav Shankar
db54bb5e3a mainboard/intel/amenia: Configure PERST_0 pin
Configure PERST_0 and assign the pin in devicetree.

BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.

Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 22:20:18 +02:00
Sumeet Pawnikar
7e10c8209b mainboards/apollolake: Set RAPL power limit PL1 value to 12W.
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.

BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.

Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14 22:19:08 +02:00
Vaibhav Shankar
8cdeef1c0d mainboard/google/reef: Configure PERST_0 pin
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.

BUG=chrome-os-partner:55877

Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-09-14 22:18:15 +02:00
Gwendal Grignou
6d8e39127b mainboard/google/reef: add MKBP EC event as SCI event.
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.

BUG=b:27849483
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.

Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13 18:17:54 +02:00
Antonello Dettori
ec4555b96d lenovo/t60: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/lenovo/t60.

The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.

Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16405
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:24:20 +02:00
Antonello Dettori
30d55bf001 mainboard/bcom/winnetp680: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/bcom/winnetp680.

Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:49 +02:00
Antonello Dettori
ef8021cc1b mainboard/gigabyte/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/gigabyte/*.

Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:35 +02:00
Antonello Dettori
837618bf20 mainboard/asus/*: transition away from device_t
Replace the use of the old device_t definition inside
mainboard/asus/*.

Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:16:24 +02:00
Hakim Giydan
e889b19ba0 soc/marvell/mvmap2315: Add DDR driver
This driver is only a prototype driver, real driver
will be integrated at a later time.

Testing: booted successfully.

Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 17:03:53 +02:00
Hakim Giydan
65c7ccc8b1 google/rotor: Add support for the Rotor mainboard
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13 16:56:18 +02:00
Werner Zeh
9d18e330fd siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPC
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.

Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 22:41:45 +02:00
Arthur Heymans
a761fa5ec9 lenovo/t60: add hda_verb.c
This creates a config for the Lenovo T60 sound card based
on values taken from vendor bios
(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16).
The sound card configuration on the vendor bios is the same
as the one on the Lenovo x60.

It improves the default behavior of the sound card:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker

Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12 20:00:40 +02:00
Rizwan Qureshi
06868f8154 kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.

Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:56:09 +02:00
Venkateswarlu Vinjamuri
d2e92e461d mainboard/google/reef: Enable lpss s0ix
This setting enables lpss to power gate in S0ix.

BUG=chrome-os-partner:53876

Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16558
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:28 +02:00
Venkateswarlu Vinjamuri
6584973bdc mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.

Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:49:08 +02:00
Damien Zammit
55a54f662e mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.

Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-09 19:40:34 +02:00
Aaron Durbin
e642b2d1d3 mainboard/google/reef: move devicetree to baseboard
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.

BUG=chrome-os-partner:56677

Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-08 16:24:33 +02:00
Kyösti Mälkki
e0d7e2690f intel/i82801gx 82801ix: Remove OpRegion of SMBus host
Defining this OpRegion for SMBus controller prevents linux kernel
driver i2c-i801 from registering SMBus under sysfs, with following
error in dmesg:

  ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI)

Solution taken from intel/bd82x6x. Worth noting we do not
define ENABLE_SMBUS_METHODS anywhere currently.

Removed remaining reference to HSTS from GETAC P470.

Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16266
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:06:31 +02:00
Arthur Heymans
e8cf4ffbee mb/intel/d945gclf: Disable combined mode to fix SATA
Similarly to 2b2f465fcb
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.

Tested on d945gclf

Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16319
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:23 +02:00
Damien Zammit
93157f6c1c mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPI
With this patch and the previous ones in this set,
PCI express graphics is now working.

01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218
        [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller])

Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16497
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07 23:05:03 +02:00
Venkateswarlu Vinjamuri
e52592078e mainboard/google/reef: Enable audio clock and power gate
Removes S0ix blocker. Sets audio clock gate and power gate
bits when audio not in use. Reduces power in S0.

Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-07 18:37:50 +02:00
Duncan Laurie
c2875872c8 google/reef: Enable I2C TPM
Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.

This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:

Device (TPMI)
{
  Name (_HID, "GOOG0005")  // _HID: Hardware ID
  Name (_UID, Zero)  // _UID: Unique ID
  Name (_DDN, "I2C TPM")  // _DDN: DOS Device Name
  Method (_STA, 0, NotSerialized)  // _STA: Status
  {
    Return (0x0F)
  }

  Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
  {
    I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
                  AddressingMode7Bit, "\\_SB.PCI0.I2C2",
                  0x00, ResourceConsumer)
    Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
    {
      0x00000039
    }
  })
}

Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06 22:58:56 +02:00