Commit Graph

1665 Commits

Author SHA1 Message Date
Stefan Reinauer cecabc19a5 ME/IFD binaries: Implement sane defaults for file paths
Change-Id: I81298aca07c18359e8e4bf5b2d8926d6b45a30c5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10763
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-02 03:01:00 +02:00
Martin Roth 57eff2a192 ifdfake: Add prompts and help for the regions in Kconfig
Update the ifdfake region questions in Kconfig with help descriptions
and prompts to allow values to be entered and not just use pre-defined
default values.

Change-Id: Ifdffadc3d74ec49492c2ded66623a1be6945425f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10649
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:45 +02:00
Martin Roth 775d50828e Intel Firmware Descriptor: Add Lock ME Kconfig question
Add the Kconfig question to allow the user to lock the ME section
using ifdtool.

Change-Id: I46018c3bc9df3e309aa3083d693cbebf00e18062
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:26:21 +02:00
Martin Roth c407cb97bc Move baytrail & fsp_baytrail to the common IFD interface.
- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults.  All the fsp_baytrail
platforms have their own defaults.

Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:21:33 +02:00
Martin Roth c528c2e3e9 Intel Firmware Descriptor Kconfig: remove USES_INTEL_ME
When I added the common IFD Kconfig and Makefile, My thinking was that
I could use this symbol to differentiate between the ME and the TXE,
and to exclude the ME questions from platforms that use the IFD, but
don't use an ME, like Rangeley.  In practice this made things a lot
more complicated and isn't worth it.

Change-Id: I4428744e53c6bb7fc00a4fa4f0aa782c25fc9013
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-02 02:17:27 +02:00
zbao 3ad1f1ca5f amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0
Besides the first five DWORDs, the offsets 0x40 & 0x41
are used to save SPI settings. They should only be 0xFF
for being written.

Other parts in ROMSIG are also changed to 0xFF for potential
requirement.

Change-Id: I61ea8295d5ee8ffbbd0cfcf9e4bece770d70e1f2
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/10651
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-25 04:06:59 +02:00
Kyösti Mälkki a48232268d sandy/ivy: Include IRQ routes from platform
The default route does work for all Chromebooks and is replaced
with platform-specific one in follow-up.

Change-Id: Ia1839ed38dacf44a89dc757394d054e17666f193
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10442
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-24 02:02:44 +02:00
Martin Roth 59aa2b191b southbridge/intel: Create common IFD Kconfig and Makefile
We've got a lot of duplicated code to set up the IFD/ME/TXE/GBE/ETC.
This is the start of creating a common interface for all of them.

This also allows us to reduce the chipset dependencies for CBFS_SIZE.

Change-Id: Iff08f74305d5ce545b5863915359eeb91eab0208
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10613
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-23 22:48:45 +02:00
WANG Siyuan db08765962 AMD Kern: Fix path of PspSecureOs BLOB
AMD Kern uses PspSecureOs_prod_CZ.csbin rather than PspSecureOs_prod_CZ.sbin.
PspSecureOs_prod_CZ.csbin is the firmware in CarrizoPI v1.0.0.7.

Change-Id: Idf54ee808dd6965aec9b979be00b7f890a88b06d
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10639
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-06-23 18:30:16 +02:00
Martin Roth 7403e059ec Remove incorrect Kconfig expressions
The symbols used in these expressions were not correct and would never
evaluate as true.

Change-Id: Ia20177f41505473b14bc7b8e4b6fb16de36cc295
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10437
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-22 21:22:47 +02:00
Jonathan A. Kollasch 5f6c392924 ck804 ACPI: set duty width in FADT correctly
Change-Id: I12ef633009b5c63b08fbeb76d58cb08c776485ac
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10546
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-15 03:08:45 +02:00
Paul Menzel 7b1a8a7445 amd/cimx/sb800/acpi/smbus.asl: Align comments
Change-Id: I1ea1b1efedfea2926a24f06beeb8d7d0464057e5
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10543
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-06-14 12:16:39 +02:00
WANG Siyuan f2dfef01e1 southbridge/amd/pi: Add support for new AMD southbridge Kern
Kern is the southbridge of AMD Merlin Falcon(Carrizo).
This add support of HD audio, lpc, sata and usb for Kern.

Change-Id: Ie47e38bc1099cdb72002619cb1da269f3739678b
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10418
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-13 02:22:49 +02:00
WANG Siyuan b3932e4975 AMD PI: remove unuseful ACPI code
sata.asl and superio.asl are empty files. Remove them.

Change-Id: Icd3e990aa713281e46dcbd8e0847166c77656b1c
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-10 21:02:15 +02:00
Vladimir Serbinenko 0f9aa1c9cd model_2065x: Use common i945-ivy TSEG SMM init.
Change-Id: I0302cbaeb45a55a4cfee94692eb7372f2b6b206d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10 05:34:01 +02:00
Vladimir Serbinenko f34082c0e3 fsp_model_206ax: Use common i945-ivy tseg SMM init.
Change-Id: Iac390b565d709b11bc7a6631b11315994b6e2c3c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10466
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-10 05:33:18 +02:00
Vladimir Serbinenko c16e9dfa18 Create i945-ivy smm tseg init based on ivy code.
CPU-side logic is unchanged for this range of CPUs as long as all of them
use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while
extracting southbridge and APIC code into separate functions.

Change-Id: Ib365681d1da8115922c557fddcc59afc156826da
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10465
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-06-09 19:52:27 +02:00
Kyösti Mälkki aa04e18409 x86 SMM: Relocator is intel-only
Change-Id: I78519b8f060b1ba81e8b9c7c345820180a14f2fe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10441
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-08 23:20:26 +02:00
Edward O'Callaghan 4565aea8fb southbridge/amd/{agesa,pi}/hudson/lpc.c: Sync together
Resync together, backporting a fix for the initialization of
8254 and 8259, as in commit 8d9a1bd5. Also fix a typo and
reduce out useless whitespace differences.

Change-Id: I9a9b1fb9083c5417a8d061f90a89074f2a601ddf
Signed-off-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reported-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10453
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-08 13:01:55 +02:00
Elyes HAOUAS 52648623e0 Remove empty lines at end of file
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;

Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-08 00:55:07 +02:00
Alexander Couzens 83fc32f7a7 device_ops: add device_t argument to write_acpi_tables
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I1ba4bfa0ac36a09a82b108249158c80c50f9f5fd
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9599
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 21:12:11 +02:00
Alexander Couzens 5eea458822 device_ops: add device_t argument to acpi_fill_ssdt_generator
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I7fca8c3fa15c1be672e50e4422d7ac8e4aaa1e36
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 21:11:43 +02:00
Alexander Couzens a90dad1bf0 device_ops: add device_t argument to acpi_inject_dsdt_generator
`device_t device` is missing as argument. Every device_op function
should have a `device_t device` argument.

Change-Id: I3fc8e0339fa46fe92cc39f7afa896ffd38c26c8d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/9597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 21:11:14 +02:00
Julius Werner 7a8a4ab1d8 lib: Unify log2() and related functions
This patch adds a few bit counting functions that are commonly needed
for certain register calculations. We previously had a log2()
implementation already, but it was awkwardly split between some C code
that's only available in ramstage and an optimized x86-specific
implementation in pre-RAM that prevented other archs from pulling it
into earlier stages.

Using __builtin_clz() as the baseline allows GCC to inline optimized
assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and
to perform constant-folding if possible. What was previously named log2f
on pre-RAM x86 is now ffs, since that's the standard name for that
operation and I honestly don't have the slightest idea how it could've
ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm
with Float result, whereas the Find First Set operation has no direct
correlation to logarithms that I know of). Make ffs result 0-based
instead of the POSIX standard's 1-based since that is consistent with
clz, log2 and the former log2f, and generally closer to what you want
for most applications (a value that can directly be used as a shift to
reach the found bit). Call it __ffs() instead of ffs() to avoid problems
when importing code, since that's what Linux uses for the 0-based
operation.

CQ-DEPEND=CL:273023
BRANCH=None
BUG=None
TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new
log2() and __ffs() results on Falco for a bunch of test values.

Change-Id: I599209b342059e17b3130621edb6b6bbeae26876
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f
Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/273008
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05 13:18:55 +02:00
Kyösti Mälkki 580e7223bb devicetree: Change scan_bus() prototype in device ops
The input/output value max is no longer used for tracking the
bus enumeration sequence, everything is handled in the context
of devicetree bus objects.

Change-Id: I545088bd8eaf205b1436d8c52d3bc7faf4cfb0f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8541
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04 11:22:53 +02:00
Kyösti Mälkki de271a8f0a PCI subsystem: Drop parameter max from scan_bus
Change-Id: Ib33d3363c8d42fa54ac07c11a7ab2bc7ee4ae8bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8539
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-04 11:21:42 +02:00
Kyösti Mälkki d0e212cdce devicetree: Discriminate device ops scan_bus()
Use of scan_static_bus() and tree traversals is somewhat convoluted.
Start cleaning this up by assigning each path type with separate
static scan_bus() function.

For ME, SMBus and LPC paths a bus cannot expose bridges, as those would
add to the number of encountered PCI buses.

Change-Id: I8bb11450516faad4fa33b8f69bce5b9978ec75e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8534
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-06-04 11:19:01 +02:00
Vladimir Serbinenko b06a249c3b bd82x6x: Move calling of finalize() on resume to southbridge code
Change-Id: I6416cd5780fbda0b3c2e236ce98a9f9a508e70c6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10293
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-29 11:26:06 +02:00
Vladimir Serbinenko 53be14c9e2 Remove whitespace at the end of line.
Change-Id: Ie9c3ef9fb4b3b2a0450a56e1d752b6509fa72a86
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10364
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2015-05-29 09:36:20 +02:00
Vladimir Serbinenko f119f0895c i82801gx: Reserve LPC decodes.
This change makes sure that LPC controller declares resources that it
actually decodes. bd82x6x already does it but i82801gx doesn't leading
to allocator potentially allocating something else to the same range.

Change-Id: Ieca9852e54c08e31d4d41aea97f317d9a6919806
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7662
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29 08:21:00 +02:00
Vladimir Serbinenko faa46e0cb6 nvs: Add missing stdint.h include.
nvs.h uses u8 without including stdint.h.

Change-Id: I4ffcbb850cb7b8f47126ee1906b9e0960dd449e8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-29 07:45:32 +02:00
Vladimir Serbinenko 7f46420f4c Migrate fsp_206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for fsp_bd82x6x.

This is adaptation of a3e41c0896

Change-Id: I4e80e6e98d3a6da3e3e480e9368fae1b3ed67cd6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10353
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28 22:07:30 +02:00
Vladimir Serbinenko 456f495d4e Migrate 2065x to SMM_MODULES
This gets rid of ugly tseg_relocate for ibexpeak.

This is backport of 29ffa54969 to ibexpeak.

Change-Id: I456d85abdbadb2fdccf77ca771e2518cf8b8c536
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10352
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28 22:07:08 +02:00
Vladimir Serbinenko a3e41c0896 Migrate 206ax to SMM_MODULES
This gets rid of ugly tseg_relocate for bd82x6x.

This is backport of 29ffa54969 to bd82x6x.

Change-Id: I0f52540851ce8a7edaac257a2aa83d543bb5e530
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-28 17:56:17 +02:00
Vladimir Serbinenko dd2bc3f819 igd.asl rewrite
Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.

Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-28 08:27:10 +02:00
Patrick Georgi 25509ee245 Remove address from GPLv2 headers
Follow up for commit b890a12, some contributions brought
back a number of FSF addresses, so get rid of them again.

Change-Id: I0ac0c957738ce512deb0ed82b2219ef90d96d46b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10322
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-28 04:21:52 +02:00
Kyösti Mälkki b1fcbf364f AGESA: Separate HeapManager declarations from BiosCallOuts
Change-Id: I168db92b10d5abc05be2dc374df3f892003d5255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10317
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-27 12:52:07 +02:00
Vladimir Serbinenko 9bb5c5c402 acpigen: Remove all explicit length tracking
Change-Id: I88248d78c01b4b4e42a097889b5f4ddfdac3d966
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7367
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2015-05-26 20:31:41 +02:00
Vladimir Serbinenko 83f81cad7a acpi: Remove monolithic ACPI
All boards now use per-device ACPI. This patch finishes migration
by removing transitional kludges.

Change-Id: Ie4577f89bf3bb17b310b7b0a84b2c54e404b1606
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7372
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-26 10:25:47 +02:00
Vladimir Serbinenko e288758b03 bd82x6x: Merge common platform ASL code.
This code in reality just describes the southbridge features, don't put a copy
in every mainboard.

Change-Id: I8cf3019a36b1ae6a17d502e7508f36ea9fa62830
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10231
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-05-26 08:53:12 +02:00
Vladimir Serbinenko 11b01a9574 Kill ENABLE_TPM.
It's used only in P470 and lynxpoint machines. Remove it from other
southbridges. New machines should use src/drivers/pc80/tpm.

Change-Id: I4741e76df4c6204d65562f016abac9ed60558432
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10268
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21 20:50:49 +02:00
Patrick Georgi b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Vladimir Serbinenko 5e597572ef acpi: make fill_slit and fill_srat into arguments.
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.

Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 19:51:40 +02:00
Vladimir Serbinenko 4141b47b07 bd82x6x: Merge common apmc finalize procedure.
Change-Id: I9c938b8a69479fae6b0eb99d1135f1caaf26d0e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10227
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 15:46:56 +02:00
Vladimir Serbinenko 9d45d6975c ibexpeak: Merge common NVS init
Change-Id: Ia5e26110928fa011305c13362f20fbe78ca9cf30
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7134
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2015-05-15 08:44:59 +02:00
Vladimir Serbinenko d3b194e6fe bd82x6x, ibexpeak: Support fully locking ROM on S3 resume.
Currently only RO-lock is supported. Make full lock available as an option.

Change-Id: Ib68a1e82733a51053a9adc80ac501b6205c6b8a7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10191
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
2015-05-14 20:00:11 +02:00
Damien Zammit f88b93214b southbridge/i82801gx: Add x_EN defines for LPC_EN
A few hardcoded values could be fixed after this commit

Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-05-08 21:29:04 +02:00
Patrick Georgi 26e24cc12d 3rdparty: move to 3rdparty/blobs
There's now room for other repositories under 3rdparty.

Change-Id: I51b02d8bf46b5b9f3f8a59341090346dca7fa355
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10109
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:18 +02:00
Patrick Georgi f4f028790a 3rdparty: Move to blobs
To move 3rdparty to 3rdparty/blobs (ie. below itself
from git's broken perspective), we need to work around
it - since some git implementations don't like the direct
approach.

Change-Id: I1fc84bbb37e7c8c91ab14703d609a739b5ca073c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10108
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-05 22:49:11 +02:00
Timothy Pearson 58649b058b src/southbridge/intel/i82801ix: Add GPIO register locations
Change-Id: I226a1a6bc6b1f921c03f8ec57875a88314928aeb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-03 09:14:33 +02:00
Martin Roth 595e7777e7 Kconfig whitespace fixes
trivial whitespace fixes.  Mostly changing leading spaces to tabs.

Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10000
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28 21:14:56 +02:00
Kyösti Mälkki b85a87b7d6 intel SMI handlers: Refactor GPI SMI/SCI routing
Move the GPI interrupt routing selection between SMI/SCI from
mainboards to southbridge. There is speculation if this is all
just legacy APM stuff that could be removed with a followup.

Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7967
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-04-28 07:59:13 +02:00
Stefan Reinauer 13e4182119 kbuild: automatically include southbridges
This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.

In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.

This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-27 23:48:35 +02:00
Marc Jones 786879777a fsp: Move fsp to fsp1_0
Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific
directory. See follow-on patches for sharing of common code.

Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/9970
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-24 00:37:37 +02:00
Damien Zammit 31ca97c38c southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset
Change-Id: I3375c21d5d4aed30d5641629c44d6a5885efee11
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/9807
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
2015-04-20 23:51:34 +02:00
Nicolas Reinecke 59aef5c79e southbrige/intel/bd82x6x: add XHCI overcurrent map config
Change-Id: I9a40e5a1028c7674e6dd54742e6646ba48ce7696
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9449
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-20 23:50:38 +02:00
Nicolas Reinecke 0b29a7b37c southbrige/intel/bd82x6x: XHCI replace magic values
Change-Id: I62674ccfb836fb0b02ac562f678cdfa44be98ae3
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/9779
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-19 21:26:14 +02:00
nicky sielicki 1376b680c2 southbridge/intel/fsp_rangeley/ : Spellcheck + Formatting
Changes:
acpi.c      - Capitalize an acronym.
early_spi.c - Spelling error.
gpio.c      - Capitalization of acronym + sentences.
gpio.h      - Capitalization of sentences.
lpc.c       - Capitalization of sentences.
soc.c       - Spelling error + capitalization of acronym.

I just wanted to go through the process of commiting something onto Gerrit.

Change-Id: Iad2ac5409f883c5b7cbc25e4e296f386ad7e13d0
Signed-off-by: nicky sielicki <nlsielicki@wisc.edu>
Reviewed-on: http://review.coreboot.org/9510
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-04-10 17:57:11 +02:00
Sergej Ivanov f687c92c9b southbridge/amd/agesa/hudson: Fix LPC_DEV definition
In agesa code for hudson southbridge LPC_DEV is not defined,
but used. Define LPC_DEV as done in southbridge/amd/cimx/sb800.
This fixes it.

Change-Id: Ie7db791e9eb607008e70e446fc6fd28114742750
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: http://review.coreboot.org/9292
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2015-04-10 15:28:13 +02:00
Stefan Reinauer a48ca841a2 kconfig: drop intermittend forwarder files
With kconfig understanding wildcards, we don't need
Kconfig files that just include other Kconfig files
anymore.

Change-Id: I7584e675f78fcb4ff1fdb0731e340533c5bc040d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9298
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-04-07 17:40:28 +02:00
Varad Gautam 06ef046045 global: Refactor get_option usage
Restructure get_option() calls to avoid unnecessary return value checks
by pre-assigning defaults to the options being retrieved.

Change-Id: I9159afe149a8eeed0785d1efd6eee8420b88b8f4
Signed-off-by: Varad Gautam <varadgautam@gmail.com>
Reviewed-on: http://review.coreboot.org/8631
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-04-06 19:40:00 +02:00
Patrick Georgi 990e7c90f0 build system x86: deprecate bootblock_lds and ldscripts variables
Instead of keeping this separate variable around, add linker scripts
to the $(class)-y source lists and let the build system sort things out.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I4af687becf2971e009cb077debc902d2f0722cfb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9289
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-04 20:07:12 +02:00
Dave Frodin 8d9a1bd5a8 southbridge/amd/pi: Add initialization of 8254 and 8259
This moves the initialization of the 8254 and 8259 out
of the (unmerged) lamar mainboard romstage.c file and into
the southbridge code as it is done in the other AMD
southbridges.

Change-Id: I73b375754ee4a9bf15981f2cd31056d7e04db23e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/9182
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-04-02 19:19:20 +02:00
Patrick Georgi 2e1f18336d amd/pi/hudson: INCLUDES was renamed to CPPFLAGS_common
And this path is already included properly elsewhere.

Change-Id: I9fc6887fc047a9df1c4cb6fa4f841abb16f6d548
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9174
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-04-01 20:53:27 +02:00
Martin Roth 72a8e5e751 Update hex values to CBFS binary name types in Makefiles
These binaries were being added to CBFS using hexadecimal values instead
of the CBFS binary type names.  The same value was being used in
different places for different things.
For example, the value 0xAB is used for SPDs, MRC & FSP binaries.

This patch uses CBFS type names instead of hex values everywhere a
hex value was previously used.

Change-Id: Id5ac74c3095eb02a2b39d25104a25933304a8389
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8978
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-30 21:47:15 +02:00
Patrick Georgi ea9f308018 build system: normalize linker script file names
We have .lb, .lds, and .ld in the tree. Go for .ld everywhere.

This is inspired by the commit listed below, but rewritten to match
upstream, and split in smaller pieces to keep intent clear.

Change-Id: I3126af608afe4937ec4551a78df5a7824e09b04b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Based-On-Change-Id: I50af7dacf616e0f8ff4c43f4acc679089ad7022b
Based-On-Signed-off-by: Julius Werner <jwerner@chromium.org>
Based-On-Reviewed-on: https://chromium-review.googlesource.com/219170
Reviewed-on: http://review.coreboot.org/9107
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-28 19:14:47 +01:00
Kyösti Mälkki 4da487eae8 CBMEM: Add LATE_CBMEM_INIT guards
Our target is to get rid of backup_top_of_ram() and get_top_of_ram()
entirely so only declare these with LATE_CBMEM_INIT=y.

Change-Id: I54f549fe774996f4d803f9ec527e0fac46f6576f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8749
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-03-19 06:17:07 +01:00
Kyösti Mälkki 1e60839be0 southbridge/amd/rs780: Remove requirement for CF8/CFC config access
The AMD RS780 early initialization code originally used the
CF8/CFC I/O method for PCI configuration space access. After
the default configuration access method was changed to MMIO
(http://review.coreboot.org/#q,aad07472), booting would hang
at "PCI: pci_scan_bus for bus 01". Fix the problem by changing
function rs780_nb_gfx_dev_table() so that it no longer borrows
the BAR3 address needed for PCIe MMIO config usage.

Change-Id: I8816b94c848e1b50f8c880e5867a96ca2a33a8a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8394
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-19 04:00:08 +01:00
Aaron Durbin 9ef9d85976 bootstate: use structure pointers for scheduling callbacks
The GCC 4.9.2 update showed that the boot_state_init_entry
structures were being padded and assumed to be aligned in to an
increased size. The bootstate scheduler for static entries,
boot_state_schedule_static_entries(), was then calculating the
wrong values within the array. To fix this just use a pointer to
the boot_state_init_entry structure that needs to be scheduled.

In addition to the previous issue noted above, the .bs_init
section was sitting in the read only portion of the image while
the fields within it need to be writable. Also, the
boot_state_schedule_static_entries() was using symbol comparison
to terminate a loop which in C can lead the compiler to always
evaluate the loop at least once since the language spec indicates
no 2 symbols can be the same value.

Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8699
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-18 16:41:43 +01:00
Dave Frodin f364fc7682 southbridge/amd/pi: Enable early I/O decode to LPC
The decode of UART addresses down to the LPC bus needs
to occur early to allow romstage console messages to
be seen. This enables the decode of most of the I/O
ports typically seen in a system.

Change-Id: I6636946af4ad5320a5a46c2920b4f06345b5f806
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-03-17 17:49:58 +01:00
Stefan Reinauer c3d15a7210 Intel common SPI: Fix compilation breakage from refactoring
When the Intel SPI drivers were refactored, compilation for Chrome OS
devices broke, because ELOG uses the SPI driver in SMM.

Change-Id: If2b2da5d526196ed742e17409b01a381417d0ce8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/8701
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-17 04:55:52 +01:00
Kyösti Mälkki 48b3dbc748 x86 SMM: Replace weak prototypes with weak function stub
Change-Id: I682617cd2f4310d3e2e2ab6ffec51def28a4779c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7961
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-11 18:15:22 +01:00
Kevin Paul Herbert 4104e6cd30 x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).

Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.

Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-27 18:15:33 +01:00
Patrick Georgi bdd185a355 amd/sb600: Fix NULL test after use issue
Change-Id: Icecbcc1dee837ecfe0dd52bade3b83fdcdd15bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8513
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-25 14:05:42 +01:00
Kyösti Mälkki 9b5f137823 Intel ibexpeak: Fix SATA configuration
It got broken with commit bde6d309.

Change-Id: I0d7180b1659da45bf87d4de46b7b387cbc73cd0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-24 11:49:32 +01:00
Kyösti Mälkki 0b87bb7726 AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins
Some GPIO pins are shared with PCI bridge 0:14.4.

As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.

Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-02-23 21:33:55 +01:00
Kyösti Mälkki b4fa3fd2ae nvidia/ck804: Minor cleanup on dead code
Change-Id: I07f4190ab73ec3468e3738be14d64468e2a05720
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8340
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:18 +01:00
Kyösti Mälkki 413e3da8c0 nvidia/ck804: Fix redundant configuration defines
All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.

Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:14:02 +01:00
Kyösti Mälkki facf0b9361 Revert "nvidia/ck804: Add ability to override CK804 base unit ID"
This reverts commit b871687991.

Use of #ifndef here makes it error-prone and hides errors.

Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-16 23:13:50 +01:00
Timothy Pearson 033bb4bc8d acpi: Generate valid ACPI processor objects
The existing code generated invalid ACPI processor objects
if the core number was greater than 9.  The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.

The modified code will function with up to 99 cores.

Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-16 21:02:30 +01:00
Kevin Paul Herbert bde6d309df x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
2015-02-15 08:50:22 +01:00
Kyösti Mälkki 24501cae52 AMD cimx/sb800: Initially enable all GPP ports
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().

Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:59 +01:00
Kyösti Mälkki 41cd047cd2 AMD cimx/sb800: Move cimx init for ramstage
This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.

Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:44 +01:00
Kyösti Mälkki 486c05f4bf AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration
A set of pins can be configured for GPIO or (parallel) PCI bridge use.

When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.

When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.

As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.

Drop related dead code.

Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:23 +01:00
Kyösti Mälkki 11f9c35bd2 AMD cimx/sb800: Fix console output
These sb800_enable() messages without newline mess up the log.

Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-14 22:37:15 +01:00
Dave Frodin 4675c598a4 southbridge/amd/pi: Combine and correct the IRQ text strings
This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.

Test: This was verified on amd/lamar.

Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-14 00:31:06 +01:00
Kyösti Mälkki cd02ef19e5 Intel FSP platforms: Fix timestamps
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.

Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-02-09 11:41:34 +01:00
Dave Frodin 5c015f045d southbridge/amd/pi: write_hpet requires additional config option
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI

TEST: amd/lamar.

Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-05 17:34:05 +01:00
Dave Frodin ef9a4e6aec southbridge/amd/pi: Update Kconfig and makefiles for bolton
Change-Id: I208c931bdaee572c9df11b35c1e6e9f27609ea6c
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8287
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-05 17:33:42 +01:00
Dave Frodin 9cfa742a26 southbridge/amd/pi: Add the bolton definitions
This adds the PCI and interrupt related definitions
for the bolton specific features.

Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2015-02-05 17:33:00 +01:00
Kyösti Mälkki 09b5e4d005 AMD8131: Remove obsolete directory
Change-Id: I875384e55a4a71d1a5c962d128d13356f3befa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-02-05 02:17:42 +01:00
Jonathan A. Kollasch 30c34c0751 nvidia/ck804: make Message Signaled Interrupts work
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable
HT MSI Mapping so that MSIs work.  Prior to this change PCIe devices
downstream of the CK804 with MSI enabled would fail to actually assert
their interrupt.  Tested on msi/ms7135 and winent/mb6047 running Debian
GNU/Linux 7.0 (wheezy).

Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8276
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-03 00:47:26 +01:00
Vladimir Serbinenko b26156ec65 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/8312
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-02-01 08:22:40 +01:00
Nicolas Reinecke 6d1158f3a9 southbridge/intel/bd82x6x native usb init: replace some magic values
Some magic numbers are documented in the PCH datasheet so use them.

Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8307
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-31 07:20:15 +01:00
Timothy Pearson 7f3ae39640 nvidia/ck804: Enable AMD Family 0Fh/10h dynamic ACPI _PSS objects
Change-Id: I682e6c34d059ae21f9767302659bdfdbea86bcc8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8285
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 20:58:10 +01:00
Timothy Pearson b871687991 nvidia/ck804: Add ability to override CK804 base unit ID
Change-Id: Ic1b35b6bdd9c6d9ab672242e40b73aff1d626e81
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8273
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2015-01-28 20:00:17 +01:00
Timothy Pearson e916201004 nvidia/ck804: Fix FTBFS with AMD Family 10h systems
The build failure stems from a missing function being called via a chain
including setup_ss_table(), set_ht_link_ck804(), and
st_ht_link_buffer_counts_chain(); the latter function is only available
in the AMD K8 code.

It appears that a bunch of K8-specific code snuck into the CK804 and MCP55
southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0.

Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8269
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:56:15 +01:00
Timothy Pearson 02112bd280 nvidia/ck804: Add ability to enable/disable PCIe PME# wake events
Change-Id: Ie2937dd220464e3b168aa8a50a57c03b6258c189
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8283
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 19:03:39 +01:00
Timothy Pearson 684fda5964 nvidia/ck804: Fix cosmetics in Kconfig
Change-Id: Ic675911f534f07516c838b52c9463e89448d4353
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8291
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-01-28 18:59:20 +01:00
Timothy Pearson e1cc3abb02 nvidia/ck804: Add ability to bypass register 0x78 initialization
On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost
immediate soft reset.  Leaving the register at its power-on
default value appears to have no ill effect on that same board.

Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8272
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2015-01-28 05:26:14 +01:00