Commit Graph

4945 Commits

Author SHA1 Message Date
Denis 'GNUtoo' Carikli e87e73edba google/veyron: Indicate which boards are laptops.
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards

Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-17 21:30:08 +01:00
Ben Gardner fa6014a6ec intel/fsp_baytrail: rename include folder baytrail to include/soc
This is to match the layout of the non-fsp baytrail to make comparisons
easier and possibly remove duplicate files.

Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12686
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16 01:10:06 +01:00
Martin Roth 1e1c7ac3b4 southbridge/amd/sb600: Update HPET base address with #define
The SB600 code had the base address of the HPET hardcoded throughout.
It looks like the plan was to have it be updated in ACPI if needed,
but this wasn't ever implemented.  The variable names being used to
do this update were the same, causing an IASL warning.  Because of
this, the operation to update the HPET address actually did nothing.
This was fine, because it didn't actually need to be updated.

- Replace all that code with a #define.
- Add and update some comments in the same area.

Fixes IASL warning:
dsdt.aml   1505:       Store(HPBA, HPBA)
Warning  3023 -                      ^ Duplicate value in list (Source is the
same as Target)

Change-Id: I9ba5fe226a4a464e0045ce7d3406898760df5e5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12705
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-12-16 00:56:08 +01:00
Aaron Durbin 07a1b281a8 x86 acpi: remove ALIGN_CURRENT macro
The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.

Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15 20:12:01 +01:00
Timothy Pearson ecd4cfcb86 mainboard/asus/kgpe-d16: Enable romstage spinlocks
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12628
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-15 16:43:09 +01:00
Martin Roth a09bb426d4 google/oak: Move CHROMEOS specific Kconfig objects under CHROMEOS
The symbols CHROMEOS_VBNV_EC, EC_SOFTWARE_SYNC, and VIRTUAL_DEV_SWITCH
should only be selected if CHROMEOS is selected.

Change-Id: I07ef631d63be53cf99a6bf61d0e91b88728dbba3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12659
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-15 01:14:27 +01:00
Martin Roth ae1bab3c9d emulation/qemu-arm7: Fix Kconfig symbols for stage compilers
These had typos ARM_STAGE_ARM7 instead of ARCH_STAGE_ARM7

Change-Id: Iffe8fecb3e52a50ff02b774478a10c353093688b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12660
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:36:04 +01:00
Martin Roth 3e41ee9847 ACPI: Fix IASL Warning about unused method for _S3 check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml 640:              If (CondRefOf (\_S3, Local0))
Warning  3144 - Method Local is set but never used ^  (Local0)

Change-Id: I758d198c33e585a6a4ad2c1c70f2370a01af5138
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:56 +01:00
Martin Roth f77516cb6d ACPI: Work around IASL warning reading/writing same register
The newer versions of IASL are unhappy when an operator
has the same object as both source and destination.

The warning can be completely disabled with a command
line argument, but in general, I'd really rather not
just disable warnings.

The bits in this register are write 1 to clear, so reading and
writing the same register is what we want to do.  Instead, store
it in a temporary register then write it in a second operation.

Fixes warning:
dsdt.aml   1396:  Store(PWST, PWST)
Warning  3023 -                 ^ Duplicate value in list
(Source is the same as Target)

Change-Id: I52d73d4431db237be83016d67cd397f31b53d9c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:32:21 +01:00
Martin Roth 91d9cbc2fb ACPI: Fix IASL Warning about unused method for _OSI check
According to the ACPI Spec for CondRefOf, the result argument is
optional.  In all of these locations, it was getting set but not
used, creating a warning in new versions of IASL.  Since it's
an optional argument, just remove it.

dsdt.aml     22:   if(CondRefOf(\_OSI,Local1))
Warning  3144 -                           ^
Method Local is set but never used (Local1)

Change-Id: I07f49ac5a3708838d1c4a7216dfb11acc415c881
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12692
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 16:31:35 +01:00
Aaron Durbin 6d720f38e0 cbfs/vboot: remove firmware component support
The Chrome OS verified boot path supported multiple CBFS
instances in the boot media as well as stand-alone assets
sitting in each vboot RW slot. Remove the support for the
stand-alone assets and always use CBFS accesses as the
way to retrieve data.

This is implemented by adding a cbfs_locator object which
is queried for locating the current CBFS. Additionally, it
is also signalled prior to when a program is about to be
loaded by coreboot for the subsequent stage/payload. This
provides the same opportunity as previous for vboot to
hook in and perform its logic.

BUG=chromium:445938
BRANCH=None
TEST=Built and ran on glados.
CQ-DEPEND=CL:307121,CL:31691,CL:31690

Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12689
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10 04:43:58 +01:00
Martin Roth 9ed54f99c7 mohonpeak/Kconfig: Fix whitespace issues
Auto-indent did me wrong, and I didn't notice it.

Change-Id: I5a736cf53a3bdbe57b28b2d6a55befd341d8dfd8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12655
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-09 16:18:14 +01:00
Patrick Georgi e7cd0f889e google/oak: define flash size
We never defined the flash size for this board, so the (too small)
default was used. Instead, adopt the size given in depthcharge's fmap
description.

Change-Id: I63782922ee05a9595d6c0de56750460ebb67aec6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12674
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-12-09 09:20:50 +01:00
Martin Roth d7ad21aa5c intel/strago: Remove CONFIG_ from CONFIG_GOP_SUPPORT inside Kconfig
The CONFIG_ is only used for Kconfig symbols outside of Kconfig.  If
used inside Kconfig, you'd end up with CONFIG_CONFIG_GOP_SUPPORT when
it was used in the C code.

Change-Id: I572323ef08fdd937d33ded1c27a418b3ad856147
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12664
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08 17:13:52 +01:00
Francis Rowe 66d0f11115 lenovo/t500: Add clone of Lenovo T400
The existing code for the Lenovo T400 works without changes on the
Lenovo T500.  Same HDA verbs are provided by Lenovo BIOS on both
laptops.

Change-Id: I300408a8a0ed00476aee6061925befc2822fb505
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10545
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-08 16:44:40 +01:00
Martin Roth b790fe944d intel/littleplains: Update with recent changes to mohonpeak
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
- Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
- Remove fixed microcode location.

Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12635
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>
2015-12-08 00:01:26 +01:00
Timothy Pearson 369b561315 mainboard/asus/kgpe-d16: Use I/O PCI access in bootblock
The existing code incorrectly used standard PCI access
calls in the bootblock.  Use the I/O PCI access calls
as the normal PCI access mechanisms have not yet been
set up.

Also ensure the recovery jumper GPIO has been set to
input mode before reading it.

Change-Id: Id626d01526427004b2404e4d9b44d7c987d172d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12651
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-12-07 17:06:31 +01:00
Martin Roth eca844b949 pcengines/apu1: Supply _HID object for ACPI GPIO devices
The _HID was present for the top level BTNS and LEDS Devices, but
was missing in the individual devices.

The alternative would be to supply the GPIO being used as an _ADR
object, but since it looks like the driver already has another
method of handling that, it isn't required.

Fixes these IASL warnings:
dsdt.aml   1522:   Device (BTN1)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1567:   Device (LED1)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1576:   Device (LED2)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   1587:   Device (LED3)
Warning  3141 -              ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I67c48084a6ee2a104ffff2b5a986d24a51ee49e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12582
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:49:26 +01:00
Martin Roth 49fdf3f957 intel/fsp_rangeley: change non-existent config options to #defines
Kconfig symbols CONFIG_ACPI_INCLUDE_PMIO and CONFIG_ACPI_INCLUDE_GPIO
were never added to the coreboot codebase when the Rangeley code was
brought in from Sage.  These symbols disabled ACPI code that was unused
because it caused dmesg warnings due to conflicts with drivers trying to
claim the same addresses as the ACPI code.  Because it could be used on
some other platforms, it was left in instead of being completely
removed.

- Change the Kconfig symbol names to simple #defines in the mainboard
code.
- Add the #defines along with comments to the reference platform.
- Hook everything together in dsdt.asl
- Update new mainboard littleplains the same way.

Change-Id: I1f62157c6e447ea9b7207699572930e4711fc3e0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12552
Reviewed-by: David Guckian <david.guckian@intel.com>
Tested-by: build bot (Jenkins)
2015-12-06 18:46:47 +01:00
Martin Roth ad4764dddd hp/pavilion_m6_1035dx: Fix IASL warning - Missing _HID object
- Add System board _HID object.
- Remove Kconfig default disabling IASL warnings as errors

Fixes warning:
dsdt.aml     64:  Device (MB) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)

Change-Id: I4fa6ab2a6744d58ded8b0feb361e002d90e11474
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12532
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:43:36 +01:00
Martin Roth d49bbff8ff Rangeley: Change A, A, A, A INT routing to A, A, A, B
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0.  The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0.  On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.

This issue did not affect ACPI interrupt routing.

This is just a workaround, and the root issue still needs to be fixed.

Change-Id: I4e6fe56084cbe86b309da15d61b296f1936458ec
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12630
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:43:11 +01:00
Martin Roth cf752fe966 fsp_baytrail: Change A, A, A, A IRQ routing to A, A, A, B
Devices that have their interrupt routing set to A, A, A, A don't get
any interrupt values assigned because that series evaluates to 0.  The
code that sets the interrupt values checks to make sure a value is set
by verifying that it's not 0.  On Bay Trail, these are all
single-function graphics devices, so by changing one of the unused
interrupt lines from A to any other value, it assigns the values
correctly.

This issue did not affect ACPI interrupt routing.

This is just a workaround, and the root issue still needs to be fixed.

Change-Id: I78866e3e0079435037e457a4fb04979254b56ee2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12629
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:42:03 +01:00
Martin Roth c4fa3fdd3e intel/eagleheights: Fix IASL warnings
The eagleheights platform had 3 warnings:

The SIO device needs an _ADR object to specify the address in addition
to the operating region.

Not all the paths through the _OSC method returned a value.  According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.

dsdt.aml    341:   Device(SIO) {
Warning  3141 -            ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml  140: Method (_OSC, 4)
Warning  3115 -          ^ Not all control paths return a value (_OSC)
dsdt.aml  140: Method (_OSC, 4)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _OSC)

- Remove Kconfig default disabling IASL warnings as errors.

Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12522
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 18:35:48 +01:00
Yidi Lin 762cdfaaa0 google/oak: Add timestamps in romstage
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: Idf74265c9c1ab3a1a74fd18dfd289fccad25177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 569c433886b19cd08d168e995bf34156c2ba6963
Original-Change-Id: I07fda6a0719d49e2c07249276ae2cc0b57fdfeda
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292660
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12610
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04 21:52:59 +01:00
henryc.chen 31ae314f0f mediatek/mt8173: Add mt6391 PMIC driver
BUG=none
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a
Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5
Original-Signed-off-by: henryc.chen <henryc.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292669
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12608
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 21:52:48 +01:00
Michael Tasche 446c5dcd14 esd/atom15: import esd atom15 board
This patch adds esd atom15 board with
Intel Atom E3815 SoC.

Change-Id: I430a40ad8ab3316d34ec5567329370f69db3f15e
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12632
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 18:58:26 +01:00
Michael Tasche 4d166f9380 intel/minnowmax: Fix IRQ connection for legacy uart at 0x3f8
The E38xx legacy uart fires IRQ4, not IRQ3.
PCI based IRQ A is switched from IRQ4 to IRQ3,
to get a working IRQ for the legacy uart.

Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12622
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-12-04 18:58:02 +01:00
Sergej Ivanov cd920bf1c0 mainboard/biostar/am1ml: Force basic SPI read mode
This patch force AGESA to use basic SPI read mode.
Without it board hangs during spi configure if W25Q32 chip is used.

Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/12580
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-04 17:07:59 +01:00
Martin Roth c6a8d2ca7b intel/mohonpeak: Change SEABIOS_MALLOC_UPPERMEMORY to config_seabios
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS
.config file to do the same thing.

Change-Id: I29110a382b7770329ef938876426e571fbbbb339
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12569
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-12-03 21:53:32 +01:00
CC Ma 86933f89c4 google/oak: Add board_id() and ram_code() implementation
BRANCH=none
BUG=none
TEST=Oak build pass

Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410
Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292675
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:33 +01:00
Yidi Lin 65873ca934 google/oak: Implement the code which reads GPIOs for ChromeOS.
BUG=none
BRANCH=none
TEST=emerge-oak corebootk

Change-Id: Ic1a0d640cac7fd98acd06d619736303fa449c0a1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce465e8cbdf6465c072e476a91a400d78c959218
Original-Change-Id: Iade51db02f45264fdffe387e0563b60e637c0710
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292674
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12606
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:29 +01:00
Biao Huang 9d48e1732a google/oak: Initialize the necessary pins
BRANCH=none
BUG=none
TEST=verified on Oak rev2 & rev3

Change-Id: I35776f5bdf54243236afba860ae8e9117a160cde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b46bd9a079107ab78964f7e39582b3b5c863b559
Original-Change-Id: I6696972d07adbf3da5967f09c1638bb977c10207
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292673
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12605
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:25 +01:00
Wisley 1a8e43e4e3 google/chell: update dptf TSR1 & TSR2 critial points
update dptf TSR1 & TSR2 critial points from 70 to 75
TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT
test, change the point will avoid to trigger critial in our factory
run in test

BRANCH=none
BUG=none
TEST=build and boot chell DUT

Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb
Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca
Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313967
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/12604
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:23:21 +01:00
Saurabh Satija 5b242f6307 intel/kunimitsu: Coreboot GPIO changes for FAB 4.
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.

BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.

Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:50 +01:00
Duncan Laurie 7a2963b86c google/glados: Disable kepler device
Disable the kepler device to save power and enable S0ix testing.
It has been disabled in the ME image and was not working anyway..

BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados

Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54
Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313827
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-12-03 14:22:42 +01:00
Duncan Laurie 4938feaee5 google/chell: Update mainboard for EVT
- Disable kepler device, it is removed and was not used on proto anyway.
- Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM.
- Disable HS400, this is breaking some devices on proto boards and
is being disabled to reduce risk for EVT build.
- Change Type-C USB2 port drive strength.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto

Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180
Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313825
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:22:35 +01:00
david 1fc5d1f01a google/lars: SPD change for Proto board
Update Memory ID for Proto board
Update detection of single/dual channel memory to use SPD Index (Memory ID)
Remove boardid.h as it is no longer needed

BUG=None
BRANCH=None
TEST=Build and Boot Lars (Proto)

Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8
Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313903
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12593
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:44 +01:00
Brandon Breitenstein a009158bf9 intel/kunimitsu: Updated Micron SPD data
Updated Micron SPD data to correct values

BUG=none
BRANCH=none
TEST=Tested on FAB 4 with Micron Dimm
CQ-DEPEND=CL:312546

Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735
Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313003
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:39 +01:00
Brandon Breitenstein e1aceef955 intel/kunimitsu: FAB 4 update for Rcomp Target table
Changed index 3 to be an exception of the default Rcomp Value

BUG=None
BRANCH=None
TEST=Tested on FAB 4 SKU 1

Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622
Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/12591
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:34 +01:00
Brandon Breitenstein ad77bf9320 intel/Kunimitsu: FAB 4 SPD changes
Updated Memory IDs and SKU IDs for FAB 4
Updated detection of single/dual channel memory to use SPD Index (Memory ID)
Added spd files for new dimms
Removed boardid.h as it is no longer needed

BUG=None
BRANCH=None
TEST=Tested on FAB4 SKU1 and SKU3

Change-Id: I60403c0e636ea28797d94cff9431af921631323e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4
Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312546
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:30 +01:00
Yidi Lin 3d7b6069e1 mediatek/mt8173: Add a stub implementation of the MT8173 SoC
BUG=chrome-os-partner:36682
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a
Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292558
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:17:08 +01:00
Martin Roth c7b26c381c lippert/frontronner-af & toucan-af: Fix IASL warnings
Not all the paths through the _OSC method returned a value.  According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.

Fixes warnings for both platforms:
dsdt.aml 1143:  Method(_OSC,4)
Warning  3115 -          ^ Not all control paths return a value (_OSC)
dsdt.aml 1143:  Method(_OSC,4)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _OSC)

Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12530
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 16:10:06 +01:00
Damien Zammit 74d165b18d mainboard/intel/d510mo: Add Intel D510MO mainboard
Board uses Pineview native raminit
Board boots from grub to linux kernel

VGA needs work, currently headless machine

Change-Id: I8e459c6d40e0711fac8fb8cfbf31d9cb2aaab3aa
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/10074
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-02 00:39:03 +01:00
Timothy Pearson f1436e58d2 mainboard/asus/kgpe-d16: Enable GART by default
Change-Id: I73eb2425bbdb7e329a544d55461877d1dee0d05b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12067
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-01 16:31:47 +01:00
Marcin Wojciechowski 9586dc72db mainboard/intel: Add Little Plains
This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp

Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-30 18:00:50 +01:00
Timothy Pearson b4b298c449 mainboard/asus/kgpe-d16: Limit HT speed to 2.6GHz
The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz.  While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.

If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer.  Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.

Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-30 05:29:47 +01:00
Martin Roth 323c7db204 bachmann/ot200: Remove DRIVERS_I2C_IDREG Kconfig symbol
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually
existed in the coreboot codebase.  I didn't see anything that it might
have been a typo of.

Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12563
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2015-11-30 00:35:38 +01:00
Martin Roth 3bb9405494 ibase/mb899: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Move Named objects out of _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes these items:
dsdt.aml 1449:  Method (_CRS, 0)
Remark   2120 -           ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1458: Method (_REG, 2)
Warning  3079 -          ^ _REG has no corresponding Operation Region

Change-Id: I801a84468097687c91d6ee3f44cec06243355fac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-27 18:10:36 +01:00
Martin Roth 232df8b2d2 kontron/986lcd-m: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes IASL Warning and remark:
dsdt.aml   1451:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml   1460:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Change-Id: I4aa59468a89c4013146ab34004476a0968c60707
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12521
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-27 18:07:09 +01:00
Timothy Pearson 259549678b mainboard/asus/kgpe-d16: Add missing IOMMU setup
Change-Id: I9a00bdbcd47804b6d83c0231cd515773d02ff951
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12527
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 01:08:25 +01:00
Timothy Pearson eda407f4eb mainboard/asus/kgpe-d16: Add IOMMU nvram configuration option
Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-26 01:07:59 +01:00
Martin Roth 601ea3d40e lenovo t400: Fix IASL warning and remark
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.

Presumably, the ATPX would not need a return value if Arg0 is anything
other than 0, so just return a zero.

- Serialize ATPX method to make IASL happy.  This means that it can
only be used by one thread at a time.

Fixes these issues:
dsdt.aml   2581: Method (ATPX, 2, NotSerialized) {
Remark   2120 -            ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Warning  3115 -          ^ Not all control paths return a value (ATPX)

Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12518
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:42:57 +01:00
Martin Roth c5fb1a2ea8 google/rambi: Fix IASL warnings _CRS must return a value
The Touchpad and Touchscreen _CRS methods do not return an interrupt
value if the I2c busses that the devices are on are not in PCI mode.

Previously they didn't return any value if they weren't in PCI mode.
This patch has them return an empty resource template.

Fixes these warnings:
dsdt.aml 2813: Method (_CRS)
Warning  3115 -          ^ Not all control paths return a value (_CRS)
dsdt.aml 2813: Method (_CRS)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _CRS)

dsdt.aml 2832: Method (_CRS)
Warning  3115 -          ^ Not all control paths return a value (_CRS)
dsdt.aml 2832: Method (_CRS)
Warning  3107 -          ^ Reserved method must return a value
(Buffer required for _CRS)

Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:41:57 +01:00
Martin Roth d26c9d603e iwave/IWRainBowG6: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

Fixes IASL Warning:
dsdt.aml   1362:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Fixes IASL remark:
dsdt.aml   1353:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)

Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12515
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:38:24 +01:00
Martin Roth 21dbc2fc3c ec/lenovo/h8: Fix IASL warnings
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.

Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.

Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 -           ^ Not all control paths return a value (MHKP)

This was the only IASL warning in most lenovo mainboards.

Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:34:34 +01:00
Martin Roth 56033a9f2d superio/smsc/mec1308: Fix IASL warnings
The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.

ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device.  The FixedIO macro is only valid for
10-bit IO addresses.  Use the IO macro instead.

Thank you to recent IASL that allows for addition in the ASL file.  :)

Fixes these warnings:
dsdt.aml   2276: Device (SIO) {
Warning  3141 -           ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml   2390:    FixedIO (0xa00, 0x34)
Warning  3060 -                 ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml   2394:    FixedIO (0xa00, 0x34)
Warning  3060 -                 ^ Maximum 10-bit ISA address (0x3FF)

Lumpy now compiles its ASL tables with no warnings.  Re-enable
Warnings as errors.

Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 22:30:19 +01:00
Martin Roth b9434aa853 intel/d945gclf: Fix IASL warning and remark
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors

dsdt.aml   1445:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml   1454:  Method (_REG, 2)
Warning  3079 -             ^ _REG has no corresponding Operation Region

Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24 21:05:45 +01:00
Zheng Bao 2286138561 AMD/bettong: Add UART support
The function delay in uart8250mem.c is not enough for hudson. I guess
there are some problems in lapic_timer(). I uploaded a patch to gerrit
to show the way to enable UART feature.
http://review.coreboot.org/#/c/12343/4

Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to
enable this feature.

The UART is test at BIOS stage.

Since it is not a standart UART device, the windows internal UART driver
doesnt support it. I guess we need a driver to use it on windows.

Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11749
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-24 20:57:47 +01:00
Timothy Pearson 68130f506d amd/amdfam10: Control Fam15h cache partitioning via nvram
Add options to control cache partitioning and overall memory
performance via nvram.

Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:27:43 +01:00
Timothy Pearson b174667534 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12046
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-24 19:03:24 +01:00
Timothy Pearson 44e4a4e4db southbridge/amd/sr5650: Add IOMMU support
Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12044
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-23 23:02:16 +01:00
Martin Roth 40d073c3c5 google/rambi: Fix end comment in Kconfig
Change-Id: I3963d145f6d209e32256268259e93103c62809c5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-23 18:49:22 +01:00
Martin Roth 77c67b3d30 IASL: Enable warnings as errors
We've actually got more warnings now than when I first tested IASL
warnings as errors.  Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.

- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled!  *****
*****          Please fix the ASL for this platform. *****

Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-23 18:48:58 +01:00
Timothy Pearson caf0adac4f mainboard/asus/kgpe-d16: Update NB VDD upper voltage limit
Certain older Opteron processors use a higher (+1.2V) northbridge
voltage.  The existing code assumed the use of +1.1V northbridge
voltages and threw an alert when the older Opterons were installed.

Update the permissible NB voltage range to include both the 1.1V
and 1.2V Opteron processors.

Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21 00:00:56 +01:00
Timothy Pearson 7c55f374d1 northbridge/amd/amdht: Add support for HT3 2.8GHz and up link frequencies
Change-Id: Ifa1592d26ba7deb034046fd3f2a15149117d9a76
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12027
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20 23:49:38 +01:00
jiazi Yang 9c6d2b8f4c google/veyron_mickey: Update LPDDR3 configuration
This makes the same changes to the LPDDR3 configuration that
were made for Samsung modules:
- Enable ODT function
- Change DS to 40  from 34.3

BUG=chrome-os-partner:47416
BRANCH=firmware-veyron-6588.B
TEST=Boot on mickey elpida board

Change-Id: If8c729188803dd854dbbe80539fb228636b5eb9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3eb8bc31b9727b67a6b53b4370315010d9d6379
Original-Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1
Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311153
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311855
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 18:21:36 +01:00
Werner Zeh 9b7bb4911d siemens/mc_tcu3: Clear checksums in hwinfo
Clear the precomputed checksums in hwinfo as they
will be updated in manufacturing process.

Change-Id: I952ca8f1ca32831c4b296de633c0d58da111ccba
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-20 16:13:55 +01:00
WANG Siyuan 8b4f98a41f AMD Bettong: add README
This is the initial version of README.
AMD provides stable Bettong code in github. Add the link and bug fixed
list to README.

Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11737
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20 05:42:32 +01:00
WANG Siyuan 839d68f101 AMD Bettong: refactor PCI interrupt table
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.

Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-11-20 05:41:41 +01:00
Martin Roth f730e44baa google/veyron_danger & veyron_emile: Fix Kconfig warnings
These platforms needed to be adjusted to fix various Kconfig warnings.

Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting
MAINBOARD_DO_NATIVE_VGA_INIT.

veyron_emile needed a few symbols that depend on CHROMEOS to be moved
into a new config CHROMEOS section.  This matches the other CHROMEOS
platforms.

veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the
CHROMEOS symbol was set.

Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12462
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-20 00:29:19 +01:00
Martin Roth 267efa2bd0 google/lars & intel/kunimitsu: Fix Kconfig warnings
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section.
This fixes the kconfig warning:

warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects
EC_SOFTWARE_SYNC which has unmet direct dependencies
(MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE)

Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12460
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20 00:19:56 +01:00
Timothy Pearson 48bfcdf006 mainboard/asus/kgpe-d16: Fix I/O link detection
Change-Id: Ibefc9dc2e1e0267389eb8d716408bae6026ce084
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12024
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-19 20:23:11 +01:00
Michał Masłowski 9d0330f537 lenovo/r400: Add clone of Lenovo T400
The existing code for the Lenovo T400 works without changes on the
Lenovo R400.  Same HDA verbs are provided by Lenovo BIOS on both
laptops.

Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8393
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-19 12:46:40 +01:00
Felix Held df95b51ab6 pcengines/apu1: enable use of clkreq pins
only enable pcie gpp clocks when the corresponding clkreq pin is asserted

Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12353
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19 02:43:23 +01:00
Felix Held b06015b92e pcengines/apu1: disable unused clock outputs
disable unconnected FCH clock outputs to save some power

Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12082
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-19 02:43:12 +01:00
Timothy Pearson 0122afb609 cpu/amd/fam10h-fam15h: Update Fam15h APIC config and startup sequence
This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.

TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.

Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-18 17:14:48 +01:00
Zheng Bao 631c8a2690 AMD/Bettong: add FCH's GPIO, UART & I2C support
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled
by registers mapped at MMIO space.
This ASL code is used for Windows drivers.

TEST:
1. Boot Windows 8 or Windows 10.
2. Install AMD Catalyst driver.
3. AMD FPIO, UART and I2C can be found in device manager.
4. I2C passed Multi Interface Test Tool (MITT) test.

Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11750
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-18 17:02:28 +01:00
ZhengShunQian 71c0aa29fa google/veyron_emile: retrieve the MAC address from vpd
Emile has a on board ethernet.

BUG=chrome-os-partner:47465
TEST=vpd -s ethernet_mac0=001122334455
     build and check the MAC address

Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927
Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311900
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12452
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:19 +01:00
Douglas Anderson 7760a47892 google/veyron*: Pulse the i2c clock once if sda was low
On one particular TV the TV was holding SDA low when it came up.  It
would release the SDA when the SCL went low the first time.
Unfortunately the HDMI i2c port wouldn't transmit until the SDA was
released.

Let's detect this case and insert a bogus clock pulse to try to get the
other side to release SDA.

It's unclear why the kernel doesn't have this problem.

BRANCH=none
BUG=chrome-os-partner:46256
TEST=Insignia TV works now

Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114
Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309258
Original-Reviewed-by: Agnes Cheng <agnescheng@google.com>
Original-Commit-Queue: Agnes Cheng <agnescheng@google.com>
Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com>
Original-Tested-by: Agnes Cheng <agnescheng@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309546
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:16 +01:00
david c494c7d68d google/lars: enable wakeup from S0ix using headset button
Kernel needs to set Audio IRQ as wake capable.

BUG=None
BRANCH=None
TEST=emerge-lars coreboot

Change-Id: Ib7f0fc52baa006d992a2f91a63417e3f76817634
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 32d82ac48c6f830fbb09b776d0adaf6b7a727416
Original-Change-Id: I3fd70ac99c623a99b07fa1a185ebace8c1fc3d69
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312172
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12450
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:12 +01:00
david 2b7103cb0f google/lars: Enable wake from touch pad
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.

BUG=none
BRANCH=none
TEST=emerge-lars coreboot

Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69
Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311890
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12449
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:09 +01:00
Duncan Laurie 3db94686e5 google/chell: Turn on keyboard backlight in romstage
Use the keyboard backlight to provide indication that the system is
booting.  This is useful for determining that a system is in S0 and
is running BIOS code.

BUG=chrome-os-partner:47435
BRANCH=none
TEST=boot on chell and see keyboard backlight come on early

Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb
Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:29:05 +01:00
Duncan Laurie 4aca1477cb google/chell: Set USB current limit to 2A
The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging
from the Type-A port.

BUG=chrome-os-partner:47172
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe
Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312451
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12447
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:59 +01:00
Aaron Durbin d49d42f629 google/chell: disable power rails in sleep path
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.

BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built for chell.

Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c
Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312321
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:49 +01:00
Aaron Durbin ce6c35699b google/glados: disable power rails in sleep path
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.

BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.

Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e
Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312320
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12445
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 16:28:46 +01:00
Nico Huber 8a44b0b18c mb/roda/rk9: Fix cbmem recovery on resume path
By calling cbmem_recovery() with `0`, we rewrote the cbmem table even
on the resume path. By that, we lost the OS' resume vector and ended up
loading the payload.

Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12420
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-18 15:12:42 +01:00
Martin Roth 2035d9aa94 newisys: Remove mainboard directory and Kconfig files
Since there are no longer any newisys mainboards, remove the directory
and Kconfig files.  This removes the Kconfig warning:

mainboard/newisys/Kconfig:3:warning: config symbol defined without type

Change-Id: Icb2e782173166a26fa261f6cfb81b665a846931e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12423
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13 01:30:32 +01:00
Saurabh Satija 66aae6d3ba intel/kunimitsu: This patch enables wakeup from S0ix using headset button.
Kernel needs to set Audio IRQ as wake capable.

BUG=chrome-os-partner:47450
BRANCH=NONE
TEST=System wakes up from S0ix by pressing headset buttons.

Change-Id: I0f89d05b4c5449e5e3277dde938d941e4ad8cbea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65bf434f7c7e1662211f9c8bf61eeb4f41bdc675
Original-Change-Id: I7b5b564023044b4458eb0976488018b3226f4c70
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12414
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-13 00:53:04 +01:00
Timothy Pearson 795ee1a6cd mainboard/asus/kgpe-d16: Add sata_alpm CMOS option
Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12409
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 21:22:11 +01:00
Timothy Pearson ef62eacb3b mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option
Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-12 21:21:15 +01:00
Zheng Bao 861f920cdf AMD/Mullins: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if devices actually use
no-msi.

Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12363
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12 09:26:08 +01:00
Zheng Bao 266609968b AMD/Kabini: Fix the interrupt routing
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if the devices actually use
no-msi.

Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12362
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-12 09:25:45 +01:00
Timothy Pearson f902722357 mainboard/asus/kgpe-d16: Add missing IRQ routing for PIKE card
Change-Id: I6eba36dad71a2a2713181382484dc0e0976e1dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11988
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-12 00:55:47 +01:00
Timothy Pearson ab87c4db30 mainboard/asus/kgpe-d16: Add maximum_p_state_limit CMOS option
Change-Id: I9a7049fd5601da10a954e02427ad59189fa93fa9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12407
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-11 22:01:32 +01:00
Timothy Pearson fe2ae61906 mainboard/asus/kgpe-d16: Set SP5100 subtype
Change-Id: If839fd71ed12c1fe27aeab374e242a6855737f5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11994
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 20:50:54 +01:00
ZhengShunQian 0dc117aa5d google/veyron_emile: adjust to the spec of emile
o. Make some gpio changes base on Emile spec.
o. Init sdmmc function.
o. Revert cpu freq reducing in recovery mode since Emile
   have more effective thermal than Mickey.
o. Revert the changes of lpddr3-samsung-2GB config.

BUG=chrome-os-partner:46658
TEST=build and boot on Emile
BRANCH=veyron

Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999
Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307651
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:43 +01:00
Archana Patni 278f20e88d intel/kunimitsu: Enable wake from touch pad.
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.

BUG=chrome-os-partner:43491
BRANCH=none
TEST=Build for kunimitsu. Tested wake from touchpad on a reworked kunimitsu board.

Change-Id: I4347be8f7a4552c6b583f0797fab64045aa9792e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c21f3b5df21d96937975dc20ee5e2f83fb3d75e
Original-Change-Id: I76e69bdba81ec22ae67c7cff3a807cea8c54a5b3
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311007
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:41 +01:00
ZhengShunQian e4d438e8dc google/veyron_emile: Add new board of veyron
This is a copy of mickey and renamed.

CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build coreboot
BRANCH=veyron

Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde
Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307620
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:36 +01:00
Duncan Laurie b87f2a55a2 google/chell: Add chromeos.c to verstage
When enabling CONFIG_SEPARATE_VERSTAGE the functions in chromeos.c need
to be put into verstage.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=enable SEPARATE_VERSTAGE and build for chell

Change-Id: Ic58a6e383806a7a64b9af760e194fddf15c645f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 403f0707074802371237beecf1941034c1612f10
Original-Change-Id: Ib1154869974337b53a64efa5892a83ecd81973b8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310928
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:31 +01:00
Duncan Laurie c1f864e257 google/chell: Disable Deep S3
In order to wake from trackpad and wifi we cannot enable Deep S3.

BUG=chrome-os-partner:46289
BRANCH=none
TEST=wake from trackpad on chell

Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a
Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311306
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12392
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:23 +01:00
Duncan Laurie a85f3ae852 google/chell: Add SPD for new memory type
This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be
used in the EVT build.

BUG=chrome-os-partner:47346
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10
Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311214
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12391
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:10 +01:00
Duncan Laurie 0ca1b2f547 intel/skylake: mainboards: Add MAINBOARD_FAMILY kconfig entry
The family variable was not being set yet for skylake, add this
to the current boards.

BUG=chromium:551715
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec
Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311213
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:44:00 +01:00
Duncan Laurie b13845191f google/chell: Fix USB port assignment again
The net names are offset by 1.  My board is not stable enough
to really test all of these yet...

BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot

Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11 20:43:52 +01:00
Timothy Pearson c7e4c27c3b mainboard/asus/kgpe-d16: Add SATA AHCI mode CMOS option
Change-Id: If7b6062fd4df16ae2864b5d9adfdd19c4356691c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12400
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-11 20:33:13 +01:00
Timothy Pearson 83abd81c8a cpu/amd: Add CC6 support
This patch adds CC6 power save support to the AMD Family 15h
support code.  As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.

Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.

Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 18:45:14 +01:00
Urja Rannikko b31017b3ac asus/k8v-x: Add more subsystem IDs to device tree
This is an attempt at better compatibility with driver matching etc.

Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 09:12:25 +01:00
Urja Rannikko 406834717a asus/k8v-x: Add PIRQ tables to init PCI IRQ config
Pulled getpir from the attic and used data provided by it
to create the table a bit more programmatically and
added the AGP slot so the video card is given an IRQ

Change-Id: Id3dc1a77ac6382405f5f36707994287e84e1168b
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12350
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 09:12:19 +01:00
Werner Zeh 737c54d4d3 fsp_baytrail: Add macros for legacy GPIO output set up
Up to now the GPIO set up macros for input sets up GPIOs to be
mapped to memory space while macros for outputs sets up GPIOs
to be mapped to legacy io space. This patch adds two additional
macros for legacy output definition and changes the old macros
to memory space mapping.

In addition, the intel/minnowmax mainboard is modified to use
the legacy macros for outputs to ensure this mainboard stays
unchanged in terms of functionality.

TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux.

Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12340
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-11 06:42:01 +01:00
Timothy Pearson 74e03a4fdd mainboard/asus/kgpe-d16: Enable CC6
Change-Id: Iae1cbe7d3a6471561abfdb8e182bc764c38bb222
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11978
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-11-11 06:39:13 +01:00
Timothy Pearson df1fb9c05f amd/amdmct/mct_ddr3: Use training values from previous boot if possible
DRAM training accounts for most of the romstage startup time, yet
if the hardware configuration has not changed from the previous boot
the previously discovered training values are still valid.  Use them
if the DIMM configuration has not changed since the last boot.

The SPD values of all installed DIMMs are hashed and stored in the S3
resume data area of the main system Flash device.  If a DIMM is changed
the hash will almost certainly change as well, forcing retraining on next
boot.

Change-Id: I37ed277b16476d38e4af76c6ae827a575c6b017d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11976
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-11 06:14:20 +01:00
Timothy Pearson 95b97848cc mainboard/asus/kgpe-d16: Set correct supported SATA port count
Change-Id: Ia5c00f07de81d409e6215cc0944d64d00e47b795
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12401
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-11 02:47:43 +01:00
Timothy Pearson f89a05ed9f southbridge/amd/sb700: Indicate iSATA/eSATA port type
Change-Id: I8ee757d07c82c151b36def6b709163ff144d244f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11984
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 02:07:42 +01:00
Timothy Pearson 2b206775fa mainboard/asus/kgpe-d16: Properly initialize SB700 SATA PHYs
Change-Id: I5323462dcb8a4e84786be38cc85070eb48d4a31d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11982
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 02:01:47 +01:00
Stefan Reinauer 7593bda5a8 [REMOVAL] tyan/s2875
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I36c2b0290f95f4c0f6bed6a7427fb3aab968d4da
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12376
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 23:04:13 +01:00
Stefan Reinauer 39456c2cca [REMOVAL] tyan/s4882
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I866440595a0a38b65ce037dc9a1f7e4c02c6beb3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12385
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:50 +01:00
Stefan Reinauer 1115625595 [REMOVAL] tyan/s4880
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I41d1f9eac2f4c37bec4d046a68f3f1cf95b51703
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12384
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:39 +01:00
Stefan Reinauer 9fc5e0bc89 [REMOVAL] tyan/s2892
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Idd6011302d2164275fe01954ad3e4e13474ec7a9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12382
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:10 +01:00
Stefan Reinauer 7c29040442 [REMOVAL] tyan/s2891
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I915d5dd4a095b84023a19c9a0474634320207a08
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12381
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:35:00 +01:00
Stefan Reinauer 52c0180dcc [REMOVAL] tyan/s2885
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Icfdcc5d6043987e22ef9b4db84847d62c91bd305
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12380
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:34:51 +01:00
Stefan Reinauer c5ab0979f6 [REMOVAL] tyan/s2882
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ie44a3c46b82e77028921339c50ae4c176e38055c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12379
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 21:34:22 +01:00
Zheng Bao 3844d9a30c AMD Bettong: Add a special case for SPD address of rev F
Rev F's SPD address is different from other revision.

            0   1
Channel A  A0  A2
Channel B  A4  AC

Change-Id: I620d1f9c295f9a0e30e3821ea36a05dd9f7d3495
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12342
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 21:24:46 +01:00
Stefan Reinauer 8993df1d16 [REMOVAL] tyan/s2895
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I9099f90c073197cc95bb9630788016b7b8221922
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12383
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:21:19 +01:00
Stefan Reinauer f3601c406f [REMOVAL] tyan/s2880
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ifd1dfa35ae13ec01d932250994086edebece924d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12377
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 21:20:56 +01:00
Stefan Reinauer 502a7e41df [REMOVAL] tyan/s2881
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Idfec80ce79c906717e679d6576dc94e71da994c9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12378
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 21:16:42 +01:00
Stefan Reinauer 9f21230e36 [REMOVAL] tyan/s2850
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ibf3849dcd7a1ef1d8bc5dfc864172a8254a64b6f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12375
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:15:12 +01:00
Stefan Reinauer f76de841f1 [REMOVAL] tyan/s2735
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I460208c18964857be73d9a4449ecfd872ccad98a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12374
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:15:04 +01:00
Stefan Reinauer 63d5088bb6 [REMOVAL] iwill/dk8s2
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I4a942150590fb69ff97279ff2b48b3be83abafa4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12372
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:14:53 +01:00
Stefan Reinauer 029f3550ef [REMOVAL] digitallogic/adl855pc
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I5b0fb633b7611e2a69aeb33cd31ca8fd4a83592c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12369
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 21:14:31 +01:00
Stefan Reinauer bb3934c3c2 [REMOVAL] iwill/dk8x
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I1913ca75aa6f2a2c6b97d49faaabc16afd2799f5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 20:23:07 +01:00
Stefan Reinauer b38e9a962e [REMOVAL] newisys/khepri
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: If0e0a7f69b77cf4bcab4c0dcb58a153485380069
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12373
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 20:22:45 +01:00
Stefan Reinauer 43f6fd3827 [REMOVAL] ibm/e325 + ibm/e326
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: I8854c31f242c13b6f91901452f7eb7ce0ef0b255
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 20:21:16 +01:00
Stefan Reinauer 7804bb002f [REMOVAL] arima/hdama
As announced in http://permalink.gmane.org/gmane.linux.bios/81918
I am removing all boards older than 10 years from the tree.

Change-Id: Ic71d8a9137f0bd2a0cc7571a43f9dddb50168d8d
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12368
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2015-11-10 20:17:17 +01:00
Patrick Georgi 47b6a825a7 mainboard/**/irq_tables.c: Remove reference to getpir
The obsolete and removed getpir utility remarked in its output that the
data is autogenerated. The tool was removed because it wasn't very
reliable, so there's no need to point that anymore.

Change-Id: I5d624931ba7872b1fefa8fa3c270ae7367e069fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12354
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-10 14:11:06 +01:00
david dc5b10bd92 google/{chell,lars}: Enable Fan control support
Copy from the CL https://chromium-review.googlesource.com/#/c/307028/
(I40c540dad32beefe249f025b570c347d3ad08c36)

BRANCH=None
BUG=None
TEST=emerge-lars coreboot

Change-Id: I131fb729661f0f3bfd198cdf238c627bf38a46a5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70d471c507d12924466979c93742944975a03f27
Original-Change-Id: I0128dc65110ba363185db9c2aca5cdb140c344c2
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310394
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12344
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-10 14:09:43 +01:00
zbao dcbb1287a7 AMD/Bettong: Set on-board eMMC as SD 2.0
The on-board eMMC is designed as 2.0. If it is set as 3.0,
it can not be detected.

Change-Id: I9fd913f76535e65c1672924ebdeba3d35dea59cc
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-10 10:37:51 +01:00
Zheng Bao fbdfed01eb AMD/Bettong: Memory configuration for DDR3 and DDR4
1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4.

2. DDR4 uses different memory configuration in AGESA.
Pass memory configuration parameters in agesawrapper_amdinitpost.

3. Tested on Rev C and Rev F.
Both of them can boot to Windows 8 and have the correct memory size.

Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11733
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 10:34:51 +01:00
Zheng Bao f3aea52a70 AMD/Bettong: add function to read board version
Bettong uses 3 GPIO(5-7) pins to identify board.
The GPIO ports are mapped to MMIO space.
The GPIO value and board version are mapped as follow:
GPIO5 GPIO6 GPIO7 Version
  0     0     0      A
  0     0     1      B
  ......
  1     1     1      H

Change-Id: I72df28043057d8c4ccc4a2e645011ca5379e9928
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11732
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-11-10 10:34:32 +01:00
Felix Held 69e89f249f asus/kgpe-d16: fix DIMMSetVoltages
The RAM voltages can be set per socket, which contains two nodes.

Only reset the allowed voltages per socket before processing a new socket and
not after every node.

Change-Id: Ia0e47676c7a3eebd56a17ab6de0e9690bf8cf703
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12297
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-11-10 01:45:09 +01:00
Jonathan A. Kollasch b65fd3e305 sunw/ultra40m2: initialize hardware monitor and fan control
Change-Id: I3fbb897feb68d899e5dec075a09d0dd605eca5ce
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12309
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-10 00:58:19 +01:00
Jonathan A. Kollasch 7c62e17f2e mainboard: Add Sun Ultra 40 M2 port
The Ultra 40 M2 is a dual Socket F workstation with MCP55/IO55 chipset,
DME1737 superio and onboard Firewire.  This board port is for family
0Fh (K8) processors.

Due to existing bugs, having memory on the second node will cause
raminit to fail.

Change-Id: I5b62ade908ffeb80e22f14edbe4c1ec04880bd30
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12304
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-10 00:57:55 +01:00
Jonathan A. Kollasch d9247828fd mainboard: copy nvidia/l1_2pvv to sunw/ultra40m2 and rename
Change-Id: Ia275a697caa73168553b5d588d54df651e0539d7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/12303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 00:57:45 +01:00
Timothy Pearson 59597ead1f mainboard/lenovo/t400: Add initial hybrid graphics support
TEST: Booted T400 with Intel/ATI hybrid graphics in integrated
mode with native Intel graphics init and verified integrated
panel framebuffer functionality in SeaBIOS and Linux.

Change-Id: I37e72c5dad0d7ab3915cc3d439ae9a4a9b3787e3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9319
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2015-11-10 00:45:40 +01:00
Urja Rannikko 9849f35459 asus/k8v-x: set superio ROM ctrl reg to enable writes
This is required for flashrom to work...

Change-Id: Icc0a52e0ca103c897d96fa8f3cf83b30780c7b49
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12349
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 00:42:21 +01:00
Paul Menzel 8a3ff6aa34 mainboard: Remove empty mainboard.c files
All the deleted mainboard files contain no code besides some print
statements denoting, that the init is executed.

If such statements are desired, this should be done in common code so it
does not have to be added to each mainboard.

Therefore, also delete files with just print statements.

Change-Id: I379e4b1e1b1725648c6231bc6954ac3cc655a596
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12355
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-11-10 00:40:10 +01:00
Marc Jones 3b0a626edc mainboard/intel: Add Stargo2
The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.

Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 00:25:14 +01:00
Timothy Pearson e619a9ac9b mainboard/asus/kgpe-d16: Add initial Family 15h CPU support
Change-Id: I76f74ed4ae383f8b1f57eaaa2e025035002430f2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11967
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-09 20:24:42 +01:00
Furquan Shaikh fdb3a8d07d arm64: Remove cpu intialization through device-tree
Since, SMP support is removed for ARM64, there is no need for CPU
initialization to be performed via device-tree.

Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11913
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:29:35 +01:00
Furquan Shaikh b3f6ad3522 arm64: Remove SMP support
As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove SMP
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.

Change-Id: Ife24d53eed9b7a5a5d8c69a64d7a20a55a4163db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11909
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:29:14 +01:00
Aaron Durbin 1148786c05 arm64: remove spin table support
As ARM Trusted Firmware is the only first class citizen for
booting arm64 multi-processor in coreboot remove spintable
support. If SoCs want to bring up MP then ATF needs to be
ported and integrated.

Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11908
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07 03:28:50 +01:00
Kyösti Mälkki 82860f8549 AGESA BiosCallouts: Remove cast
This cast only hides errors in matching the API properly.

Change-Id: Ic396dfb572a50ac5ce5c1c83424e1f17f15bad1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/12270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-06 20:59:52 +01:00