set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
"usb2_ports[7]" for internal bluetooth device was configured as
'USB2_PORT_EMPTY' mistakenly in previous patch, so we need to enable
it again.
BUG=None
BRANCH=firmware-dedede-13606.B
TEST=Built and verified BT device existence with lsusb
Change-Id: Id2900152e23bbc2f454d064dc86a9e45e934ea0f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds explicit initializations for the remaining named display
(power) control GPIOs to the bootblock GPIO init code. These pins are
usually mapped to pins that are already configured to pull-downs on
power-on reset so this wasn't really required, but we have already moved
them around so often that you never know when EEs might one day move
them to a pin with a different power-on reset configuration, so it's
better to be explicit.
In one particular case, GPIO(67) (used by CoachZ rev1+ but not by
anything else for the EN_PP3300_DX_EDP pin) is not actually a pull-down
on boot, even though that is claimed by the datasheet. This is likely
due to the fact that it can serve as the SPI_HOLD pin for the boot flash
QSPI bus, so even though our board's boot flash doesn't really use that
pin, it seems that the boot ROM still configures it as such.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I533baa962d2dfc87cfa510f442ed2e8912e0e5b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: mturney mturney <mturney@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This conflicts with the MSTH i2c_tunnel.
BUG=b:175146875
BRANCH=zork
TEST=Boot trembyle and inspect ACPI tables.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It's easier to understand what these symbolic names mean rather than
using the constants; the static.c will will end up (indirectly)
including `soc/usb.h` therefore the macros are in scope here.
Change-Id: I5ef977a05a2522e177f32c99bfab74f9288ae869
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The only difference is an additional include that is no longer needed.
Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to repeat the same code on every board.
Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.
TEST=Verified that UPDs are configured correctly with and without this
change.
Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
All Broadwell boards only use the `mainboard_pre_raminit` function to
call `mainboard_fill_pei_data` and optionally `mainboard_fill_spd_data`.
Move the declaration and weak definition of `mainboard_fill_spd_data` to
platform code, replace the call to `mainboard_pre_raminit` in romstage.c
with calls to `mainboard_fill_pei_data` and `mainboard_fill_spd_data`,
and delete all other instances of `mainboard_pre_raminit` for Broadwell.
Finally, delete now-empty romstage.c and spd.h files from mainboards.
Change-Id: I3334b20bd7138bb753b996a137ff106e87c6e8a5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Make it optional and change its signature.
Change-Id: I4b5f3fb08e8954514ebf39e72c95aa62d66856d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This allows us to drop many now-redundant Kconfig options.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
The default configuration file also remains identical, as expected.
Change-Id: I20b0200550508679bf2533342ce918b221dcf81e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The VR config and S0ix options are now specified for the CPU chip.
Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code to read the SPD file and index it is not variant-specific.
Change-Id: Iaee0a77934a45c65bf32dd0dba23cec654abc0b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
It is identical for all variants that have it.
Change-Id: Iec3a5f036d9b760d1075059f2db1480b1c76273e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
They are part of the same line, so merge them.
Change-Id: I969ce91f7a5f16a85750c140eaa444d7923b2014
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Factor out common DRAM SPD definitions and relocate SPD GPIO macros.
Also factor out common function definition. Drop now-empty headers.
Change-Id: Id05ba6c9cea27fbad5ee831f033d0de43717847e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I279956f30cbb6fb031cdfe6aaa09b644b6b7d3e7
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49427
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do LPC/eSPI pad configuration at board-level to match other platforms.
This is done by adding missing pads to the bootblock gpio table.
The soc code gets dropped in CB:49410.
Change-Id: I95993b1bd4f1fd8b4ac7b21fb89ec4d196b0240a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49412
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I62ffbe36bd7b7675aa0f41a8c6e9214d04ad4ae5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49428
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early gpio table for the board as a
first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I6fedcebea3bb31d992bac1e3b21382fea93a8b82
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49429
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: Ieeb738afd54e77ee853ee109009f611411aa0d4a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49426
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I5482f44b361925b7d2dbcbf1065c1be035c68b0b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49424
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).
Change-Id: I7dcf88d61c305f0598a0a79f8cfa46ef5009564b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.
The soc code gets dropped in CB:49410.
Change-Id: Ie33bae481f430a1c4410a0a4e2b2a34a3e78adaa
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49411
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow MRC training in SA GV.
BUG=b:177779469
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Idc9f634135b489450f53f8cd28d80649309d0f70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Assigned USB2 port to type-c use.
BUG=b:177483060
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I9bd820406124927d56296508be05033217c0d472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49638
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct GPIO settings as below reason:
1. GPP_G7 not being used but set to NF.
2. GPP_C22 and GPP_C23 is set to NC but internal pull down to 20K
BUG=b:177283756
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc
Change-Id: Idf25674efa2336bde98c5abaff278484fd71ea8b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Correct GPIO settings as below reason:
1. GPP_D19/GPP_D20/GPP_D21 not being used but set to NF.
2. GPP_B7 should configure as WWAN SAR detect ODL, but set to NC
BUG=b:175932166
BRANCH=dedede
TEST=emerge-dedede coreboot chromeos-bootimage and boot into emmc
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id7780d5332551ed3fd20ef14f8b5d31164f16385
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).
Change-Id: I795b8da3c5e1efb51c8fe4673f025839a1c630bc
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).
Change-Id: I2f484d232a46214ff98168f41f96d56b047892e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).
Change-Id: I67bdd9a96928b77a9a178afea7dab03dc370312c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Do early pad configuration in early bootblock before console init, to
make the console work as early as possible. The board does not do any
other gpio configuration in bootblock, so this should not influence
behaviour in a negative way (e.g. breaking overrides).
Change-Id: I342b9217af0288a3b525e629aac791eb0f880442
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The BACKLIGHT_ENABLE pin on this board unfortunately defaults to a
pull-up on power on, meaning the backlight is immediately enabled. Best
we can do about that is to turn it off again early and wait until it is
actually correct in the panel power sequence to turn it back on.
Some panels want an explicit 80ms delay after training the eDP
connection before the backlight is turned on (this is probably just to
avoid temporary display artifacts, but whatever). We don't want to
busy-wait that extra time, so instead just delegate turning on that GPIO
to the payload (which is also in charge of the backlight PWM already).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id8dafbdcb40175fbc9205276eee698583b971873
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
In order to use the function smbios_mainboard_version()
to query the board revision from the EC.
we need to select GOOGLE_SMBIOS_MAINBOARD_VERSION.
BUG=b:177818769
TEST=1. emerge-volteer coreboot chromeos-bootimage
2. flash the image to the device and check board rev
by using command `dmidecode -t 1 | grep Version`
Change-Id: I2474ee03845356d0775f6da25274f696ad33f935
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Create the sasukette variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:175848514
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SASUKETTE
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I0a554efe0919dc2f5880f0f7817a37bd4be88ed9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change enables LTE modem for sasuke.
- Add LTE modem device into devicetree
- Add GPIO control for LTE modem power on and off
BUG=177177967
TEST=Built and verified modem device existence with lsusb
Change-Id: I34ba8ab00b73f24d1786ab014e9981b172a63a27
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49163
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF paramerters from thermal team.
1. PL1 max =5.8W
2. PL1 min =3.8W
3. PL2 =20W
BUG=b:177249297
BRANCH=dedede
TEST=build image and verified by thermal team.
Change-Id: I19654b65613817ebecf979ce7ac4f76d370ebdc2
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Dalboz variants do not use an MST hub; remove the i2c tunnel for it.
That bus is actually connected to the battery on these devices, which
should not be exposed to the AP.
BUG=b:175658311
TEST=builds
BRANCH=zork
Change-Id: If1714a5c441bf185efd2517c7c94e57b5f351f5a
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49628
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the USB2 port 3/4/9
1. USB2 port3 assign to WWAN, and elemi have no WWAN.
2. USB2 port4/port9 connect to Type-C C1/C0
BUG=b:177483059
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I9affc69cc325b5eb0219b50bfe46f66eb0bb2016
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49473
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.
Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.
Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.
Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).
Change-Id: I5e07584d7857052c7a9388331a475f5a073af038
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Two configuration files are added:
1. H9HCNNNFAMMLXR-NEE-8GB: new byte mode
2. MT53E1G32D2NP-046-4GB: new single rank mode
Also initialize the rank number field 'rank_num' for all configs.
BUG=b:165768895
BRANCH=kukui
TEST=DDR boot up correctly on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: I1786c1e251e8d6e110cbdce79feeb386db220404
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49108
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fw_config field SPI_SPEED is not used for zork devices.
To define SAR config, use the fw_config bit[23..26].
Then vilboz can loaded different WiFi SAR table for different SKUs.
BUG=b:176858126, b:176751675, b:176538384
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I5ba98799e697010997b515ee88420d0ac14ca7ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Based on voema schematics, two USB2 ports 3 and 5 are assigned to type C
connectors on Voema board.
BUG=b:177483061 b:172535001
TEST=Build and boot Voema.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I12cef85595e511801ab9c563ae4aa26e25875679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LTE module is not expected to be powered off during warm reset. Hence
configure the LTE_PWR_OFF_ODL (GPP_A10) gpio pad reset configuration to
PWROK and set the TX state to 1.
BUG=b:163100335
BRANCH=dedede
TEST=Verified through the waveforms that power sequence is meeting the LTE module requirements.
Change-Id: I8676da6186559288aabe078b6158fc01075c7b41
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
LTE module used in metaknight has a specific power on/off sequence.
GPIOs related to power sequence are:
* GPP_A10 - LTE_PWR_OFF_R_ODL
* GPP_H17 - LTE_RESET_R_ODL
1. Power on: GPP_A10 -> 20ms -> GPP_H17
2. Power off: GPP_H17 -> 10ms -> GPP_A10
3. Warm reset: GPP_A10 keeps high, GPP_H17 goes low at least 2ms
Configure the GPIOs based on these requirements.
BUG=b:173671094
TEST=Build and boot Metaknight to OS. Ensure that the LTE module power
sequence requirements are met.
Change-Id: Ibff16129dfe2f1de2b1519049244aba4b3123e52
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The default value is not sufficient to correctly configure the Type-C
ports as it has all ports disabled by default. On Volteer ports 0
and 1 are enabled so setting this value to 0x3 and correctly
keeping the IomPortPadCfg values at 0 for ports that have a
retimer and ports that are not configured. These values were set
to 0x90000000 to avoid s0ix issues which arose from the UsbTcPortEn
value being incorrect.
BUG=b:159151238
BRANCH=firmware-volteer-13672.B
TEST=Built image for Voxel and verified that s0ix cycles complete
without any issues
Change-Id: Ib4f2bd0f68debd4e97ccaab9e1d8a873dc4e4d9f
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48814
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the functions that get called by the coreboot console
initialization code aren't in the SOC-specific code anymore, the SOC's
uart.c can be included unconditionally in the build now. This also
replaces the STONEYRIDGE_UART Kconfig option with the common
AMD_SOC_CONSOLE_UART one.
Change-Id: I09c15566a402895d6388715e8e5a802dc3c94fdd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update PL1 min and max values for Delbin systems
BUG=b:168958222
BRANCH=None
TEST=Build and verify on delbin system
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: I2152f0dbeb0ae463b78464571b6c434830f0082a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers.
BUG=b:174338903
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I875f6b32c4053ef6d23ad7606cd35a129a78c306
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49290
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initiate overridetree.cb based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I31e5ac1703476083ac71dac30b0a3299b38384c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Follow latest schematic to fill gpio table.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a983605b5139ff8510a0cf225e6564b9215cb1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board.
This update configures these USB2 ports for Type C which will allow USB2
port reset message upstream from PCH to CPU to recover a USB3 device
that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Voxel board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The FW config takes 2 bits for USE_FAN[27,28].
So FW_CONFIG_SHIFT_WWAN value should be 29.
BUG=b:174121847
BRANCH=zork
TEST=build vilboz
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ica6d04f9c48aa0800189283608bf57416ac75cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49236
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:171757619
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Change-Id: I37390535e263b4b9547ad7307278e3360ba836bd
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
This will allow CSE RW FW updates and also fixes the problem where no sound is emitted from the speakers.
BUG=b:176536593
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: Wayne3_Wang <wayne3_wang@pegatron.corp-partner.google.com>
Change-Id: I69962a5b7c7c464280b35c834f7ee1c9b77db6fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While FORCE_PWR is set high, it prevents retimer from entering low power
state. S0ix failure occurs while USB4 Gatkex is connected on Port-0.
This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be
toggled by kernel through DSM method while updating retimer firmware.
BUG=b:174166586
Cq-Depend: chromium:2594438
TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.
Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of hard-coding function names in strings, use the __func__
constant for better maintainability.
Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a space after each comma to fix linter issues.
Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
