This patch was tested with the following card:
IDE interface: Silicon Image, Inc. PCI0680 Ultra ATA-133 Host Controller [1095:0680] (rev 02)
Change-Id: I988b73684b54942d8ee6e44a9319dcc54086fca7
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/12171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: I9c547ae177dc95030c8c545a302a2349bf1c9cf8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 07b6465f0b3e18d30647959b8e1db44d8647cf90
Original-Change-Id: I49bf7f1bd2edb32ffe9cc22f6fce1348434fd234
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301243
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12152
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
The 1392MHz value used to throttle the RK3288 earlier was somewhat
arbitrary. This patch brings the throttling in sync with the operating
points specified in the Linux device tree for RK3288.
BUG=chrome-os-partner:42054
BRANCH=none
TEST=Saw print statement in image.serial.bin indicating that APLL
was set to the desired frequency.
Change-Id: Ibe570267bbfe23f010ad5e1ea651356291b9c63c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a146f23b13cb0f6da93ada65648cf33ecfaaa7d6
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I6bcdb5fd6ffa3f9a22e79c519bdb7980492e2318
Original-Reviewed-on: https://chromium-review.googlesource.com/302633
Reviewed-on: http://review.coreboot.org/12137
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This applies CL:300617 to Rialto to down throttle further in
recovery mode.
BUG=chrome-os-partner:42054
BRANCH=none
TEST=Saw print statment in recovery mode with image.serial.bin,
device only got mildly warm after several minutes (not hot).
Change-Id: I08b6024d31c83c6bbd8c8d9d9a07adc9835e81fd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74eb9143fbe13df5f386185eab9e5ba9df27cadf
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9e57d826750cb523c115332fa13a6143bcff7449
Original-Reviewed-on: https://chromium-review.googlesource.com/302631
Reviewed-on: http://review.coreboot.org/12135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Id2230ecd800b138b6ccbbac318e71c9edf076c75
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12116
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: Ib078b21ddf0493ad6795c6ab79125b3917ff7049
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12115
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change-Id: I45b3412263507d92f443743d2ee63c9a8ef94795
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12114
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The possibility of adding a bootsplash image to ROM should be independent
from VGA_ROM_RUN and VESA menuconfig options.
For example, the stored image could be saved in CBFS not for coreboot
but for later use in SeaBIOS.
Change-Id: I3a0ed53489c40d4d44bd4ebc358ae6667e6c797f
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/12129
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
LPC decodes were not enabled, leading to a failure of POST 80 cards
and similar debugging devices. Enable the relevant LPC decodes
to allow debugging.
Additionally, the SMBUS controllers were not properly set up.
Enable both the primary and auxiliary controllers.
Finally, K10 and higher CPUs were hanging during boot due to
a misconfigued IOAPIC. Properly configure the IOAPIC.
Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12177
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Certain devices, such as the Intel 82575GB, contain multiple nested
PCIe bridges (for example the PES12N3A). Coreboot does not set
the primary bus number of the lower bridges, causing upstream
forwarding failure. This in turn causes coreboot to fail to find
the lowest devices (in this case the NICs), and as a result the
required resources are not allocated and the NICs do not function.
Change-Id: I4fd3aa21a04dbe89ac6a5995e7707af914d432b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12186
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
Update mainboards using the w83795 sensor device with sane default
values. Note that in some cases the defaults may vary from the
defaults provided by the old driver, for example the default fan
speeds and control modes have changed as I do not have any information
on the correct sensor to fan mappings for these boards.
Change-Id: Id2ad6222d7a0f29483b022fa097d7d098c6b4122
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12124
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Add full support for fan control, fan monitoring, and voltage
monitoring. Fan speeds and functions are configurable via
each mainboard's devicetree.cb file.
NOTE: This patch effectively rewrites large portions of
the original driver. You may need to re-verify correct
operation on your hardware if you were using the old
driver code.
Change-Id: I3e246af0e398d65ee43ea708060885c67fd7d202
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11936
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Certain devices (such as the LSI SAS 2008 controller) do not
respond to PCI probes immediately after link training. If it
is known that such a device is likely to be installed allow the
mainboard to insert an appropriate delay.
Change-Id: Ibcd9426628cacd6f88e6e3fcbc2b3eb7e3a92081
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11991
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Tested-by: build bot (Jenkins)
If an SMBUS device in devicetree.cb is placed under a parent device
that does not have an SMBUS controller, coreboot will enter an
infinite loop and hang without printing any failure messages.
Modify the loop to exit under these conditions, allowing the failure
message to be printed.
Change-Id: I4c615f3c5b3908178b8223cb6620c393bbfb4e7f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12131
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
The hudson chipset has 4 USB controllers, the fourth is USB1.1-only and
(presumably) not used very often, add support for hiding it:
00:10.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03) USB1 (3.0, XHCI)
00:10.1 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB XHCI Controller (rev 03)
00:12.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB2 (2.0, OHCI+EHCI)
00:12.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:13.0 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB3 (2.0, OHCI+EHCI)
00:13.2 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB EHCI Controller (rev 11)
00:14.5 USB controller: Advanced Micro Devices, Inc. [AMD] FCH USB OHCI Controller (rev 11) USB4 (1.1, OHCI only)
Change-Id: I804e7852fd0a6f870dd118b429473cb06ebac9a4
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7355
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On my Foxconn nT-A3500 on cold boot the board doesn't survive the soft
reboot in the UsbRxMode path and the vendor bios doesn't touch this
Cg2Pll voltage setting either.
The fixup code for UsbRxMode in src/vendorcode/amd/cimx/sb800/SBPort.c
doesn't seem to "CG PLL multiplier for USB Rx 1.1 mode", but rather
lowers the Cg2Pll voltage from the hw default of 1.222V to 1.1V
by setting Cg2Pll_IVR_TRIM in CGPllConfig5 to 1000.
See also USB_PLL_Voltage which is only used in the UsbRxMode code path.
However if this is already the efuse/eprom default for the SB800 then
UsbRxMode is a no-op, so whether or not it gets executed depends on the
very exact hw revision of the southbridge chip and could change between
two instances of the same board.
UsbRxMode used to be unitialized and was first set to default to 1
in http://review.coreboot.org/6474 (change I32237ff9,
southbridge/amd/cimx/sb800: Uninitialized variables in config func):
> > Why initialize those to 1? (just curious)
> See src/vendorcode/amd/cimx/sb800/SBTYPE.h
> git grep 'SbSpiSpeedSupport\|UsbRxMode'
> src/vendorcode/amd/cimx/sb800/SBTYPE.h
I could not find a corresponding errata in the SB800 errata list,
however errata 15 (USB Resets Asynchronously With Port CF9h Hard Reset)
might play into this being unsafe to do since the code uses CF9h to
reset.
So its possible that while previously undefined it still ended up
defaulting to 0 and the codepath exercised on my board is simply
buggy or there is a difference between a true "SB800" and the
"A50 Hudson M1" presumably used on my board.
Change-Id: I33f45925e222b86c0a97ece48f1ba97f6f878499
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10549
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace the AMD SMBus section with the equivalent SB800 smbus.asl
include or remove already commented-out sections.
Verified by running the cpp preprocessor over the DSDTs and diffing the
results against this patch.
The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where
someone added RADD and SADD to the OpRegion, but those are unused, so
removing them is fine.
Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10618
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Auron only has three GPIOs for RAMID, so there is no need for
sixteen SPD file entries. Only include 8 SPD entries.
Change-Id: Icf83719a2a5b9271b29f48cde5c66c4c8ccd07f4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12073
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On Broadwell, this reduces the number of 'remarks' in the IASL build
from 222 to 3.
Fixes these remarks:
Object is not referenced (Name is within method [_CRS])
The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method. Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.
This change was made for fsp_baytrail in commit 2eaa0d49
fsp_baytrail: Fix ACPI 'Object is not referenced' warnings
Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11268
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11883
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The ASL code is already present in
`southbridge/intel/common/acpi/platform.asl` and
`cpu/intel/common/acpi/cpu.asl`.
So include these files instead of duplicating the code.
Something similar was don in commit commit 24813c14 (i945: Consolidate
acpi/platform.asl).
Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11882
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the
southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact
same ASL code though. So share this in the directory
`src/southbridge/intel/common/acpi`.
Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11881
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file
in the directory `src/cpu/intel/model_6dx/acpi`, although the devices
can also use different Intel CPU models like, for example,
`intel/model_6ex` on the Lenovo T60.
Therefore move the file to the directory `src/cpu/intel/common/acpi` so
that other devices, like Intel GM45 based devices, can also include it.
Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11880
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP
configuration option.
TEST=Built and booted on Minnowboard Max
Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11
Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl>
Reviewed-on: http://review.coreboot.org/10126
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
connections checked by desoldering the FCH and looking at the PCB
this lowers the power consumption by about 150-200mW measured on primary side
based on change #5397
Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/11866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
don't use non-volatile pointers for MMIO access
Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12081
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.
Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.
Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
To help hypervisors to assign PCI devices individually to virtualization
guests, page align dynamically allocated MMIO resources.
Tested with kontron/ktqm77 which has dynamically configured onboard
devices on the root bus and secondary buses. Booted Linux and checked
the configuration with `lspci -v`. Got the configuration through Muen's
tools which are very picky about overlapping and alignment. Booted a
Muen based system that uses many onboard devices. GMA, xHCI and one NIC
(on a secondary bus) were verified to function properly.
Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/12111
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Values based on correlation of brand strings, brand numbers and the TDP
listings on AMD's web site (Wikipedia for Athlon 64 FX-7x TDPs).
Change-Id: I7e6d12d0b6cc4fefc3f84076234c62c40e08304c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/10926
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It works there, we want it, disable that restriction.
Change-Id: Idc023775f0750c980c989bff10486550e4ad1374
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/12094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit e660651824.
After some discussion on IRC we decided to revert it as libpayload can
only read the copy that was removed (and other users like nvramtool can
only read the other copy). So we need both copies at this time.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6cf6b2a1523d771bb52f3d5720b1b16ed4b348db
Reviewed-on: http://review.coreboot.org/11696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We need to special-case filling out the vboot structures when
we use CBFS instead of vboot's custom indexed format, otherwise
(due to the way the CBFS header looks), it will try to write several
million entries.
Change-Id: Ie1289d4a19060bac48089ff70e5cfc04a2de373f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.
Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These are needed for the hardware-sequencing function of the PCH SPI
interface. Values are specific to the flash chip used on a board.
Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11798
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.
In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().
BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron
Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
Do not hardcode the CPU downstream non-posted request limit; the
value of this register is CPU family specific and is set appropriately
in the corresponding CPU driver code.
Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11935
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Commit dbeedbef (arch/x86/bootblock: Link in object files selected with
bootblock-y) breaks building of x86 boards with
`CONFIG_EARLY_CBMEM_INIT` *not* selected but CBMEM time stamp collection
enabled.
Aaron Durbin explained as below [1] and provided this patch to fix it.
> That change actually processes bootblock-objs where before it never did
> such a thing. I'm sure this isn’t the only issue lurking. bootblock on
> x86 implied romcc and thus all the bootblock-y += rules that other
> architectures use worked, but now all the implied assumptions are no
> longer true on x86.
>
> timestamp stuff on x86 !CONFIG_EARLY_CBMEM_INIT is the issue you're
> seeing. In order to compile timestamp.c for bootblock under these
> conditions will mean there needs to be some more Makefile guarding.
[1] http://review.coreboot.org/11864
Change-Id: I3441b9fcdbbc8bbe82b9f2075e60668a846ecf09
Fix-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The broadwell soc code was upstreamed based off an old coreboot branch
and apparently never tested with USBDEBUG.
This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine
board, as verified with a FT232H setup. The fix is simply removing
outdated code that since branching off had been deduplicated in upstream
coreboot, anyway.
Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: http://review.coreboot.org/11874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Serial number is derived from the MAC address of first NIC.
Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Do this to wipe error message and hexdump of SPD from console log.
Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.
Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3a42ba9494b5174920e36e3110b8d62d721fe742
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing microcode update system used custom, manually generated microcode
blob files. This made updates very difficult. Update parser to use stock
microcode update files as provided by AMD.
Change-Id: I772b264ad167f2a5d629dab5d64d9b0ccab3a053
Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11829
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Updating to a new IASL introduces a lot of warnings that are
not serious issues but can be fixed with some reworks.
- Method local variables that are set but never used now warn,
when needing to read back a register the ordering is now changed
to set the value in Local0 first so the compiler does not complain.
- Methods that create an object must be serialized
- A ResourceTemplate declared inside a _CRS with a named variable
does not seem to be able to compile without a warning. To fix
this move the ResourceTemplate outside the _CRS method.
- The DPTF CPU code was still using the old legacy \_PR.CPUx
instead of the new \_PR.CPxx definitions.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build glados with iasl-20150717 and see no warnings
Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11812
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
In order to support verstage the cache-as-ram split
is taken advantage of such that verstage has the
cache-as-ram setup and rosmtage has the cache-as-ram
tear down path. The verstage proper just initializes
the console and attempts to run romstage which triggers
the vboot verification of the firmware. In order to
pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning
to the assembly code which tears down cache-as-ram.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with verstage support as well as
VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.
Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To support x86 verstage one needs a working buffer for
vboot. That buffer resides in the cache-as-ram region
which persists across verstage and romstage. The current
assumption is that verstage brings cache-as-ram up
and romstage tears cache-as-ram down. The timestamp,
cbmem console, and the vboot work buffer are persistent
through in both romstage and verstage. The vboot
work buffer as well as the cbmem console are permanently
destroyed once cache-as-ram is torn down. The timestamp
region is migrated. When verstage is enabled the assumption
is that _start is the romstage entry point. It's currently
expected that the chipset provides the entry point to
romstage when verstage is employed. Also, the car_var_*()
APIs use direct access when in verstage since its expected
verstage does not tear down cache-as-ram. Lastly, supporting
files were added to verstage-y such that an x86 verstage
will build and link.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using separate verstage.
Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When a separate verstage is employed the verstage file
was just being added through the cbfs-files mechanism.
However, that doesn't allow one to specify other flags
that aren't supported that an architecture may require.
The x86 architecture is one of those entities in that
it needs its verstage to be XIP. To that end provide
a mechanism for adding verstage with options.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using his mechansim on x86.
Change-Id: Iaba053a55a4d84d8455026e7d6fa548744edaa28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11819
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
internal USB EHCI controller broken, with no assigned IRQ.
PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
for the GPIO to use. They cannot be used for PCI devices at the same time.
Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9993
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
If timestamps need to be enabled for t132-boards, build would break
because TIMESTAMP region does not exist. With this change, t132 boards
can enable "COLLECT_TIMESTAMPS" without any build error.
Change-Id: I283a5ec49b5af95bd524f590e352367b7cbfd83d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/11893
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Changes to CR1 and CR2 were effectively overwriting the backlight
configuration from the devicetree with static values.
Instead read the maximum brightness value from BCLM (backlight
modulation frequency) and calculate the target level (Arg0 is the
target level as percentage).
Turned out that _BQC has to return a value from the list returned by
_BCL. So XBQC got a little heavier to search for the correct value.
Change-Id: I35419993c8250c95fc69ba4db30db9dba9e6f8ff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11704
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
The two cases only differ in the register locations.
As the values in BRIG were all the same, consolidate them. They also
got normalized to percentages as the ACPI spec wants that (0x61 was 100%
before).
Change-Id: I9216a953bb89458ed102c39194ea370cbf463d5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11703
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Consolidate some common (and mostly broken) code. Will try to fix things
in separate commits.
Maybe, igd.asl taken from gm45 (the non-PCH case) could also be used for
i945 and sch. But this needs further investigation.
Change-Id: Id3663bf588458e1e71920b96a3149f96947921e9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11702
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
The right files just need to be added to the verstage
build. Do that so a stand alone verstage builds and
links.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11828
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The current method was only taking the cbfs path. Because
of this fsp.bin was never being utilized from the RW slots.
Using prog_locate() now provides both the cbfs and vboot
locate methods for free.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I2b3e088326d5a965ad90806a7950b9f401ed57de
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Leave the SPI controller enabled upon boot block exit.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Move base address into iomap.h. Use PCI symbols instead of SPI specific
symbols. Fix comments.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to support x86 verstage proper the work buffer
needs to live in cache-as-ram. However, after cache-as-ram
is torn down one still needs the verification results to
know which slot was selected. Though the platforms with
a dedicated SRAM can just use the work buffer in SRAM, the
x86 cache-as-ram platforms need a place to stash the
results. For that situation cbmem is employed. This works
because when cbmem is initialized cache-as-ram is still
enabled. The VBOOT_DYNAMIC_WORK_BUFFER case assumes
verified boot doesn't start until after cbmem is up. That
doesn't change, but it's a goal to get rid of that option
entirely once all other x86 platforms are moved over to
pre-romstage vboot.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with pre-romstage verification
as well as VBOOT_DYNAMIC_WORK_BUFFER case.
Change-Id: I7eacd0edb2b6ca52b59b74075d17c00b50676d4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11821
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On x86 the early stages are currently execute-in-place which
means they live in the memory-mapped spi flash. However, when
loading romstage from verstage the romstage is
execute-in-place so it's unnecessary to write over a read-only
media -- not to mention writing to read-only memory is wrong
to begin with.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Noted reduction of 20ms when
loading romstage.
Change-Id: I7cd399302a3925a05fbce82600b4c50ea66a0fcb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11823
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Bump up the romstage size to allow more breathing room.
Change-Id: I4df7031d286c13797dccdf2f49d023bbf462fbb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11830
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The conditions in cbmem console for supporting verstage
were implicitly utilizing CONFIG_BOOTBLOCK_CONSOLE to handle
the cbmem console enablement. Fix it so verstage is a first
class citizen for deciding actions pertaining to cbmem console.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using verstage. cbmem console
shows verstage output.
Change-Id: Iba79efd1c1d4056f1a105a5e10ffc95f3e69b597
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11820
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For the purpose of isolating the work buffer logic
the surface area of the API was slimmed down. The
vb2_working_data structure is no longer exposed,
and the function signatures are updated accordingly.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: If64184a79e9571ee8ef9822cfce1eda20fceee00
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11818
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For vboot1 there was an rmodule that was loaded and ran to
do the firmware verification. That's no longer used so remove
the last vestiges of VBOOT_STUB.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I6b41544874bef4d84d0f548640114285cad3474e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11817
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The report_platform_info() and set_max_freq() are not being
used similarly on skylake and braswell. With the addition
of other SoCs I suspect a similar pattern will emerge. Instead
of having weak functions to ensure things link with the hardcoded
policy push these calls into their respective SoC homes.
For parity, both skylake and braswell were updated to be consistent
with the same calls prior to this patch.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Built braswell.
Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303334
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11815
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Latest FSPv83 made some change related to UPD/VPD
need this patch to align those
BUG=None
TEST=Build and Boot Cyan System
BRANCH=strago-7287.B
CQ-DEPEND=CL:*226897
Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291394
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303137
Original-Commit-Ready: John Zhao <john.zhao@intel.com>
Original-Tested-by: John Zhao <john.zhao@intel.com>
Change-Id: I9920eea84b802699454850bfde489668201ffeb6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11813
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On Skylake, mailbox interface is used to configure VRs, dropping direct msr
writing. With current fsp, svid/vr programming seems to be functional - no
errors are given in the svid transactions in boot, and hw engineer verified
the VRs on Kunimitsu. Additional tunnings might be needed later with power
testing.
24mhz calibration is no longer needed on Skylake due to bclk archtecture
change.
BRANCH=none
BUG=chrome-os-partner:45387
TEST=Built and boot on kunimitsu/glados, reboot, S3/resume verified.
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Change-Id: If99b5758fcdba8604139c761a07403d4a5d2eb4c
Original-Reviewed-on: https://chromium-review.googlesource.com/301470
Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I98acf78aac9c705614fb200f8c3313a89296fbf2
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11811
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Instead of just passing bits, tsc_low, tsc_high, and an
opaque pointer to chipset context those fields are bundled
into a cache_as_ram_params struct. Additionally, a new
struct fsp_car_context is created to hold the FSP
information. These could be combined as the existing
romstage code assumes what the chipset_context values are, but
I'm leaving the concept of "common" alone for the time being.
While working in that area the ABI between assembly and C code
has changed to just pass a single pointer to cache_as_ram_params
struct. Lastly, validate the bootloader cache-as-ram region
with the Kconfig options.
BUG=chrome-os-partner:44676
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/300190
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It builds only on veyron_* which already select it, no need to ask user.
Change-Id: Ie508b9eade16e0f39073b23dc0da6b6d1e0a4c73
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10380
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
board_id() returns an integer which is platform-specific. 0 for one port
is different from 0 for another port. So there is no default board_id()
and hence enabling it on boards other than urara would cause build failure.
Not enabling it on urara or just setting id to "(none)" as is default results
in board_id() = 0 which means urara and an error message on console.
Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10379
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Fixes linking error. Specifies that we're in text mode.
Change-Id: I7ad258961039c19e1491e2b3832b003671d8a5c7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11848
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
MBa doesn't have a usable usbdebug port.
Change-Id: Ia8459daa5c9b9405c289954b28ecf1423b1f076c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested on T60 with intel graphics.
Change-Id: Id74d0a1315749052e7313135242e6b64862aa5e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5345
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the info by Felix Held.
Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
MBA has eDP and not LVDS, so it's not supported by our native init.
Change-Id: I489b7a98163b648f0e8000202117593c6b1aaf31
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11842
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
MBA has a soldered RAM without SPD, so you need to use stored SPD.
Change-Id: I0205e6c65ccbfe7764c12c815e60801a3c3623a5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11841
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Just ran autoport on the data from MacBookAir4,2
Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11840
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make sure edge write test results are sane.
Check rn.all to make sure rn.start and rn.end are valid.
Most likely the following test is going to fail on the same
rank anyway.
Change-Id: Ifa601406e6c74ceb8d70063be5ce1bf6bc512c18
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11247
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Don't disable PEG bits while turning on IGD.
Fixes PCI device enumeration of PEG devices.
Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H
Sidenote: This should be taken from a CMOS option instead.
Change-Id: I2d6522504e4404f2d57f9c319351d08317aefdcb
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11058
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Activate PEG clock-gating only if all PEG devices are disabled.
Fixes system hang when trying to access PEG registers.
Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H
Change-Id: I7d62fbb83c16741965639cea1a0e4978d4e3d6da
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11059
Tested-by: build bot (Jenkins)
Since we now have more freedom in the bootblock linking step it no
longer makes sense to use a monolithic bootblock.S. Code segments must
still be included as the order in bootblock.S determines code flow.
However, non-code flow related assembly stubs don't need to be directly
included in bootblock.S
Change-Id: I08e86e92d82bd2138194ed42652f268b0764aa54
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11792
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code flow doesn't fall through to walkcbfs, as it does in the rest
of bootblock.S. Instead, walkcbfs is called (albeit via a jmp). The
linker cannot know this when walkcbfs.S is included directly.
When we use a CAR bootblock, we lose several hundred bytes because
walkcbfs is not garbage-collected, yet it isn't used. This problem
is solved by assembling walkcbfs.S separately, and linking it.
Change-Id: Ib3a976db09b9ff270b7677cb4f9db80b0b025e22
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11785
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As part of preparing for systems with non-memory-mapped media, we want
to be able to call into C code. This change allows us to link C code
directly into the bootblock. The steps of going from bootblock main()
to CAR setup to C code will be implemented in subsequent patches.
Note that a few files selected with bootblock-y will now be compiled
for the bootblock as well, but since we enabled garbage collection,
they will not be included in the final binary.
Change-Id: I5ca6dcaf176f5469c6a3bb925859399123493bc6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11783
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The only difference between the ifeq/else/endif guarded rules is the
linker flags specific to x86. Add those flags to LDFLAGS_bootblock,
and only use one rule for bootblock.debug.
Change-Id: I986a93e0418f05fb273512d7efe0573052493332
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11782
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The macro is defined in `util/cbmem/cbmem.c` too, so do the same here,
so that searching for that macro name shows all the usages.
Change-Id: I52e9fa414fbbe2012bc6d00312db528efba3e564
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11803
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Commit 47818b4d60
(fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IO)
breaks the logic which decides whether FSP
could be found or not in cache_as_ram.inc.
Fix the error by inverting the logic of the test.
TEST=Bootet mc_tcu3 board
Change-Id: I993d3422ac406d204a53e4dc890210fb9a52469d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Now that cbfs is adding more metadata in the cbfs file
header one needs to access that metadata. Therefore,
add struct cbfsf which tracks the metadata and data
of the file separately. Note that stage and payload
metadata specific to itself is still contained within
the 'data' portion of a cbfs file. Update the cbfs
API to use struct cbfsf. Additionally, remove struct
cbfsd as there's nothing else associated with a cbfs
region aside from offset and size which tracked
by a region_device (thanks, CBFS_ALIGNMENT!).
BUG=None
BRANCH=None
TEST=Built and booted through end of ramstage on qemu armv7.
Built and booted glados using Chrome OS.
Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The x86 bootblock linking is a mess. The bootblock is treated in
a very special manner, and never received the update to link-time
garbage collection.
On newer x86 platforms, the boot media is no longer memory-mapped.
That means we need to do a lot more setup in the bootblock. ROMCC is
unsuitable for this task, and walkcbfs only works on memory-mapped
CBFS. We need to revise the x86 bootflow for this new case.
The approach this patch series takes is to perform CAR setup in the
bootblock, and load the following stage (either romstage or verstage)
from the boot media. This approach is not new, but has been done on
our ARM ports for years.
Since we will be adding .c files to the bootblock, it is prudent to
use link-time garbage collection. This is also consistent to how we
do things on other architectures. Unification FTW!
Change-Id: I16b78456df56e0053984a9aca9367e2542adfdc9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11781
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Up to now, the multi-CBFS code path merely looked up files in the "boot
ro" image (ie. the default), disregarding the specified fmap region to
use for CBFS.
The code still relies on the master header being around, which on the
upside allows it to skip an offset at the beginning of the region (eg.
for ARM bootblocks).
This will change later (both the reliance on the master header and the
presence of the bootblock like this).
Change-Id: Ib2fc03eac8add59fc90b4e601f6dfa488257b326
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11805
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.
Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is no other guard to prevent this from being picked up when
building for other architectures.
Change-Id: I2039a289a4dd9970d5dd0f90d43d5d5c2a6d0a0b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11795
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EM100Pro allows the debug console to be sent over the SPI bus.
This is not yet working in romstage due to the use of static variables
in the SPI driver code. It is also not working on chipsets that have
SPI write buffers of less than 10 characters due to the 9 byte
command/header length specified by the EM100 protocol.
While this currently works only with the EM100, it seems like it would
be useful on any logic analyzer with SPI debug - just filter on command
bytes of 0x11.
Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Building an image for the Lenovo X201 with native graphics
initialization selected fails due to the changes introduced by commit
a3b898aa (edid: Clean-up the edid struct).
Same as in 11738 / 11585 / 11491
Change-Id: I4233a4ce2f5423c7ebdad68e8059cd34ac61cfaa
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/11787
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Users of DRIVERS_UART_8250MEM_32 would have to also select
DRIVERS_UART_8250MEM to avoid missing Kconfig dependencies. Instead,
do what the OXPCIE driver dies and select the appropriate options.
Change-Id: I40d93df024fcb3a9ad6dc51d6a5966e7b1b6c07f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11786
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
mohonpeak is the reference board for Rangeley. I doubt anyone uses it
or cares about it. We jokingly refer to it as "Moron Peak". It's code
with no known users, so we shouldn't be hauling it around for the
eventuality that someone might use it in the future.
Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11790
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
We already have two other code paths for this silicon. Maintaining the
FSP path as well doesn't make much sense. There was only one board to
use this code, and it's a reference board that I doubt anyone still
owns or uses.
Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11789
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Certain chipsets provide their own main symbol for verstage.
Therefore, it's necessary to know this so that those chipsets
can leverage the common verstage flow.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built nyan using this option.
Change-Id: If80784aa47b27f0ad286babcf0f42ce198b929e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11777
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Though the tegra124 SoC makes their faster cpus come up
in verstage it can still use the common flow. Therefore,
use the common verstage API for performing thenecessary
steps to initialize the caches on the faster cores.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built nyan.
Change-Id: I93023ec92a9de111db688742b057b5c64143f0b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11776
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The file was not referenced or used. Kill it.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=None
Change-Id: I30285d523ef3ca4dd3ce38b53aeb42862d929c90
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are compiler settings and interactions with other
header files that should be handled. First use __typeof__
instead of typeof because 'std' modes don't accept typeof.
The __typeof__ variant works equally well on clang. The
other change is to guard the helper macros so as not to
trigger redefinition errors.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built cbfstool including commonlib/helpers.h
Change-Id: I58890477cb17df14a9fa8b7af752a7c70769cf36
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11773
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to support FSP 1.1 relocation within cbfstool
the relocation code needs to be moved into commonlib.
To that end, move it. The FSP 1.1 relocation code binds
to edk2 UEFI 2.4 types unconditionally which is separate
from the FSP's version binding.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: Ib2627d02af99092875ff885f7cb048f70ea73856
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11772
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now that the commonlib/endian.h routines have landed utilize
those in the FSP relocation code.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: If431d64fd2843bea864d971ca1ea06b07c0d6435
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11771
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Remove dummy data from hwinfo.hex as it is not needed
anymore in the system.
Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11763
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Since microcode was moved to 3rdparty/blobs, we need to select
USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly.
Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11764
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
I missed these Makefile.inc changes. As verstage.c was removed
remove the references within the Makefile.incs.
Change-Id: I5d38c0a87d057622a3706bf3bde1142944c3b17c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11759
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since fsp_baytrail was refactored to use microcode.bin
in 3rdparty/blobs, we do not need MICROCODE_INCLUDE_PATH any more.
Change-Id: I4382b0c174877186bd37fbff21f3269136d15e10
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11762
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Building an image for the Lenovo X200 with native graphics
initialization selected fails due to the changes introduced
by commit a3b898aa (edid: Clean-up the edid struct).
Change-Id: Ifd36571c9c00761b4a2a6deb3c9c4a52d9d13e25
Signed-off-by: Audrey Pearson <apearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11738
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
vboot_handoff_flag was duplicating the logic to grab the handoff info, that is
already made available with vboot_get_handoff_info.
This uses vboot_get_handoff_info in vboot_handoff_flag instead.
Change-Id: I28f1decce98f988f90c446a3a0dbe7409d714527
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11498
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inspired by the Sage source code (itself from coreboot).
Change-Id: I4864923166efb200882d895c572d1ee060c71951
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The thermal sensor interface exposed in function 3 of the northbridge is
a more convenient and faster way to access the processor-internal
thermal sensor than using the SMBus/SB-TSI interface from the FCH, see
the Family14 BKDG: "Tctl is a processor temperature control value used
for processor thermal management. Tctl is accessible through SB-TSI and
D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the
processors cooling requirements"
Also on at least some of these boards the existing thermal zone is
broken and always returns 40C (the default value if the SMBus read
failed) because the SMBus muxing register (SmBus0Sel) is not set up
correctly.
Case in point: The fallback "smbus read failed" temperature is 40 C and
the the logs taken from the board status repository for the Asrock
E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)"
e.g.
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425
Example lm-sensors output with this patch on the pcengines APU1, on
Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and
CONFIG_SENSORS_K10TEMP enabled):
acpitz-virtual-0
Adapter: Virtual device
temp1: +54.0 C (crit = +100.0 C)
k10temp-pci-00c3
Adapter: PCI adapter
temp1: +54.0 C (high = +70.0 C)
(crit = +100.0 C, hyst = +97.0 C)
Change-Id: Id9c5b783ba424246816677099ec6651814e59f21
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add some missing devices to device tree and header.
Remove the obsolete devices.
Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The vboot verification in a stage proper is unified
replacing duplicate code in the tegra SoC code. The
original verstage.c file is renamed to reflect its
real purpose. The support for a single verstage flow
is added to the vboot2 directory proper.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11744
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Using a copiler to compile something that's already a binary is pretty
stupid. Now that Stefan converted most microcode in blobs to a plain
binary, use the binary version.
Change-Id: Iecf1f0cdf7bbeb7a61f46a0cd984ba341af787ce
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11607
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to do a verification of romstage on x86 one needs to
run verstage which verifies romstage (and the memory init code).
However, x86 doesn't have SRAM like every other modern SoC so
managing the cache-as-ram region is especially critical.
First move all of the "shared" objects to the beginning of
the .car.data section. This change then ensures that each stage
using car.ld to link has the same consistent view of the addresses
of these fixed-sized objects in cache-as-ram. The CAR_GLOBALs can
be unique per stage. However, these variables are expected to have
a value of zero at the start of each stage. In order to allow a
stage to provide those semantics outside of the initial cache-as-arm
setup routine add _car_global_start and _car_global_end symbols.
Those symbols can be used to clear the CAR_GLOBALs for that stage.
Note that the timestamp region can't be moved out similarly to the
pre-ram cbmem console because the object storage of the timestamp
cache is used *after* cache-as-ram is torn down to indicate if the
cache should be used or not. Therefore, that timestamp needs to
migrated to ram. A logic change in src/lib/timestamp.c could
alleviate this requirement, but that task wasn't tackled in this
patch.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I15e9f6b0c632ee5a2369da0709535d6cb0d94f61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11740
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to support verstage on x86 one needs to link verstage
like romstage since it needs all the cache-as-ram goodies. Therefore,
provide a macro that one can invoke that provides the necessary
recipes for linking that particular stage in such an environment.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I12f4872df09fff6715829de68fc374e230350c2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11739
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This moves a few vboot-prefixed functions that were defined in chromeos.c to
vboot_common.c, since those are only relevant to vboot and depend on the vboot
handoff data. This allows more separation between CONFIG_CHROMEOS and what
CONFIG_CHROMEOS selects, so that each separate option (such as
CONFIG_VBOOT_VERIFY_FIRMWARE) can be enabled separately.
Thus, the actual definitions of these functions will only be declared when
CONFIG_VBOOT_VERIFY_FIRMWARE is set, so the check before calling
vboot_skip_display_init in bootmode was also adapted.
Change-Id: I52f8a408645566dac0a2100e819c8ed5d3d88ea5
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11497
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Avoid specifying the size of the microcode in microcode_size.h.
Instead, the size will be determined during build time and
microcode_size.h will be generated. This way, the size does
not need to be adjusted by hand.
Change-Id: I868f02b0cc03af12464a6a87c59761c200eb2502
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11709
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use the common ME and descriptor code.
BUG=chrome-os-partner:43462
BRANCH=None
TEST=Built glados
Change-Id: I7196f587b92fd26129b30e2cd73f4caf5f4ebef8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11735
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of selecting the Kconfig option and adding the subdir
entry within each chipset auto include the common/firmware
directory as it's guarded by HAVE_INTEL_FIRMWARE.
BUG=chrome-os-partner:43462
BRANCH=None
TEST=Built glados.
Change-Id: I166db67c41b16c4d9f0116abce00940514539fa5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11734
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The output of command below,
# i386-elf-nm build/cbfs/fallback/romstage_null.offenders | \
grep -q "" ; echo $?
has different result on MacOS, OS X Mavericks, which outputs 0.
On linux, it outputs 1.
I assume it is misleading to search an empty string in a empty
string. Change it to testing if the string is empty.
Change-Id: Ie4b8fe1fb26df092e2985937251a49feadc61eb0
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11600
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This fixes building with CONFIG_COVERAGE=y
Change-Id: I5128ae0ef0d4f71e3ede7bcb3ee7ed7e265d1bb7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11729
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Set XN bit of block upper attribute to device memory in mmu. CPU may
speculatively prefetch instructions from device memory, but the IO
subsystem of some implementation may not support this operation. Set
this attribute to device memory mmu entries can prevent CPU from
prefetching device memory.
BRANCH=none
BUG=none
TEST=build and booted to kernel on oak-rev3 with dcm enabled.
Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c
Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302301
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There appears to be an issue that is causing this particular bit of
ACPI code to be incorrectly interpreted by the kernel and the IASL
disassembler.
Ensuring the PCRB() method is defined in the DSDT before any uses of
it appears to fix the problem, but that relies on specific ordering
of the ASL files included by pch.asl and may break again in the future
if the includes were re-ordered. (they are alphabetic now)
So in this case to work around the issue unroll the function call so
the admittedly messy calculation is reduced to a constant when compiled.
Note this issue was observed with both iasl-20130117 and
iasl-20150717.
ACPICA bug: https://bugs.acpica.org/show_bug.cgi?id=1201
BUG=chrome-os-partner:45760
BRANCH=none
TEST=verify disassembled AML is correct
Change-Id: I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ecacc340d6e1068ea649f0859657bb3208695730
Original-Change-Id: I232523f5b6ce290da6e7d99405a53b9437b10e0d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302167
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BUG=chrome-os-partner:41280
BRANCH=none
TEST=Audio jack insert/eject detection and headset buttons work
on glados with the nau8825 driver in chromeos-3.18 and the
staging kernel skl2.
Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb
Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293610
Original-Reviewed-by: Anatol Pomazau <anatol@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11720
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the CTDP support code that is in ACPI. It has been ported
from haswell and while the MCHBAR register interface does seem to
still exist the calculations for determining PL2 is no longer
straightforward.
Additionally nothing is using this interface and the expectation
is that DPTF will be used for throttling with PL[1234] and having
ACPI interfere with the configuration would not be good.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I81e356ddf564a5253458b82bc3327bfb573ab16d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 884ee9a764bad0b3b4bcaeb5a3f46c5f090a116c
Original-Change-Id: I284ab52a305cee25c88df5228b01ff1e9544efe3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302166
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11719
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Recent version of iasl are flagging more things as warnings.
Remove unused Local0 uses and make _CRS method serialized to
fix these warnings.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build glados with iasl-20150717
Change-Id: I1d4535205426dd9a6346f53ff159221cf5cd899a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8b43f8f24bb7cb33ad0411c24616da66663c2e3e
Original-Change-Id: I71eafd91d30d5f50e6211368f0bbc517c8085892
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302163
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the TPM _CRS method creates named objects it needs
to be serialized to prevent a warning in recent iasl.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build glados with iasl-20150717
Change-Id: I59a52552ab24b7d9c9928331aa8c8d19f54fd1b7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a5c474c94980661573a99eb94d5f661f2d0114b
Original-Change-Id: Ie9d164ea8781304dd0bf1833d182d7c601b8e18d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302162
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to wake from S0ix the kernel needs to know that the
keyboard interrupt is wake capable. Using IRQNoFlags does not
allow the wake capability to be reported.
For normal S3 this does not matter as the EC is the one handling
the keyboard wake event. For S0ix the EC does not need to be
involved in this particular wake event.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=echo freeze > /sys/power/state and wake from keyboard
Change-Id: I7175d2ea98f8a671765897de295df7b933151fc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 645f1cd96c35f42aa7c40ff473b15feb619b0373
Original-Change-Id: Ia89c30c51be9db7b814b81261463d938885325fd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/301441
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11712
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This removes the dependency on chromeos and vboot for the sw write protect state
function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
both reflect this change and become consistent with the definition of
get_write_protect_state that is already in use.
Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When building for ChromeOS, it is expected that Coreboot will only occupy the
first MiB of the SPI flash, according to the veyron fmap description.
Otherwise, it makes sense to use the full ROM size.
Change-Id: I168386a5011222866654a496d8d054faff7a9406
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11117
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Unlike the other stages, the payload requires virtual memory to be set up
and also a privelege level change.
Change-Id: Ibbe2a55f7719d917f121a53a17c6d90e6b2ab3d1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/11699
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Currently coreboot expects the loader to clear the bss section
for all stages. i.e. stages don't clear their own bss. On ARM
SoCs the BootROM would be responsible for this. To do that
one needs to include the bss section data (all zeros) in the
bootblock.bin file. This was previously being attempted by
keeping the .bss info in the .data section because objcopy
happened zero out non-file allocated data section data.
Instead go back to linking bootblock with the bss section
but mark the bss section as loadable allocatable data. That
way it will be included in the binary properly when objcopy
-O binary is emplyed. Also do the same for the data section
in the case of no non-zero object values are in the data
section.
Without this change the trick of including .bss in .data
was not working when there wasn't a non-zero value object
in the data section.
BUG=None
BRANCH=None
TEST=Built emulation/qemu-armv7 and noted bootblock.bin contains
the cleared bss.
Change-Id: I94bd404c2c4a8b9332393e6224e98940a9cad4a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11680
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit adds read/write functions for both big and
little endian interpretations. Additionally there are
variants that allow an offset to be provided into the
source buffer.
BUG=None
TEST=Wrote test harness for functions. Also booted ARM QEMU
through end of payload.
Change-Id: If44c4d489f0dab86a73b73580c039e364c7e517d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11677
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use the common ACPI _SWS code and provide a function to fill out
the wake source data.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-samus coreboot
Change-Id: I3d2ceca8585314122b78317acb7f848efb6e9a14
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d8afaee8e27222639c5e249d53be28cddcb78f72
Original-Change-Id: Ie551ecf3397c304216046cc2046c071f7b766e5f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298168
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Switch braswell to use the common code for filling out the NVS
data used by ACPI _SWS methods. This code was out of date on
braswell so also update it to provide the \_GPE.SWS method.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-cyan coreboot
Change-Id: I41c2a141c15f78dc0d9482954c157f81bd0759fa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4c4d1ee76f337addf687ca5a9ae2da5e898c2de0
Original-Change-Id: I44424784d5d3afb06d0d58c651a9339c7b77418c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298230
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Enable and use the common code for filling out the NVS data used
by the _SWS methods. Add a function to provide the wake source
data. With Deep S3 enabled skylake does not retain the contents
of the PM1_EN register so instead just select the wake related
events in PM1_STS.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=tested on glados by checking for valid _SWS string in
/sys/firmware/log after suspend/resume. Wake sources that were
tested are RTC, power button, keypress, trackpad, and wifi.
Change-Id: I93a4f740f2e2ef1c34e948db1d8e273332296921
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cb4d4705b87ef7169f1979009c34a58de93c4ef0
Original-Change-Id: Ib6b4df09ea3090894f09290d00dcdc5aebc3eabb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298169
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is a follow-up patch to
https://chromium-review.googlesource.com/#/c/286877, after fsp support
is landed in v1.5.
BUG=chrome-os-partner:42975
BRANCH=none
TEST=execute "mosys memory spd print all" on glados and kunimitsu
Change-Id: I949e287372b190affac36a0efde8a30402eecdc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa
Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298967
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Assign GPE DW0 to GPP_B block
- Enable GPP_B16 as ACPI_SCI for wake
- Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
Note that current designs cannot wake from Deep S3 via wifi.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529
Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Assign GPE DW0 to GPP_B block
- Enable GPP_B16 as ACPI_SCI for wake
- Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
Note that current designs cannot wake from Deep S3 via wifi.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=tested on glados:
1-disable deep s3 in devicetree.cb
2-enable magic packet with "iw phy phy0 wowlan enable magic-packet"
3-powerd_dbus_suspend to go to S3
4-wake system with magic packet
Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2
Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298231
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11650
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The values are taken from latest BWG as well fsp src.
BRANCH=none
BUG=chrome-os-partner:45208
TEST=Built and boot on kunimitsu
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164
Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b
Original-Reviewed-on: https://chromium-review.googlesource.com/299480
Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11659
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order for easier consumption in userland tools split the
FSP 1.1 relocation logic into a single file w/ an aptly named
function name.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I49998b8621611c638375bc90884e80d0cd3bdf78
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc898e1c528df60683575d553d6194a1e8200afa
Original-Change-Id: I736c0059d43f6d0be4fdb6e6f47cdb5c189a7ae8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298833
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11665
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
UEFI defines everything as little endian. Additionally the
EDK II header files assume they are used on machines
which are running UEFI -- thus little endian. This patch
attempts to fix up all the possible endian violations
when running on a big endian machine. This is for
in preparation of using the FSP 1.1 code in userland
for relocating FSP images.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I39f4de84688e48978a4650303b8af8345f44fd03
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c7eab9b7c10765355feffa3c3cac403275f9479
Original-Change-Id: I33a7661281307cf31ae33899d1a4eb6a2fbd01a1
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298832
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to integrate fsp 1.1 relocation with cbfstool one
needs to be able to supply the address to relocate the FSP
image. Therefore, allow this by returning offset for return
values. Note that exposed API has not changed.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Confirmed relocation values matched.
Change-Id: I650a08ffb9caf7e0438a988cae9bec56dd31753c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53870b0df809418e9a09e7d380ad2399a09fb4fb
Original-Change-Id: Ic2ec63681ed4e652e2624b40e132f95d1e5a0887
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298831
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/11663
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Patch b2a62622b (linking: move romstage and bootblock to use program.ld)
unified the linker scripts between different stages. Unfortunately it
omitted several special cases from the old bootblock.ld script that are
required for non-x86 environments.
This patch expands program.ld to once again merge the .BSS into the
program image for bootblocks (ensuring correct initialization by the
external loader). It also revives the .id section (which adds a
human-readable blurb of information to the top of an image) and fixes a
problem with unintended automated section alignment.
BRANCH=None
BUG=None
TEST=Jerry and Oak boot again.
Change-Id: I54271b8b59a9c773d858d676cde0218cb7f20e74
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6fddbc00963e363039634fa31a9b66254b6cf18f
Original-Change-Id: I4d748056f1ab29a8e730f861879982bdf4c33eab
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/299413
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11660
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In LP0 resume, a couple of SDMMCx pad settings need to be set to 0 to
reduce power leakage.
BUG=None
BRANCH=None
TEST=Tested on Smaug; able to suspend/resume >100 times
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9f35a90a8af2180443db2c4be75d4566d0990de5
Original-Change-Id: Ifc946b0cea437ef0807cea0c11609d8e09387e8e
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298195
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Joseph Lo <josephl@nvidia.com>
Original-(cherry picked from commit be3ac49a6bc4c9088d3799555d69c87c8ce1693c)
Original-Reviewed-on: https://chromium-review.googlesource.com/298154
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Change-Id: If5d5cebc89b8220480b3c72293a410e782eb437e
Reviewed-on: http://review.coreboot.org/11656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
FSP should not lock CMOS unconditionally. coreboot sends Silicon
UPD parameter "RtcLock" to FSP to take action on CMOS
region locking/un-locking. This patch has CB generic code for
creating the Silicon UPD paramater.
BUG=chrome-os-partner:44484
BRANCH=none
TEST=Build and booted in kunimitsu, tested using below command-
When DIsabled RtcLock from devicetree in coreboot, booted to kernel
and run following commands -
>> crossystem fw_result=success
>> crossystem | grep fw_result
It should reflect the value that is set. Here, success.
If ENabled RtcLock from Coreboot devicetree, The same commands will
fail to update the fw_result status from crossystem utility.
CQ-DEPEND=CL:*229144
Change-Id: I7f63332097cdaf6eedefbc84bec69ce4e9cc59d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7b8293a2c55117d7ca2001ac9ec0de24d35b80b
Original-Change-Id: If708e2c782644dcf7f03785d1bfa235ef5385d80
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297980
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Currently, erase operation only works if the region is sector-aligned.
These asserts ensure we can erase the region when it's all used up.
Erase operation can be updated to handle unaligned erases by read,
update, write-back cycle. However, these asserts will still remain useful
in case the adjacent region contains critical data and mis-updating it
can cause a critical failure.
Additionaly we should write a FAFT test but it's more reliable to catch
it here since FAFT can fail in many ways.
BUG=none
BRANCH=master
TEST=tested on samus using misaligned nvram region
Change-Id: I3add4671ed354d9763e21bf96616c8aeca0cb777
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc001a4d3446cf96b76367dde492c3453aa948c6
Original-Change-Id: Ib4df8f620bf7531b345364fa4c3e274aba09f677
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297801
Reviewed-on: http://review.coreboot.org/11654
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The EC doesn't support these commands so sending them is
not working. We have had a default policy of wake on USB
for a long time now and this runtime config isn't really
needed any longer.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be
Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298234
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The EC doesn't support these commands so sending them is
not working. We have had a default policy of wake on USB
for a long time now and this runtime config isn't really
needed any longer.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655
Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298233
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Jonathan A. Kollasch