Allow a driver to return device specific _HID, which will be consumed by
acpigen in order to generate proper SSDTs.
Change-Id: Ibb79eb00c008a3c3cdc12ad2a48b88a055a9216f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35006
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With RELOCATABLE_RAMSTAGE, S3 resume path only uses
memory that is reserved from OS. So there is no need
for low memory backup and recovery.
Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
ACPI S3 resume path can only modify low memory where
the non-relocatable ramstage resides, there is no need
to maintain a bigger backup copy.
Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
As most platforms will share the subset of enabling
both low RAM WB and high ROM WP MTRRs, provide them
with a single function.
Add possibility for the platform to skip these if
required.
Change-Id: Id1f8b7682035e654231f6133a42909a36e3e15a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34809
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Constify the struct device arguments in below APIs:
> acpi_device_name
> acpi_device_path_fill
> acpi_device_path
> acpi_write_dbg2_pci_uart
> acpi_device_scope
> acpi_device_path_join
The APIs do not seem to modify the argument and are using
device argument as reference to device only.
Change-Id: Ic2ce045f17efa288eb41503795723d0ad5ec78bd
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34625
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are only minimal differences between the architecture specific
stdint.h implementations, so let's tidy them up and merge them together
into a single file. In particular,
- Use 'unsigned long' for uintptr_t. This was already the case for x86
and riscv, while arm and mips used 'unsigned int', and arm64 and ppc64
used 'unsigned long long'. This change allows using a single integer
type for uintptr_t across all architectures, and brings it into
consistency with the rest of the code base, which generally uses
'unsigned long' for memory addresses anyway. This change required
fixing several assumptions about integer types in the arm code.
- Use _Bool as the boolean type. This is a specialized boolean type that
was introduced in C99, and is preferrable over hacking booleans
using integers. romcc sadly does not support _Bool, so for that we
stick with the old uint8_t.
- Drop the least and fast integer types. They aren't used
anywhere in the code base and are an unnecessary maintenance burden.
Using the standard fixed width types is essentially always better anyway.
- Drop the UINT64_C() macro. It also isn't used anywhere and doesn't
provide anything that a (uint64_t) cast doesn't.
- Implement the rest of the MIN and MAX numerical limits.
- Use static assertions to check that the integer widths are correct.
Change-Id: I6b52f37793151041b7bdee9ec3708bfad69617b2
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
AMD Picasso, and later, will not use CPU_AMD_AGESA or CPU_AMD_PI.
Those two symbols indicate an Arch2008 system. Add SOC_AMD_COMMON
to cause cpu_is_amd() to return TRUE on Picasso.
This removes an error message of "Unknown CPU".
The patch also assumes AMD Family 10h and non-AGESA Family 15h
devices were seeing the "Unknown CPU" message. No functionality
has been verified on these devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I3357606c37082f3587ff91924bf7a0e0f8af9625
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34146
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Add architecture independend way of clearing all DRAM
* Implemented in ramstage as MTRRs need to be set to speed up
clearing. Takes up to 15 seconds per GiB otherwise.
* Use memset_pae on x86
* Add quirks for FSP1.0
Tested on P8H61M-Pro:
* Clears 4GiB in less than 1 second
Tested on wedge100s:
* Clears 8GiB in 2 seconds
Change-Id: Idaadb8fb438e5b95557c0f65a14534e8762fde20
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31550
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ALIGN((a), b) and ALIGN_UP(a, b) needs 'helpers.h'
Change-Id: I029c7c5cbb19c7e69997b3d84f929cb61e8e2b23
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ALIGN_UP macro is basically an alias of the ALIGN macro; with this change
it's more obvious in which direction the alignment happens.
Change-Id: I6f1b9f9bbcafeb85a6ef5c10ce4b57edc0740e72
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This patch contains the rest of the fixes for this subtree; having one change
for every area would create an unnecessary amouint of patches.
Change-Id: Id92c11d58693292d58cba323c8468db858becfb5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33630
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Chengdu Haiguang IC Design Co., Ltd (Hygon) is a Joint Venture
between AMD and Haiguang Information Technology Co.,Ltd., aims
at providing high performance x86 processor for China server
market. Its first generation processor codename is Dhyana, which
originates from AMD technology and shares most of the architecture
with AMD's family 17h, but with different CPU Vendor ID ("HygonGenuine")
/Family series number (Family 18h).
More details can be found on:
http://lkml.kernel.org/r/5ce86123a7b9dad925ac583d88d2f921040e859b.1538583282.git.puwen@hygon.cn
Change-Id: I8af8b0f0675f978ac07522029696e43651a3153f
Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32876
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for generating IndexField, which is similar to Field.
Change-Id: If66a627e64953696b0b68488256bd5c141e4c205
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33032
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Previously cpu_index() always succeeded, but since commit 095c931
(src/arch/x86: Use core apic id to get cpu_index()) it is now possible
for it to indicate an error by returning -1. This commit adds error
handling for all calls to cpu_index(), and restores several checks that
were removed in commit 7c712bb (Fix code that would trip -Wtype-limits)
but are now needed.
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5436eed4cb5675f916924eb9670db04592a8b927
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This cpu_index() implementation assumes that cpu_index() function
might always getting called from coreboot context (ESP stack
pointer will always refer to coreboot).
This might not be true in case of proposed PI spec MP_SERVICES_PPI
implementation, where FSP context (stack pointer refers to fsp)
will request to get cpu_index(), natural alignment logic will
use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte).
This is not the place where cpu_index is actually stored by
ramstage c_start.S
Hence this patch tries to remove those dependencies while retrieving
cpu_index(), rather it uses cpuid to fetch lapic id and matches with
cpus_default_apic_id[] variable to return correct cpu_index().
BRANCH=none
BUG=b:79562868
TEST=Ensures functions can be run on APs without any failure and
cpu_index() also provides correct index number.
Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remapping Hardware Status Affinity (RHSA) structure is applicable for
platforms supporting non-uniform memory. An ACPI Name-space Device
Declaration (ANDD) structure uniquely represents an ACPI name-space
enumerated device capable of issuing DMA requests in the platform.
Add RHSA and ANDD structures support for DMAR table generation.
BUG=b:130351429
TEST=Image built and booted to kernel
Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9]
are not the same.
Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Sync acpigen.h content to match with laetst acpica, the link is
https://github.com/acpica/acpica/blob/master/source/include/amlcode.h,
and revision is 20190405. The purspose of the change is just make spec
up to date.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to
calculate nominal TSC frequency.
As per SDM recommendation:
For any processor in which CPUID.15H is enumerated and
MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is
available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774
TEST=Boot ICL platform and calculate TSC frequency using below methods
1. TSC freq calculated based on MSR 0xCE
tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15
tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
The SMBIOS spec requires type 7 to be present.
Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.
As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity
Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.
Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Add two functions to determine if CPU is made by a specific vendor.
Use Kconfig symbols to allow link time optimizations.
Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The effect of pointer aliasing on writes is that any data on CPU
registers that has been resolved from (non-const and non-volatile)
memory objects has to be discarded and resolved. In other words, the
compiler assumes that a pointer that does not have an absolute value
at build-time, and is of type 'void *' or 'char *', may write over
any memory object.
Using a unique datatype for MMIO writes makes the pointer to _not_
qualify for pointer aliasing with any other objects in memory. This
avoid constantly resolving the PCI MMCONF address, which is a derived
value from a 'struct device *'.
Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the current state of the tree we do not utilise the
mechanism of having per-device overrides for PCI bus
ops.
This change effectively inlines all PCI config accessors
for ramstage as well.
Change-Id: I11c37cadfcbef8fb5657dec6d620e6bccab311a4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In case PCI_IO_CFG_EXT=n parameter 'reg' was not
properly truncated to 8 bits and it would overflow
to dev.fn part of the register.
A similar thing could happen with 'dev' but that
value originates from PCI_DEV() macro unlike 'reg'.
Change-Id: Id2888e07fc0f2b182b4633a747c1786e5c560678
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By design only 'reg' parameter can have the two least-
significant bits set. As 'reg' is often a constant,
'0xCFC + (reg & 3)' resolves to an immediate value
already at buildtime, unlike (addr & 3) which depends
of a constant (but non-immediate) value of 'dev' in
ramstage.
Change-Id: I6e729fe800c92b1ce4994ad2b4203072fa75a958
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31754
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One could understand 'where' as bus, device, function
or register. Make it clear it is register.
Change-Id: I95d0330ba40510e48be70ca1d8f58aca66c8f695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide clean separation for PCI and PNP headers,
followup will also move PNP outside <arch/io.h>.
Change-Id: I85db254d50f18ea34a5e95bc517eac4085a5fafa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Having different signatures for the PCI config accessors
prevents them from having the same name in different
stages.
For now, work around this using __SIMPLE_DEVICE__.
Change-Id: I20f56cfe3ac7dc4421e62a99ca91f39a857c0ccf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
As we are running ACPI v3.0, references to older
than v3.0 are removed.
Change-Id: I0cce0035ed2b952d59cc1a4a9e6017dae67ef6db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To make PCI driver side arch-agnostic, function
declarations have to be in symmetrical header
file locations.
From the driver side, the correct file to include
is now <device/pci_ops.h>
Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is expected that method of accessing PCI configuration
register space via memory-mapped region is arch-agnostic.
Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are defined for __SIMPLE_DEVICE__ when PCI
enumeration has not happened yet. These should not
really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge
being located on bus 2 and available for configuration, so
I rather leave the code unchanged. Just move these out of
arch/io.h because they cause build failures if one attempts
to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to
avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We need sizeof(struct ehci_dbg_info) of 88 but only
reserved 64 bytes. If usbdebug_hw_init() was called
late in romstage, for some builds it would corrupt
CAR_GLOBALs like console_inited variable and stop
logging anything.
Also change pointer initialisation such that
glob_dbg_info will hit garbage collection for
PRE_RAM stages.
Change-Id: Ib49fca781e55619179aa8888e2d859560e050876
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
PCI_ADDR() is tightly coupled with different setup_resource_map()
variants so move the declaration away from global namespace.
In the implementation of setup_resource_map() use the bottom
12 bits as the register mask like the other variants do already.
Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EHCI hardware needs to be initialized only once during CAR stages.
Some exception need to be made when a blob messes with the EHCI
hardware. To achieve this add a fixed location in the car.ld linker
script such that the ehci debug information can be shared across CAR
stages.
Currently this means only romstage and bootblock, but verstage can
also be hooked up later on.
Tested on google/peppy: Both the bootblock and the romstage properly
output console.
Change-Id: I78e20a172fd5cc81f366d580f3cce57b9545d7a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.
Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t is deprecated.
Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.
This also removes all references to LATE_CBMEM_INIT
in comments.
Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We alwas define uint64_t as unsigned long long, even on x86_64.
Fix PRIu64 to match the definition of the datatype, to prevent
compilation errors when compiling for x86_64.
Change-Id: I7b10a18eab492f02d39fc2074b47f5fdc7209f3d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/30002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Linux kernel can use the ACPI _PLD group information to
determine peer ports. Currently to define the group information
the devicetree must provide a complete _PLD structure. This
change pulls the group information into a separate structure that
can be defined in devicetree. This makes it easier to set for
USB devices in devicetree that do not need a full custom PLD.
This was tested on a sarien board with the USB devices defined
by verifying that the USB 2/3 ports are correctly identified
with their peer in sysfs.
Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to newest TCG ACPI Specification for Family 1.2 and 2.0
Version 1.2, Revision 8, TPM2 ACPI table has two more fields LAML and LASA.
Update the table structure definition, create the log area for TPM2 in
coreboot tables and fill the missing fields in TPM2 table. TPM2 should be
now probed well in SeaBIOS rel-1.12.0 or master.
Tested on apu2 with Infineon SLB9665 TT2.0.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie482cba0a3093aae996f7431251251f145fe64f3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/29800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Change 76ab2b7 ("arch/x86: allow global .bss objects without
CAR_GLOBAL") allowed use of global .bss objects and hence moved around
the macros resulting in car_active returning 0 even for those boards
where CAR is actually active but do not require global migration. This
resulted in boards getting stuck when doing a reset in verstage because
the code flow incorrectly assumed that there was no CAR active and
hence triggered a cache invalidate.
This change fixes the above issue by returning 1 for car_active if
ENV_CACHE_AS_RAM is set even if global migration is not required.
BUG=b:109717603
TEST=Verified that board reset does not trigger cache invalidate in
verstage and does not result in board hang.
Change-Id: I182f3e4277c57d6c50f7fcac2be72514896b3c61
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Reviewed-by: Nick Chen <nickchen@ami.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Romstage is where DRAM comes online. Therefore, allow
raw CAR_GLOBAL object access in all cache-as-ram stages
that are not romstage. In practice, this should be a nop.
However, the explicit check for romstage is clearer.
Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For platforms utilizing CONFIG_NO_CAR_GLOBAL_MIGRATION there's
no need to automatically migrate globals. Because of this it's
possible to automatically allow for uninitialized global variables
which reside in the .bss section without needing to decorate those
objects with CAR_GLOBAL.
Change-Id: Icae806fecd936ed2ebf0c13d30ffa07c77a95150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Distinguish between TPM 1.2 and 2.0
ACPI table support
* Add TPM2 table support for TIS interface only
Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/29181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change does the following:
1. Adds a helper macro ACPI_IRQ_CFG that can be used by all other
ACPI_IRQ* macros to initialize acpi_irq structure.
2. Provides ACPI_IRQ_WAKE* versions to allow board to define an irq as
wake capable.
BUG=b:117553222
Change-Id: Ic53c6019527bbd270806897247f547178cd1ad3c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's very common across many x86 silicon vendors, so place it in
`arch/x86/`.
Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
Create a structure for the Boot Error Record Table, and a generic
table generator function.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add code for generating the region pointed to in an ACPI Boot Error
Record Table.
The BERT region must be reported as Reserved to the OSPM, so this
code calls out to a system-specific region locator. cbmem is
reported as type 16 and is not usable for the BERT region.
Events reported via BERT are Generic Error Data, and are constructed
as follows (see ACPI and UEFI specs for reference):
* Each event begins with a Generic Error Status Block, which may
contain zero or more Generic Data Entries
* Each Generic Data Entry is identifiable by its Section Type field,
and the data structures associated are also in the UEFI spec.
* The GUIDs are listed in the Section Type field of the CPER
Section Descriptor structure. BERT doesn't use this structure
but simply uses its GUIDs.
* Data structures used in the Generic Data Entry are named as
Error Sections in the UEFI spec.
* Some sections may optionally include a variable number of
additional structures, e.g. an IA32/X64 processor error
can report error information as well as machine contexts.
It is worth noting that the Linux kernel (as of v4.4) does not attempt
to parse IA32/X64 sections, and opts to hexdump them instead.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28470
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI Platform Error Interfaces definitions that will be used
for building a BERT table region in a subsequent patch. Two tables
are defined: the Generic Error Status Block, Generic Error Data
Entry.
For reference, see the ACPI specification 6.2-A tables 381 and 382.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some ACPI interfaces introduced by Chrome or coreboot do not
need drivers outside ChromeOS, for example Chrome EC or
coreboot table; or will be probed by direct ACPI calls (instead
of trying to find drivers by device IDs).
These interfaces should be set to hidden so non-ChromeOS systems,
for example Windows, won't have problem finding driver.
Interfaces changed:
- coreboot (BOOT0000), only used by Chrome OS / Linux kernel.
- Chrome OS EC
- Chrome OS EC PD
- Chrome OS TBMC
- Chrome OS RAMoops
BUG=b:72200466
BRANCH=eve
TEST=Boot into non-ChromeOS systems (for example Windows)
and checked ACPI devices on UI.
Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1078211
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Trybot-Ready: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a single function to set ACPI table versions. This allows us
to keep revisions synced to the correct levels for coreboot. This
is a partial fix for the bug:
FAILED [MEDIUM] SPECMADTFADTRevisions: Test 2, MADT revision is not
in sync with the FADT revision; MADT 1 expects FADT 3.0 but found 4.0
instead.
BUG=b:112476331
TEST-Run FWTS
Change-Id: Ie9a486380e72b1754677c3cdf8190e3ceff9412b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28276
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds 2 methods for Conginuous Performance Control that was
added in ACPI 5.0 and expanded twice in later versions. One function
will create a global table based on a provided struct, while the other
function is used to add a _CPC method in each processor object.
Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All of the callers to acpigen_write_register() also make calls to
acpigen_write_resourcetemplate_[header|footer](). This change introduces
acpigen_write_register_resource() to unify all of those trio of calls
into one. I also made the input parameter const.
Change-Id: I10b336acf9f03c423bee9dc38955b1617e11c025
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27672
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cache_sync_instructions() has been superseded by
arch_program_segment_loaded() and friends for a while. There are no uses
in common code anymore, so let's remove it from <arch/cache.h> for all
architectures.
arm64 still has an implementation and one reference, but they are not
really needed since arch_program_segment_loaded() does the same thing
already. Remove them.
Leave it in arm(32) since there are several references (including in SoC
code) that I don't feel like tracking down and testing right now.
Change-Id: I6b776ad49782d981d6f1ef0a0e013812cf408524
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Useful for debugging or for cases where we need to enter SMM.
Probably should be moved to commonlib or libpayload.
Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add DMAR RMRR table entry and helper functions, using the existing
DRHD functions as a model. As the DRHD device scope (DS) functions
aren't DRHD-specific, genericize them to be used with RMRR tables as
well. Correct DRHD bar size to match table entry in creator function,
as noted in comments from patchset below.
Adapted from/supersedes https://review.coreboot.org/25445
Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27269
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit adds support for writing ACPI _PLD structures that
describe the physical location of a device to the OS.
This can be used by any device with a physical connector, but is
required when defining USB ports for the OS.
A simple function is provided that generates a generic _PLD
structure for USB ports based on the USB port type.
Change-Id: Ic9cf1fd158eca80ead21b4725b37ab3c36b000f3
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit adds support for writing ACPI _UPC structures that
help describe USB ports for the OS.
This is a simple structure format which indicates what type of
port it is and whether it is connectable. It should be paired
with an ACPI _PLD structure to define USB ports for the OS.
Change-Id: Ide3768f60f96e9ad7f919ad3fb11d91045dc174a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds new macros to define gpio with an option to either
enable irq wake (mark it as ExclusiveAndWake flag in SSDT) or disable
it (mark it as just Exclusive flag in SSDT).
Change-Id: Ia71559dcae65112b75e4c789328e4a6153e922b0
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/25838
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MMConf is not architecture specific. We also always provide a
pci_bus_default_ops() now if MMCONF_SUPPORT is selected.
Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26062
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I54bebc245df6e967acd30a0b029557e23f8da529
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having
the interrupt handling code available to all stages. In order
to do this the idt setup is moved to a C module. The vecX
entries are made global so that a table of references to all
the interrupt vector entry points can be used to dynamically
initialize the idt. The ramification for ramstage is that
exceptions are initialized later (lib/hardwaremain.c). Not
all stages initialize exceptions when this Kconfig variable
is selected, but bootblock for the C, stages using
assembly_entry.S, and of course ramstage do. Anything left
out just needs a call to exception_init() at the right
location.
BUG=b:72728953
Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No longer needed as low memory backup is implemented as part of
the ramstage loader, when the actual requirement of the ramstage
to load is known.
Change-Id: I5f5ad94bae2afef915927b9737c79431b6f75f22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15477
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other
EN/DISABLE definition.
Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25540
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.
Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Emits a list of CPU cores, e.g.
Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 })
Tested on Lenovo Thinkpad T500.
Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides new APIs to write into EBDA area
and read from EBDA area based on user input structure.
Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch provides a kconfig option as EARLY_EBDA_INIT to
ensures user can make use of EBDA library even during early
boot stages like romstage, postcar.
Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's arch specific, so no need to pollute non-x86 with it.
Change-Id: I99ec76d591789db186e8a33774565e5a04fc4e47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21392
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is at least one I2C device (being used by Soraka) that has 3
controls -- enable, reset and stop. If the stop gpio is not put into
the right state when turning off the device in suspend mode, then it
causes leakage. Thus, we need control in power resource to be able to
stop the device when entering suspend state.
BUG=b:64987428
TEST=Verified on soraka that touchscreen stop is correctly configured
on suspend.
Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21249
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide a new function that will allow adding arbitrary properties
to devicetree entries without needing a custom driver for the device.
This will allow the 'generic i2c' driver to support kernel drivers
that need additional device properties exposed and have those board
specific properties set with values from devicetree.
BUG=b:63413023
TEST=not used yet, compiles cleanly
Change-Id: Id272256639a8525406635e168a3db5ab1ba4df6b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21269
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.
This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.
Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Update all symbols to use IS_ENABLED()
- Update non-romcc usage to use 'if' instead of '#if' where it
makes sense.
Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20005
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add additional ACPI opcodes, that are going to be used in the
following commits.
Change-Id: I20c3aa5a1412e5ef68831027137e9ed9e26ddbc9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Caching is a very architecture-specific thing, but most architectures
have a cache in general. Therefore it can be useful to have a generic
architecture-independent API to perform simple cache management tasks
from common code.
We have already standardized on the dcache_clean/invalidate naming
scheme that originally comes from ARM in libpayload, so let's just do
the same for coreboot. Unlike libpayload, there are other things than
just DMA coherency we may want to achieve with those functions, so
actually implement them for real even on architectures with
cache-snooping DMA like x86. (In the future, we may find applications
like this in libpayload as well and should probably rethink the API
there... maybe move the current functionality to a separate
dma_map/unmap API instead. But that's beyond scope of this patch.)
Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This patch adds a simple function that can be used to check if
CAR_GLOBALs are currently being read from CAR or from DRAM.
Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Create new functions similar to read and write of other sizes.
Change-Id: I35a08c498f25227233604c65c45b73b1c44fae1f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19394
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When a platform is using postcar stage it's by definition not
tearing down cache-as-ram from within romstage prior to loading
ramstage. Because of this property there's no need to migrate
CAR_GLOBAL variables to cbmem.
Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Currently only 256 bytes can be written at a time using the
acpigen_write_return_byte_buffer or acpigen_write_byte_buffer API's
and there can be cases where the buffer size can exceed this, hence
increase the number of bytes that can be written.
Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18966
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: do not use assignment in if condition
ERROR: trailing statements should be on next line
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: switch and case should be at the same indent
WARNING: char * array declaration might be better as static const
WARNING: else is not generally useful after a break or return
WARNING: storage class should be at the beginning of the declaration
WARNING: void function return statements are not generally useful
WARNING: break is not useful after a goto or return
WARNING: Single statement macros should not use a do {} while (0) loop
WARNING: sizeof *t should be sizeof(*t)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I39d49790c5eaeedec5051e1fab0b1279275f6e7f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I3495cd30d1737d9ee728c8a9e72bd426d7a69c37
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18864
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warnings detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: plain inline is preferred over __inline__
TEST=Build and run on Galileo Gen2
Change-Id: I8ba98dfe04481a7ccf4f3b910660178b7e22a4a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18863
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: space prohibited after that open square bracket '['
ERROR: space required after that ',' (ctx:VxV)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ';' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:ExV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:WxV)
ERROR: spaces required around that '||' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:WxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: need consistent spacing around '>>' (ctx:WxV)
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "foo * bar" should be "foo *bar"
ERROR: code indent should use tabs where possible
WARNING: space prohibited between function name and open parenthesis '('
WARNING: unnecessary whitespace before a quoted newline
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: Unnecessary space before function pointer arguments
TEST=Build and run on Galileo Gen2
Change-Id: I2d7e1a329c6b2e8ca9633a97b595566544d7fd33
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: open brace '{' following function declarations go on the next line
ERROR: that open brace { should be on the previous line
ERROR: else should follow close brace '}'
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I13d1967757e106c8300a15baed25d920c52a1a95
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18861
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIO edge interrupts can report that they are ActiveBoth and will
generate an interrupt event on both rising and falling edges.
Add a macro so this type of GPIO interrupt can be used.
BUG=b:35581264
BRANCH=none
TEST=successfully use this interrupt type on Eve
Change-Id: I91408386538e442bddcacc9840e0aa14370a446c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18834
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Switch some IRQ_* macros to ACPI_IRQ_* instead so they do not
fail at compile time if they are used.
BUG=b:35581264
BRANCH=none
TEST=successfully compile with ACPI_GPIO_IRQ_LEVEL_HIGH
Change-Id: Id4040eca4c7c9d8f7b4f0add411d5d6fe5ed1eb8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18833
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get
used by devicetree when necessary.
BUG=b:35585307
BRANCH=none
TEST=Add rt5514 SPI device with active high level IRQ on Eve board
and check that it is enumerated in the kernel
Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18815
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The newly assigned ACPI ID for coreboot is 'BOOT'
http://www.uefi.org/acpi_id_list
Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific
ACPI objects instead of the placeholder range of "GOOGCBxx".
Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18521
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18376
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In order to allow GPIOs to be set/clear according to their polarity,
provide helper functions that check for polarity and call set/clear
SoC functions for generating ACPI code.
BUG=None
BRANCH=None
TEST=Verified that the ACPI code generated remains the same as before
for reef.
Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add individual macros for the various interrupt types so
they can be used in devicetree.
BUG=chrome-os-partner:58666
TEST=nothing uses this yet, will be used in an upcoming commit
Change-Id: I2a569f60fcc0815835615656b09670987036b848
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18392
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move the function that adds a power resource block from
i2c/generic to the acpi device code at src/arch/x86/acpi_device.c
so it can be used by more drivers.
BUG=chrome-os-partner:61233
TEST=verify SSDT table generation is unchanged
Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a new callback to spi_ctrlr structure - get_config - to obtain
configuration of SPI bus from the controller driver. Also, move common
config definitions from acpi_device.h to spi-generic.h
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add VFCT table to provide PCI Optiom Rom for
AMD graphic devices.
Useful for GNU Linux payloads and embedded dual GPU systems.
Tested on Lenovo T500 with AMD RV635 as secondary gpu.
Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Reviewed-on: https://review.coreboot.org/18192
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18220
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and
that function is reponsible for bootstrapping the cmos post register
contents. Without this function being called none of the cmos post
functionality works correctly. Therefore, add a call to lib/bootblock.c
which the C_ENVIRONMENT_BOOTBLOCK SoCs use.
BUG=chrome-os-partner:61546
Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18043
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
