Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or
overridden by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Port of commit a182faeb88 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API")
Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Fix typo in the comment for Common Clock Configuration.
Change-Id: Idd01e787458a9090d53b9a57547b8158480dcc16
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP
section to cache the MRC training data in recovery mode.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS
directory entry is populated with the appropriate MRC_CACHE FMAP
section.
Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Use fw_config to probe fingerprint.
BUG=b:269986245
TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass
with 1000 reboot cycles.
Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:270640775
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
To support an RPL SKU on osiris, osiris must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL
FSP headers for osiris.
BUG=b:270640775
BRANCH=firmware-brya-14505.B
TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage",
flash and boot osiris to kernel.
Cq-Depend: chromium:4290627, chrome-internal:5516851
Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
It's sufficient to generate CPU devices for all available CPU cores/
threads instead of for the maximum number of possible CPU cores/threads.
TEST=google/careena with 2 cores still boots and Linux doesn't complain
about ACPI errors due to referenced but not present CPU objects.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6850edfa305304060092cb5480f4296f4f5ddacc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
On boards with RECOVERY_MRC_CACHE FMAP section, populate type 0x63 BIOS
directory entry in RO with that section. If the RECOVERY_MRC_CACHE
section is not present, then fall back to RW_MRC_CACHE.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS
directory entry is populated with the base and size of appropriate MRC
cache.
Change-Id: I49ec4f64e33c4d5780a7fe6a5540eab42b6cec9f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
If a mainboard has RECOVERY_MRC_CACHE and the recovery mode is enabled,
then use APOB data from that section and make any updates to that
section. Otherwise continue to use DEFAULT_MRC_CACHE section.
BUG=b:270569389
TEST=Build and boot to OS in Skyrim.
When in normal mode, DEFAULT_MRC_CACHE is used.
Normal Mode Boot1:
------------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[INFO ] APOB RAM hash differs from flash
[SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x0/0x1e000
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] SF: Successfully erased 122880 bytes @ 0x0
[INFO ] Updated APOB in flash
Normal Mode Boot2:
-----------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] APOB hash matches flash
When the device is in recovery mode, RECOVERY_MRC_CACHE is used.
Recovery Mode Boot1:
--------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[INFO ] APOB RAM hash differs from flash
[SPEW ] Copy APOB from RAM 0x02001000/0x1db18 to flash 0x650000/0x1e000
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] SF: Successfully erased 122880 bytes @ 0x650000
[INFO ] Updated APOB in flash
Recovery Mode Boot2:
--------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] APOB hash matches flash
Switch from Recovery Mode to Normal Mode:
-----------------------------------------
[DEBUG] FMAP: area RW_MRC_CACHE found @ 0 (122880 bytes)
[DEBUG] APOB hash matches flash
Switch from Normal Mode to Recovery Mode:
-----------------------------------------
[DEBUG] FMAP: area RECOVERY_MRC_CACHE found @ 650000 (122880 bytes)
[DEBUG] APOB hash matches flash
Change-Id: I93f357e407c98b6e5fca495f4f779fad54a3430f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
This commit separates setting FSP debug params from the rest of code and
configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8)
are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Remove world-facing microphone for xivu360.
Switching to world-facing camera will use the
user-facing microphone to record sound.
BUG=b:263927799
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
BUG=b:269786649
TEST=build and test USB2 port function works fine
BRANCH=dedede
Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
To support an RPL SKU on constitution, it must use the FSP for RPL.
Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL
FSP headers.
BUG=b:267539938
TEST=emerge-brask intel-rplfsp coreboot
coreboot-private-files-baseboard-brya
Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246
Reviewed-by: Pablo Ceballos <pceballos@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove `fixme` from gpio.h since it has been addressed.
BUG=none
TEST=Only a cosmetic change
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Update ec_commands.h from the EC repo at:
"8441cf4 Add host event: EC_HOST_EVENT_BODY_DETECT_CHANGE"
This is an exact copy of the EC repo's ec_commands.h with the
exception of updating the copyright message.
BUG=b:261141172
BRANCH=none
TEST=built coreboot for skyrim
Change-Id: I9892c0c3518f63d357459861e8fa1b7f5f494e68
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73258
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Because the ChromeOS boards don't fill a manufacturer in for the memory
SPDs, that information isn't available from the FSP. We can get the
Manufacturer ID based on the memory name from CBI instead. Use this
information to fill in an ID so that the manufacturer name is available
in the SMBIOS information.
BUG=None
TEST=Look at dmidecode output
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I810c3191180dd3b566d7ea64006f29b625b10526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
There is a Nanya device used on one of the Google Guybrush devices,
so add it to the list of SPD manufacturer names.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia449f4d14385cdd5a2548e2a05e3928ea3602c12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The DMI error correction type was not being filled in, so was reporting
as "Error Correction Type: <OUT OF SPEC>". This patch fixes that.
Since it's now filling in information for both Type 16 & 17, rename
the function to reflect that.
BUG=None
TEST=dmidecode now reports the type correctly.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6b51612d808c63de1acd2be952cb6c152f8a1be5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
SimNow does not support the Birman EC, so skip the EC configuration
steps when building for SimNow.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6e879a13a119d593674d3403d4e1b32e0e244d9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add option for mainboards to target builds for SimNow.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id765437b69f1bc3a9f9d7858edcd27e687d5a7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move 'asmlinkage' before the function type for consistency.
Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch optimizes CPU MP Init related configs being used within
multiple SoC directory and moving essential configs into common code
to let the SoC user to choose as per the requirement.
TEST=Able to build and boot google/kano and google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This reverts commit 363202b435.
Reason for revert: Seeing some bit flips on the SPI bus, but cannot
repro reliably on local builds. Going to downgrade back to 50 MHz
to see if builder builds are more stable on each variant as a result.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I4fe76bac915e3b3c794821cd160a66824e38ea83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73214
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
MT62F1G32D2DS-026 WT:B 2 (0010)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 3 (0011)
BUG=b:265190498
BRANCH=None
TEST=emerge-skyrim coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I860f10552e4e4180e09ab805ca82b108fdc8f21a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73049
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 3eb17b91da.
Reason for revert:
PLTRST only keeps 18xms and it's too short for eMMC disk fully reset.
Change-Id: If4277cb600bfe4e071959dacaf204fe7d3518f68
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73202
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This reverts commit 0e0f9e51c4.
Reason for revert:
PLTRST only keeps 18xms and it's too short for eMMC disk fully reset.
Change-Id: I13b93747bdb4d39de1ffcfdc020648871fa6e048
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73203
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15.
This patch selects ME 15 specification defined at common code and
removes elkhartlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Alderlake based SoCs uses Intel's Management Engine (ME), version 16.
This patch selects ME 16 specification defined at common code and
removes alderlake SoC specific ME code and data structures.
BUG=b:260309647
Test=Build verified for brya.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Cannonlake based SoCs uses Intel's Management Engine (ME), version 12.
This patch selects ME 12 specification defined at common code and
removes cannonlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Jasperlake based SoCs uses Intel's Management Engine (ME), version 13.
This patch selects ME 13 specification defined at common code and
removes jasperlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Icf4bc651e94d6ec977ed8f2381d7184337dc1ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73139
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tigerlake based SoCs uses Intel's Management Engine (ME), version 15.
This patch selects ME 15 specification defined at common code and
removes tigerlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: If4fbfd7c591794ed945c1e9e8487a9e9723c7551
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73138
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Meteorlake based SoCs uses Intel's Management Engine (ME), version 18.
This patch selects ME 18 specification defined at common code and
removes meteorlake SoC specific ME code and data structures.
BUG=b:260309647
Test=Build verified for rex.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I36ee66f94f0c37ab6a134e79e49da9abc83b93cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73137
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch adds ME specific source code at common location in order to
reduce maintenance efforts at SoC level and improve readability. The
functionality and code are redundant for various SoC platforms and
require more maintenance.
BUG=b:260309647
Test=Build verified for brya and rex.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ic6622662fd3b8bcc9d9ac8bd6ffa732f5d78801a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73133
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes ME specification datastructures for various ME
versions. Including the ME specification in common code will help
current and future SoC platforms to select the correct version based on
the applicable configuration. It might be also beneficial if two
different SoC platforms would like to use the same ME specification and
not necessarily share the same SoC directory.
BUG=b:260309647
Test=Build verified for brya and rex.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I83df41d7180d2df419849a0c01c728ff0fe75378
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73129
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch includes ME specification configuration for various versions,
which will allow SoCs to get ME support by selecting the correct
version.
BUG=b:260309647
Test=Build verified for brya and rex.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I817d14e52b0d353bbb4316d6362fcb80cbec3cda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73128
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Rather than explicitly checking for Recovery or Developer mode via
vboot, use display_init_required() so that vboot is not required, and
other instances where the display is needed pre-OS (such as when
applying a critical system update) are covered as well.
With this change, SoCs implementing selective GOP init will need to
select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required()
to not assert on compilation.
BUG=b:255812886
TEST=build/boot skyrim
Change-Id: Iac7e06863764a9f21c8a50fc19050cb5a6627df2
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Rather than explicitly checking for Recovery or Developer mode via
vboot, use display_init_required() so that vboot is not required, and
other instances where the display is needed pre-OS (such as when
applying a critical system update) are covered as well.
Select VBOOT_MUST_REQUEST_DISPLAY in order for display_init_required()
to function properly (and not assert on compilation).
BUG=b:255812886
TEST=build/boot skyrim
Change-Id: If2fee71bcc11468fd2db0abaafe4ea35e2953993
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The headers added are generated as per FSP v4031.01
BUG=b:270416522
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Cq-Depend: chrome-internal:5513169, chrome-internal:5511170
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ia21807ee71c98489fd96f870c2d61f54e094c3d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Define some actions based on probe results for audio:
- Disable the SoundWire GPIOs when I2S option is selected.
- Disable the I2S GPIOs when SoundWire option is selected.
- Disable all the GPIOs when no audio is enabled.
BUG=b:269497731
TEST=Test that GPIOs are configured based on the current
value of the fw_config field in cbi.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
In order to improve gpio merge mechanism. Change iteration override
to padbased table override. And the following patch will change fw
config override with ramstage gpio table override.
Port of commit 7aef2b1294 ("mb/google/nissa: Apply gpio padbased
table override")
BUG=none
TEST=Verify devbeep at depthcharge console
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The reset bit mapping was incorrectly assigned to GPIO groups. The
reset mapping for Community 0 actually reflects the GPD reset mapping.
Change the Community 0 reset mapping to the correct default map and fix
the GPD reset mapping.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2b9d093ca7ea0f5087f49671ca457c0b45927918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control
the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always disabled
for RPL & ADL-N based ChromeOS platforms.
It is not disabled for ADL-P based platforms because ADL-P FSP relies
on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit
sync doesn't occur if no MBP HOB, so it results S0ix issue. This
limitation is addressed in the later platforms so creation of MBP HOB
can be skipped for ADL-N and RPL based platforms.
This made skip_mbp_hob SOC chip config variable redundant which is also
removed as part of this change.
BUG=none
TEST=Build and boot to Google/Taniks.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
In the current Kconfig option MEDIATEK_BLOB_FAST_INIT, the meaning of
"BLOB" is unclear. Add "DRAM" to the name.
BUG=b:204226005
TEST=./util/abuild/abuild -t GOOGLE_STEELIX -x
Change-Id: Ida7bda770f1d1a40cae205b08c8cb22f2329e49f
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73155
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MX98357A is not a soundwire codec, so move it out of
drivers/intel/soundwire node.
BUG=none
TEST=Build and boot MTL-P RVP to Chrome OS. Verify I2S audio card
enumeration and no max98357a entry under /sys/bus/soundwire/devices.
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Change-Id: I24fc7084ea18445c341eed012cfacde8de126fd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
This reverts commit 272c9c07bd.
Reason for revert: Sorry was going to give +2 but pressed the submit
button and accidentally merged this out of train.
Change-Id: I8a2c6407832bdcf3d475209356501f8fc3672f6b
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73213
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Alderlake based SoCs uses Intel's Management Engine (ME), version 16.
This patch selects ME 16 specification defined at common code and
removes alderlake SoC specific ME code and data structures.
BUG=b:260309647
Test=Build verified for brya.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I94cb8a9cbb6167d1a11a012efbd6a135a8692969
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73135
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*:
Remove lapic from devicetree).
Alderlake cpu code was linked in romstage but unused so drop it.
Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Use the existing IO_APIC2_ADDR definition instead of a magic value.
TEST=Timeless build results in identical image for pcengines/apu2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ee039e23309fdae0d614bb1fb0610d82564bf3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The coreboot-common acpi_create_fadt writes a pointer to the FACS table
into both firmware_ctrl and x_firmware_ctl_l FADT fields and sets
x_firmware_ctl_h to zero. When x_firmware_ctl_[l,h] is non-zero, the
pointer in firmware_ctrl will be ignored, but that's what is already
done on Cezanne and newer.
TEST=Linux doesn't complain about any new ACPI problem on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9eab4dcf828f28a60c6312ec96872aac4cfb266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The FADT data structure is zero-initialized in acpi_create_fadt which
then calls the SoC-specific acpi_fill_fadt function, therefore it's not
needed to assign 0 to the ARM_boot_arch FADT field in acpi_fill_fadt.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2d24a9b8d5b04271eb4da6a622b5bba66dbc501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73188
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The FADT data structure is zero-initialized in acpi_create_fadt which
then calls the SoC-specific acpi_fill_fadt function, therefore it's not
needed to assign 0 to the ARM_boot_arch FADT field in acpi_fill_fadt.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ica968db1228a2d63e83f2b6c4ea57c5f02bf1504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73187
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate
when the state of charge drops to low_battery_shutdown_percent.
BUG=b:255465618
TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898)
Verify system resumes from s0ix and then enter S5 on nivviks with steps:
1. disconnect AC
2. powerd_dbus_suspend --disable_dark_resume=false
3. fakebatt 5
4. fakebatt 4
Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9
Signed-off-by: Ivan Chen <yulunchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add common device tree used for EGS platform. Also add register
setting shared for all EGS platform.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The current clock register definition is wrong, which results in wrong
audio sampling rate. Fix it by adjusting the POSTDIV registers of
APLL1-APLL5.
TEST=build pass
BUG=b:250459803, b:250464574
Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0
Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
MT8188 supports port0/port1 download. The hardware needs a trapping pin
to select the port to use. When port1 is selected, the phy of port1 will
be switched to port0. That is, port1 connector will be the physical line
of port0. Since port0 phy isn't initialized in coreboot, switch back to
port1 phy.
BUG=b:269059211
TEST=can detect USB2 devices in depthcharge.
Change-Id: Ic97d0bd9d0233883196b2e73ac2a22cd8ea9466b
Signed-off-by: Shaocheng Wang <shaocheng.wang@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
USB2 port 6 may be used for a PL2303 USB to UART bridge, so enable the
port.
BUG=b:269690930
TEST=kernel can detect a PL2303 USB device
BRANCH=dedede
Change-Id: I0ba421c3a502e69d101de40bbd31122211d3fb05
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Add functionality such that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami.
Confirmed power is off for 150ms seconds on boot.
Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
Change-Id: I21eb85dc11e0ea0eb5de8a6092b01663d3c3df91
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68820
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Phoenix2 VBIOS PCI DID is 15c8 though the VBIOS image uses a different
PCI ID i.e. 0x1205, so we need to implement map_oprom_vendev for the SoC.
Change-Id: I7eef5eb41b781f02abb9dd4098e92a8652a431f5
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
VGA defineds the extended ASCII set based on CP437, but there is a bug
on printing them: in vga_write_at_offset(), we perform a bitwise or
between 'unsigned short' and 'signed char':
```
p[i] = 0x0F00 | string[i];
```
If we want to show an extended ASCII character, string[i] will be
negative and this bitwise operation will fail due to their implicit
casting rule: convert signed char to unsigned short by adding 65536.
To fix this, we need to cast the string to unsigned char manually
somewhere. Since we still want to leverage the built-in string utilities
which only accepts const char*, we still preserve the original
prototypes before, and cast it until we write into the frame buffer.
BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage
and verify drawing characters with code > 127.
Change-Id: I9cd65fe9794e5b0d338147924f28efd27fc8a1e8
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Based on product spec v1.4, update T3 timing from 180 ms to 150 ms.
BRANCH=none
BUG=b:262734395
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0d8f1e008276fccdfbb8c76cfebaccbe71160b64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73130
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
After first recovery request coreboot would get stuck in bootloop with
VB2_RECOVERY_PREAMBLE as recovery reason due to not checking whether
coreboot is alread in recovery mode, and calling failing code.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Idc947a1d150ff6487cf973b36bf4f0af41daa220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Package C state demotion is now disabled for all RPL SoCs from within
soc/intel/alderlake/fsp_params, so no need to duplicate that in the
skolas devicetree.cb.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Change-Id: I1c630e2efbdddd18a5423c79b73269e9b1be79c7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The EFS entry at offset 0x14 can point to either the first level PSP
directory table or to the PSP combo directory structure that was used
before the introduction of the AMD A/B recovery scheme. This scheme is
not to be confused with the VBOOT scheme. The PSP verstage code checks
if the header this entry points to begins with the PSP_COOKIE, which
indicates the entry is a first level PSP directory table. Due to that,
the EFS entry at offset 0x14 is always expected to point to a PSP
directory table, so rename combo_psp_directory to new_psp_directory to
match the actual usage. This EFS entry that points to the PSP directory
table is called new_psp_directory, since the entry at EFS offset 0x10
was used on some early AMD chips to point to the older PSP directory
table and that one is already called psp_directory. amdfwtool uses the
same naming scheme for those two PSP directory table pointers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10f19ee63f8d422433dba64402d84fd6bb9e0f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73083
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive`
so their configurations are unchanged.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as if it
is not, it will break S3 exit.
When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).
This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72765
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP
programs certain registers via Notify phase ReadyToBoot and it cannot
be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we
try to set BIOS_DONE MSR as late as possible to avoid this.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add fast_spi_set_vcl() to be called by the SOC lockdown function if SPI
Vendor Specific Component Capabilities are desired.
Change-Id: I6d9b58e90fa16c539b90c6b961862e97e1bf29a2
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72478
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To make MIPI/eDP panel functional on unprovisioned devices, it requires
passing SKU ID and panel ID info to the payload(depthcharge) to load the
corresponded device tree for kernel.
BUG=b:247415660
TEST=cbmem -1 |grep "SKU Code".
Change-Id: Id2254729b7bd621d1e9bc520e8f40916d0f81030
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73076
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds enable/disable FSP DisableEnergyReport feature
option to be used in devicetree for power instrument purpose.
BUG=None
Branch=None
Test=Build and boot MTL RVP.
Signed-off-by: Yong Zhi <yong.zhi@intel.com>
Change-Id: I58d4aea28ee2561d2ed73260c40cb22ce3fdd135
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Replace the magic number with the CPUID_FROM_FMS macro to make it easier
to read.
TEST=Resulting image of timeless build for pcengines/apu2 is identical
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I15480dc883b65b5ffaf0cd38cf4e1f7b2222022e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73069
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having two entries for two different steppings of the same
family and model combination using the CPUID_EXACT_MATCH_MASK, just have
one entry that uses CPUID_ALL_STEPPINGS_MASK to cover all steppings.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0118bb9b4b0be4d954a657d50789addca08a784e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73068
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The platform supports a discrete LPC TPM module. However, ME firmware
enables PTT by default and descriptor is configured for SPI TPM on the
platform's original firmware. So disabling PTT in ME is not enough,
because it falls back to SPI TPM. Ensure PTT is disabled in ME and SPI
TPM is disabled in descriptor soft straps.
TEST=Boot VP4650 and see LPC TPM is recognized by coreboot.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3764e085f2eb5ae957b9087d150320def7af4fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Based on product spec v1.4, update T3 timing to 150 ms from 300 ms
BRANCH=none
BUG=b:269041202
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the Elan touchscreen works fine.
Change-Id: Ie5bd4bc2c8be2e43470edd374af0623162067497
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
Some users of MSI Z690-A board reported non-working IGD display
during post using various CPUs. As not all PCI IDs were hooked,
coreboot didn't detect GOP-provided framebuffer nor passed the
framebuffer information to the payload, causing a black screen.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I07584e07182ee56b61b6f751100431589d1cbe83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add NO_S0IX_SUPPORT for boards that do not support, or do not want
to support S0IX.
As all the boards in the tree that do this, don't support D3Cold,
add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is
selected to disable D3Cold support.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I03378cc7bb76fd65fcec81018e47f6288d437cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Besides crashlog, there's also other errors such as MCA error, which
should be recorded in BERT table. With current code, BERT table is
not generated if crashlog is not enabled. Add if statement for
SOC_INTEL_CRASHLOG so that MCA error can be recorded in BERT table
when crashlog is not supported.
For some server mainboard, crashlog is supported through BMC instead
of host firmware.
Also check if BERT region is generated when crashlog is not enabled.
Change-Id: I323ca889eef2b246fc4e062582d2d11b4213316f
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Enable HDA device and update jack codec HID from ALC5682I-VD to
ALC5682I-VS.
BUG=b:268309238
TEST=kernel detects audio DSP and rt5682s
BRANCH=dedede
Change-Id: Icd17d5009ab8ef4711bb6c5fa414a8188fc0912f
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
pmc_lock_smi() and pmc_lockdown_config() have PCH specific
implementations. Move them from common lockdown.c and pmc.c
into lbg/soc_pmutil.c.
Move sata_lockdown_config() and spi_lockdown_config() to
lbg/lockdown.c.
While here, fix some coding style issues.
Change-Id: I9b357ce877123530dd5c310a730808b6e651712e
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
BUG=b:265611305
TEST=Reboot test 2500 times pass
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Change-Id: I2b114cac58a7fadeaee6d48996cb8b51f192e78f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This patch improves `incomplete` debug messages for missing ACPI
name PCI devices.
Additionally, using the proper PCI device B:D:F to locate the device
with the missing ACPI name.
Finally, modify the msg time from Debug to Warning to make it more
purposeful.
TEST=Able to build and boot google/rex.
Without this patch:
```
[DEBUG] dev->path.devfn=10
[DEBUG] dev->path.devfn=a2
[DEBUG] dev->path.devfn=b0
```
With this patch:
```
[WARN] Missing ACPI Name for PCI: 00:02.0
[WARN] Missing ACPI Name for PCI: 00:14.2
[WARN] Missing ACPI Name for PCI: 00:16.0
```
Change-Id: I605e59de8cbec18c9a56eaa6e90a34f36ea4cdd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73072
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch fixes the wrong warning msg around `Unknown min d_state`
with having proper PCI Bus/Device/Function number to help to parse
the log better.
With this patch:
[WARN ] Unknown min d_state for 20
[WARN ] Unknown min d_state for 50
[WARN ] Unknown min d_state for 98
[WARN ] Unknown min d_state for 9a
[WARN ] Unknown min d_state for f9
With this patch:
[WARN ] Unknown min d_state for PCI: 00:04.0
[WARN ] Unknown min d_state for PCI: 00:0a.0
[WARN ] Unknown min d_state for PCI: 00:13.0
[WARN ] Unknown min d_state for PCI: 00:13.2
[WARN ] Unknown min d_state for PCI: 00:1f.1
Change-Id: Iccaf26882ce5998469b2be6cf5bc7082f193cb29
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Yabits is no longer maintained and git repo is archived.
Yabits has not been maintained for a long time,
the project is apparently closed.
Change-Id: Ida0bb79342448510d2c309339fabbe8066eca73c
Signed-off-by: Elias Souza <eliascontato@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
According to the author of the mainboard scaleway/tagada, the mainboard
is not used anymore. Since the mainboard is not publicly available for
purchase and not used anywhere else, the usual deprecation process
of 6 months is not needed.
Thus, to reduce the maintenance overhead for the community, support for
the following components will be removed from the master branch and will
be maintained on the release 4.19 branch. Also, add a note to the 4.20
release notes.
* Mainboard Scaleway Tagada
Change-Id: Ifb83b8f2b1dc40cbef657e52c629948dc466ec6e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72915
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`stddef.h` should only provide the definitions defined by ISO or Posix.
The included `commonlib/bsd/helpers.h` provide a lot of non standard
definitions that may interfere with definitions from the application.
Change-Id: Ia71edbc3ffe6694ff4b971decf3a41f915264bc8
Signed-off-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70116
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in
Mendocino's Kconfig instead of relying on the board's .config files
providing the correct settings. Those settings are per-SoC and not
per-board, so this is valid for all boards using the Mendocino APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I09c537d3801123e7ffc01608171918b0396b7a5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add the correct defaults for VGA_BIOS_ID and VGA_BIOS_FILE in Cezanne's
Kconfig instead of relying on the board's .config files providing the
correct settings. Those settings are per-SoC and not per-board, so this
is valid for all boards using the Cezanne APU.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67101d518c6b873ad89932ae39c2deb2ed6a4c29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
map_oprom_vendev_rev is implemented in graphics.c in the SoC directory.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0123cb8ff662445fd0a613711d9e1981272b1235
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add a new baseboard for hades, an Intel RPL based reference design.
Also, add variants for the reference boards hades. This commit is
a stub which only adds the minimum code needed for a successful build.
Need update gpio and memory DQ pins after final shchematic comes out.
BUG=b:269371363
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib7fbdf997df8225cc7814a34f8b4e4e04884dbf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic96846d74df2dc279e13b22f2a83b6f893954fe8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73009
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I26b96966495dc35a8b4a0cb7d5a841f3812f2a70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73007
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The way the PSP_APCB_FILES list is created will always insert at least a
space into it. When tested by the if, this space will prevent the else
clause from ever running and never generate a build error.
Remove the non-functional check. Instead, mainboards should select
warn_no_apcb or die_no_apcb to generate a warning message or build error
if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib9fe0f05739fb19da2494629dc1d5aaa0ca6431f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73006
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add target to die when no APCB is found. This is not always a fatal
case, so mainboards can select between this and warn_no_apcb.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5bbc8dd3200c4781677411e67a4b5f1fe8b20286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will
use ARMv8 Crypto Extension for SHA256[1] instead of software
implementation.
This will speed up firmware verification in verstage.
[1] https://crrev.com/c/4170144
BUG=b:263514393
BRANCH=corsola
TEST='calculating body hash (SHA2)' get 13 msecs improvement on
Tentacruel.
Before:
509:finished calculating body hash (SHA2) 161,548 (14,490)
After:
509:finished calculating body hash (SHA2) 155,101 (1,187)
Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72711
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72422
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_ON() calls _STA() at the beginning. If _STA() indicates the device is
ON, it exits immediately. The solution is to move this _STA() check
into the ONSK logic. In general cases, ONSK remains '0'.
NOTE: RTD3 provides a way to skip _OFF() and _ON() methods following
by a device reset such as WWAN device. When such device calls its
_RST(), it increments OFSK. When the following _OFF() is called, it
was scheduled to skip, it will also increments ONSK. Similarly, when
the following _ON() is called, it checks if the previous _OFF was
skipped or not. If skipped, it needs to do the same. In normal
suspend/resume cases, these two variables remains '0'. No _OFF() and
_ON() calls are skipped.
entire generated code:
Method (_ON, 0, Serialized) // _ON_: Power On
{
If ((ONSK == Zero))
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
Return (One)
}
Acquire (\_SB.PCI0.R3MX, 0xFFFF)
EMPG = Zero
Local7 = 0x06
While ((Local7 > Zero))
{
If ((AMPG == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
Release (\_SB.PCI0.R3MX)
\_SB.PCI0.PMC.IPCS (0xAC, Zero, 0x10, 0x00000020, 0x00000020,
0x00000020, 0x00000020)
\_SB.PCI0.STXS (0x015E)
If ((NCB7 == One))
{
L23R = One
Local7 = 0x14
While ((Local7 > Zero))
{
If ((L23R == Zero))
{
Break
}
Sleep (0x10)
Local7--
}
NCB7 = Zero
Local7 = 0x08
While ((Local7 > Zero))
{
If ((LASX == One))
{
Break
}
Sleep (0x10)
Local7--
}
}
}
Else
{
ONSK--
}
}
BUG=b:249931687
BUG=b:241850118
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Id1ea2e78e98d334a90294ee6cdd14ae2de9b9b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72826
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When the flash size is over 16M, the absolute address could be lager
than 16M, which can not be taken by CBFS. For the relative address, it
is more flexible.
This is one of series of patches to support 32/64M flash.
BUG=b:255374782
TEST=binary identical test on birman and mayan when
CONFIG_BIRMAN_HAVE_MCHP_FW and CONFIG_MAYAN_HAVE_MCHP_FW are set as
y.
Change-Id: I65be3039cd3449bfb481ad87281b72e88a58bd45
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Select DEBUG_SMI and RUNTIME_CONFIGURABLE_SMM_LOGLEVEL.
Tested=On OCP Delta Lake, SMM log level can be changed via VPD variable.
Change-Id: I73afc944fbd6c21e884397f3049bd363e2c1ce2c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47006
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
VPD variable 'smm_log_level' can be read and passed to SMM for
overriding SMM log level. By default it's zero therefore it disables
most of the SMM log. When we need to see SMM log we can set this VPD
to a larger value to enable it.
Implement mainboard_set_smm_log_level() that reads VPD variables for SMM
log level.
Change-Id: I90d471d1d070d9a0f1a82ca9da8a2c034c9fd574
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71992
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This patch ensures avoiding displaying wrong warning msg as
`Graphics hand-off block not found` during ChromeOS normal mode
booting as FSP is not executing GFX PEIM hence, GFX hand-off HOB
is expected to be missing.
TEST=Able to build and boot google/rex in normal mode w/o having
warning msg.
Change-Id: Ia9192129852195f6183c0c43369cd33b253f9140
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid
prompting wrong dmesg as below.
```
usb usb2-port3: Cannot enable. Maybe the USB cable is bad?
```
Mainboard variants to override the USB ports as per the target
board design.
TEST=Able to build and boot google/rex with all USB ports are
working as expected.
Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add a Kconfig RUNTIME_CONFIGURABLE_SMM_LOGLEVEL that enables
mainboard to override mainboard_set_smm_log_level for SMM log level.
This can let SMM have different log level than other stages for
more flexibility.
Another reason is that getting certain data that requires searching
from flash VPD or CMOS is not very ideal to be done in SMM, so in this
change the value can be passed via the member variable in struct
smm_runtime and be referenced directly in SMM.
One example is that mainboard can get the desired SMM log level from
VPD/CMOS, and pass SMM console log level via the variable and in SMM
it can be referenced in get_console_loglevel() override function
directly.
Tested=On OCP Delta Lake, verified SMM log level can be overridden.
Change-Id: I81722a4f1bf75ec942cc06e403ad702dfe938e71
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49460
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
While executing S0ix tests on Raptor Lake boards, we observed CPU fails
to enter suspend state, causing failure.
As a workaround, disable package C-state demotion, till this issue
is fixed in ucode.
BUG=268296760
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Some platforms have an onboard speaker which could be used as an
indicator of successful boot or critical error, e.g. in die_notify
function. The function assumes that SPKR GPIO is properly configured
by the platform code.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8189b3462bb5140af352fa786db3a6a2a45076f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs
to ADL not RPL, though some RPL SoCs are also using ADL PCH.
Hence correct the name reporting to avoid confusion when ADL SoCs
were used.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) Samsung K3KL8L80CM-MGCT
2) Hynix H58G56BK7BX068
3) Micron MT62F1G32D2DS-026 WT:B
4) Micron MT62F512M32D2DR-031 WT:B
5) Hynix H58G56BK8BX068
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I1f650c7e90804e871572f42ac925da85afd7f9d3
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72886
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyle Lin <kylelinck@google.com>
Add support for MTL-P RVP mipi camera functionality
BUG=None
TEST=Build and boot MTL-P RVP to Chrome OS. Verify SSDT entries
related to mipi camera and verify camera working.
Scope (\_SB.PCI0.I2C1)
{
Device (CAM0)
Scope (\_SB.PCI0.I2C0)
{
Device (CAM1)
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I698edd7155fc38477f3416900799e61d3295fd1a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Use the common missing APCB warning when the APCB is missing
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie6303bc3457731bcac322770c4c08712f89fce3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move missing APCB warning from birman to amd/common so that other
mainboards can utilize the same warnings if the APCB is missing.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7ae689726ae4f7ccdf6959e47cbb5aee15cdb690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Extend the coverage of the 'ifeq ($(CONFIG_SOC_AMD_COMMON),y)' case to
the entire file. This matches the coverage of the related Kconfig.
Add comments to endif to show which if they are ending.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I369e23e7ee9463ca1ae487d1e2181c760ae1bab2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70208
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adjust timing parameters on i2c1 and i2c2 to meet timing requirements.
For SCL, the t-high time is now over the min 600ns requirement
for 400KHz operation (measure at over 700ns). Also, this change
does not violate other parameters - rise time, setup time and hold time.
BUG=b:264704732
TEST=Verified all timings meet spec now
Change-Id: I0e92b2c9c25e7fb5fa7082af3f4a88da168c3ef2
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The NVPCF DSM subfunction specified a incorrect checksum.
Update this function to the proper checksum of 0xaf.
BUG=b:214581372
TEST=build
Change-Id: Ib58bd6cc10703ca67a7a4f520273865a95a4702b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch enables S0ix for MTL-P RVP platform
BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Since it actually depends on the SoC type whether the old PSP
directory table pointer or the new comboable PSP directory table
pointer is used in EFS, get this information from the SoC ID instead
of passing the comboable flag for the SoCs that need to use the new
comboable PSP directory table pointer.
TEST=Binary identical on amd/majolica, pcengines/apu2, amd/gardenia
Change-Id: I0c3f21065939d1b13c2607aba16cbef74dd8d389
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Create the whiterun variant of the skyrim reference board by
copying the winterhold files to a new directory named for the variant.
BUG=b:265955979
BRANCH=None
TEST=emerge-skyrim coreboot and boot up on Whiterun
Change-Id: I3539f84e79c05936fe006bfe9d08743d6a9a6ba7
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72483
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a FMAP region to support caching GOP-driver-modified VBIOS tables.
Select SOC_AMD_GFX_CACHE_VBIOS_IN_FMAP if CHROMEOS && RUN_FSP_GOP.
Default USE_SELECTIVE_GOP_INIT to y if CHROMEOS && RUN_FSP_GOP.
BUG=b:255812886
TEST=build/boot skyrim, verify cached VBIOS data differs from VBIOS
in CBFS, cached VBIOS data is used when not booting in recovery
or developer modes.
Change-Id: I5857fa4a15250bf6478bffa96b16200e318492b1
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Commit 45b1da33c8 ("mb/google/hatch: split up hatch and puff
baseboards") moved puff out from under hatch into its own
mainboard dir, but this basebaord include was left behind.
Delete it as it's not needed.
TEST=build hatch variants
Change-Id: I9045c52006fd232552541d68972d831c8b52da27
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Allows Windows/Linux driver to use the proper jack eject debounce time.
Credit to coolstar for identifying the issue.
Change-Id: I32b94b9285f7c85ff1d67b3d78c845835bbf90d7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT.
Fixes warning shown in Linux:
ACPI Error: AE_NOT_FOUND, While resolving a named reference
package element - \_SB_.PCI0.SATA (20220331/dspkginit-438)
Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The PPCC method should return the package, but is missing the return
statement, leading to DPTF/S0ix to not function properly. Add the
required return statement.
TEST=build/boot Win11 on google/banshee, verify DPTF, S0ix functional.
Change-Id: I051db7d69dd6cdfbb07caf649247ee166c1c74ac
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72921
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch overrides `SkipExtGfxScan` UPD as the Rex device is
equipped with an on-board graphics device hence, skip scanning
external GFX devices.
BUG=b:228002764
TEST=Able to save ~1ms+ boot time on google/rex.
FSP FPDT Data is showing the timestamp between those function calls.
Without this patch:
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22
[INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131
With this patch:
`CheckOffboardPcieVga` is not getting called.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch allows override to the `SkipExtGfxScan` UPD.
Ideally a platform with an on-board graphics device should skip
scanning external GFX devices aka set this UPD to `1`.
BUG=b:228002764
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00e15b71ed67119df9ca6f98a750ede109ff33fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support for the selective GOP init feature by only running the FSP
GOP driver when necessary: if the FMAP cache is invalid, or if the
board is booted in either recovery or developer mode.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I7ddadc254e05aca0fdd7a9567160a9329cb0e15c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Write the SHA256 hash of the cached VBIOS data when saving to FMAP,
and use it to validate the data read from FMAP on subsequent boots.
Add TPM2 as a dependency to the selection of VBIOS_CACHE_IN_FMAP.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I9c8f23b000b90a1072aeb7a57d3b7b2b2bc626dc
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72402
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add methods to store and retrieve the hash of the data stored in the
VBIOS cache FMAP region. Add a dedicated index in TPM NVRAM to store
the hash, and methods to calculate/read/write it.
Modeled after mrc_cache_hash_tpm.{c,h}
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: I030017d3bf956b8593bc09073ad6545b80a5b52b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Make does its work in two distinct phases. The first one basically
initializes and expands all variables, which are not in a recipe and
the second expands all variables inside recipes and then executes the
recipes if necessary.
Currently on some mainboards it can happen that cpu_microcode_bins
variable is filled with microcode paths AFTER swid-files-y is expanded
in the prerequisite for the sbom rule. That causes the
"$(build-dir)/intel-microcode-%.json pattern matching rule not to be
invoked. At the time, when the recipe is executed however (second phase
of make), swid-files-y will now contain the cpu microcode paths from
cpu_microcode_bins. That causes the goswid tooling to fail since the
necessary files were never created, since
"(build-dir)/intel-microcode-%.json" target was never executed.
In order to trigger the expansion of swid-files-y at the second make
phase (after cpu_microcode_bins is fully filled), this patch makes use
of make's secondary expansion feature.
Before on some boards (including samsung/lumpy) the goswid tool
complained about not finding the microcode sbom files.
Test: build samsung/lumpy with CONFIG_SBOM_MICROCODE=y
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I884469a388fd48be89d74ccda686dd8f299d63eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
By saving the results of amdfwread into a file, it only needs to be run
once instead of every time amdfwread-offset-size-cmd is called.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1afaf65b9b2f9fb856aefc3ff37fb3a3442f6369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72924
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To assist in debugging, add a way for PSP_verstage to send postcodes to
the system.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH.
BUG=b:263548436
TEST=emerge-brask coreboot
Change-Id: Iffbc9dc932325cdd2176b36795a2ff1b3690fbf8
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72941
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH.
BUG=b:263548436
TEST=emerge-brask coreboot
Change-Id: I610d53059e86945693bc5b3d7e43462e53640564
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72940
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The correct ACPI device for DPTM is TCPU; fixing this puts the
participant devices under the correct parent device, and allows
Windows to properly go into S0ix.
TEST=builb/boot Win11 on google/banshee, verify Si0x functional.
Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Instead of using PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC), use the equivalent
SMBUS_DEVFN define.
Even though the FCH IOAPIC is in the LPC part of the FCH, it needs the
IVRS IOAPIC table's source_dev_id field set to SMBUS_DEVFN which is the
function 0 of the FCH PCI device. LPC is function 3 of the FCH device.
When assigning LPC_DEVFN to source_dev_id, the kernel from Ubuntu
2022.04 LTS complains about the IOAPIC part of the IVRS table being
wrong:
AMD-Vi: [Firmware Bug]: : No southbridge IOAPIC found
AMD-Vi: Disabling interrupt remapping
With SMBUS_DEVFN being used as source_dev_id, no such error is reported.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8470d67b2513031e75fb422d4c1c181e017ace0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE
regions to fit. This requires moving memory addresses around to prevent
overlapping memory linker errors.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Glinda and Phoenix have different requirements, so split the birman FMD
files to better apply to each SoC.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia2dbaeb8af04fb1d1224c397d728929c50800dfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3919fba40f22ee84b0a3eee1ac7b6e48c076d713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I15e29443d2735342a5a43339f5bb095e5115349c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update the fmap_config.h dependency now that SMMSTORE is compiled into
all phases. This makes parallel builds work again.
Change-Id: Ie8a44c28ea9f3d4794f06d0fd320f5c765513a32
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Some of the eDp panels use 6bit color depth as default.
Set the default color depth configuration to 6 bit when there
is no match with the supported color depths.
BUG=b:255870643
TEST=Validated on sc7280 Zombie development board
Change-Id: I2cea10ad417a05f020e4c418f15212fee06a2369
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72744
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC.
In such case, is_pci64bit_alloc() return 1.
Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72441
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow other drivers to use the SMMSTORE region device.
Change-Id: I6316b703829590bd6f41c3d4013b4a4660b9cbab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The function has already moved to fw.cfg.
4/5
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: Idf9e491ed46ae574ccd17f24925e3e5c595039fa
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use existing functions instead of open-coding the same functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie35c7e0fd3caa25b0d3d02443609e54dd2fdcb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
acpigen_write_rom open-codes this functionality, so add a function for
this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ief25dd854d1639a295c021e9d02c05b4cc61109c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Use existing functions instead of open-coding the same functionality.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I660bd5d357eb86c19a5a7847925f6176c3fb4425
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Update Power Limit1 (PL1) minimum value to 15W based on the Brya
design.
BRANCH=firmware-brya-14505.B
BUG=b:235311241
TEST=Built and tested on Brya system
Change-Id: Ifd5256221b82eae2cfe8009918f8ff4791751b4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update Power Limit1 (PL1) minimum value to 15W based on the skolas
design.
BRANCH=firmware-brya-14505.B
BUG=b:235311241
TEST=Built and tested on Skolas system
Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72727
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast.
BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Brya system
Change-Id: I58bc7132086b0776ee191a242bd1302554f3854f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72867
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast. This change is based on the discussion on
bug:235311241 comment#7.
BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Skolas system
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71692
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The keyboard reset is not being used on this board, so disable the
functionality.
BUG=None
TEST=Check register values
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
For MDN, PHX, & Glinda platforms, the Keyboard Reset functionality has
been moved from GPIO 129 to GPIO 21.
Additionally, the issue where the system would reset when the KBDRST_L
pin went low even when not configured for Keyboard reset seems to have
been fixed, so remove that text.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iefe7e00d63777577b59ee98cb974b07afea1fd12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72912
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
One of the main functions performed by the FSP GOP driver is to modify
the ATOMBIOS tables (part of the VBIOS) in memory based on the display
output configuration. This device-specific modified VBIOS can be cached
in a FMAP region specific for that purpose, then loaded into memory
instead of the "generic" VBIOS, saving the ~130ms execution time of the
GOP driver.
As this approach only works when no pre-OS display output is needed,
limit its use to ChromeOS builds, with the GOP driver enabled, and
not booting in either recovery or developer modes.
SoCs supporting this feature will need to selectively run the FSP GOP
driver as needed, using the same criteria used here to determine
whether to load the VBIOS from CBFS or from the FMAP cache.
Boards utilizing this feature will need to add a dedicated FMAP region
with the appropriate name/size, and select the required Kconfig options.
BUG=b:255812886
TEST=tested with rest of patch train
Change-Id: Ib9cfd192500d411655a3c8fa436098897428109e
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
The SPI BIOS decode lock bit needs to be set, according to
Intel EBG EDS dodcumentation.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3366817b42a5878f16575698ebc546fa7852e285
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
The patch adds support for new Meteor Lake MCH (ID:0x7d16).
TEST=Build and boot the system having MCH ID:0x7d16.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib0c9ce5c58e4bdec5e7245840f0892d651922cd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Enable DPTF functionality for Meteor Lake based mtlrvp board
BRANCH=None
BUG=None
TEST=Built and booted on mtlrvp board
Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Using a &uint64_t as a string argument does not include the required
NULL character termination. Update the format string to only print the 8
desired characters and not continue printing stack memory until a NULL
is found.
Before:
[EMERG] Invalid UPD signature! FSP provided "AMD_01_M;....`", expected was "CEZANE_MAMD_01_M;....`".
After:
[EMERG] Invalid UPD signature! FSP provided "AMD_01_M", expected was "CEZANE_M".
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib334daa8518a92e0cf3d22c4d95908f4c84afe04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72911
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit ae20d4c78f ("mb/google/volteer: Fix USB4 enabling for volteer
family") reworked the USB4/TBT config for volteer, but drobit variant
was missed for some reason. Add the missing USB4/TBT entries.
TEST=build/boot Windows on drobit, verify USB4/TBT functional.
Change-Id: I43d771eeaf29b4e141b222ccb05af5cb7ceedc6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit 525c61f74e ("mb/google/hatch: Implement touchscreen power
sequencing") contained a copy/paste error; KOHAKU's enable GPIO is set
twice in ramstage, and the reset GPIO not at all, leading the
touchscreen to not be detected.
Correct the copy/paste error by replacing the 2nd instance of GPP_C12
with GPP_D15.
TEST=build/boot Windows/Linux on KOHAKU, verify touchscreen works.
Change-Id: I08d35f1e2a951cdaa463daa34df2134fdc8c65c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enables display backlight control under Windows.
VBT extracted from stock ChromeOS firmware Google_Drallion.12930.543.0.
TEST=build/boot Win11 on drallion, verify OS backlight control
available and functional.
Change-Id: I85065f22b825a7616fa4ac632c42ae7972091e24
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Under Win11, a longer delay after asserting reset is needed for the
Goodix touchscreen to init properly. Increase the reset delay to match
that used for the Goodix touchscreen by other volteer variants (120ms).
TEST=build/boot Win11, Linux on eldrid variant with Goodix touchscreen,
verify functional.
Change-Id: I489f037f0bbade9567aad2ad64404a5ac66965d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Not all firmware which uses VPD uses both RO and RW regions, so either
one not existing is not necessarily an error.
Change-Id: I50f43a25ee24a642c39e2f0b52de2d4fef023f3b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72476
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Some older devices use the vpd key 'ethernet_mac' vs 'ethernet_mac0'
for the first/only LAN NIC, so don't treat the key lookup as an error.
If no MAC is able to be found, another error will be printed later
in the driver init.
TEST=build/boot google/fizz, dump cbmem log, verify 'ethernet_mac0'
lookup failure printk output at warning level.
Change-Id: If5226f4686a819a7020fd14f130181420ee1462b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add EC_HOST_EVENT_USB_MUX to MAINBOARD_EC_S0IX_WAKE_EVENTS for
brask. Without it EC won't send host event to wake AP when USB
MUX is changed during S0ix. It's there for brya but missing
for brask.
BUG=b:267573651
TEST=emerge-brask coreboot
Signed-off-by: Derek Huang <derekhuang@google.com>
Change-Id: Id08d9aec9ab3566176369f2ca25cd00b9f0a0ca5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This reverts commit 8e1bb93fb8.
Reason: Enabling L.2 breaks some devices on this bridge. Reverting
until a workaround is found and additional testing is done.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
The desktop 9 series PCHs should be the same as the 8 series PCHs.
Change-Id: Iee93fee4f28b88a72c537944159fb7cbb2796235
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Hook up the `wake_on_usb` EEPROM setting so that it works as intended.
TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3.
Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO 67 is not currently used on skyrim, so set it as no-connect.
Since it's now free for other purposes, make sure that the
SPI-ROM-SHARING functionality is disabled.
BUG=b:268330591
TEST=Examine registers after change
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
BUG=None
TEST=Verify that DMI type 3 - Chassis Information Type field has changed
from Desktop to Laptop
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I76c8970fe3fdc2ea322a07f114ad03a0373e152c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72907
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the missing APCB warning to the end of the build and make it stand
out better. Prior to this patch, the warning would appear as one of the
first build messages and easily be missed due to the rest of the build
messages.
TEST=build with and without proper APCBs being found, warning message
appears only when APCB is not found and stands out more
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iabe32636b8e31fe781519533a329a08535bd661a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Instead of having a magic entry in the CPU device ID table list to tell
find_cpu_driver that it has reached the end of the list, introduce and
use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is
compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID
instead of the 0 in the CPU_TABLE_END definition.
TEST=Timeless build for Mandolin results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
1. add functions to generate if greater than conditions:
acpigen_write_if_lgreater_op_op:
if (op1 > op2)
acpigen_write_if_lgreater_op_int:
if (op > val)
acpigen_write_if_lgreater_namestr_int:
if (namestr > val)
2. add function to assignal value to a namestr
acpigen_write_store_namestr_to_op:
namestr = val
TEST=Use above functions and check the generated SSDT table after OS
boot.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Iffe1b23362a7ab58bdc2aa8daf45cd6f086ee818
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72825
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When enable_gpio is used as active low output, the _STA returns
incorrect value.
Also, simply the logic for _STA method.
When enable pin is used for _STA:
| polarity | tx value| get_tx_gpio() | State |
| active high | 0 | 0 | 0 |
| active high | 1 | 1(active) | 1 |
| active low | 0 | 1(active) | 1 |
| active low | 1 | 0 | 0 |
When reset pin is used for _STA:
| polarity | tx value| get_tx_gpio() | State |
| active high | 0 | 0 | 1 |
| active high | 1 | 1(active) | 0 |
| active low | 0 | 1(active) | 0 |
| active low | 1 | 0 | 1 |
Generated _STA method:
Ex: for using active low power enable GPIO pin GPPC_H17:
Method (_STA, 0, NotSerialized) // _STA: Status
{
Local0 = \_SB.PCI0.GTXS (0x5C)
Local0 ^= One
Return (Local0)
}
TEST=Check the SSDT when booted to OS.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie6f1e7a5b3e9fd0ea00e1e5b54058a14c6e9e09e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72421
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard name is Compal JBL00. This is based on the GM45/ICH9M chipset
and uses DDR2 RAM. The EC is a SMSC MEC5035 which has internal flash, so
there's no issue about making sure to include the EC firmware in the
BIOS region. This only supports the variant with integrated graphics
only, the version with a discrete Nvidia Quadro NVS 160M is not
supported.
This port was based on the Lenovo T400 port.
Working:
- USB EHCI debug (lower USB port on right side)
- Keyboard
- Touchpad/trackpoint
- VGA
- Displayport
- ExpressCard
- Audio
- Ethernet
- mPCIe WiFi
- mPCIe Bluetooth (uses USB)
Not working:
- Brightness hotkeys
- Physical Wireless switch
- SD card slot: Linux outputs an "irq 18: nobody cared" message when
inserting a card, after which it disables the IRQ
Unknown/untested:
- Dock
- Smartcard (slot and contactless)
- Firewire
- eSATA
- TPM
- Battery (my battery is at the end of its lifespan)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For Carrizo, the soc name was set as UNKNOWN.
The change is supposed to be binary unmodified, except the SPI
settings. According to the spec, the Stoneyridge and Carrizo have the
same definition of SPI setting in EFS.
Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Found by linter
Change-Id: I7a49cce0b56cf83d0e4490733f9190284a314c4a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
"break" is useless after "return".
Change-Id: I84bc506a3d50e937797f42659299bf90ce392e09
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The AMD SimNow tool supports fast logging through an IO port. Add a new
console to support SimNow logging through port 80.
TEST=observe significant speed improvements on SimNow console log
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42a431f48ea14ba4adacbd4a32e15abe7c5e4951
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the
power-on sequence for BOE_TV110C9M_LL0.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The regulator MT6359P is needed by both firmware display and SD card.
To avoid duplicate initialization in ramstage, publicize init_pmif_arb()
as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would
save 13 ms for boot time on Geralt.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch removes hybrid_storage_mode variable from
soc_intel_meteorlake_config struct since hybrid storage is no longer
supported on Meteor Lake platform.
TEST=Verify the build for Rex board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I40ec3775b827ab6e1ebd4778c6c8e13eac1944e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Move eMMC init from depthcharge into coreboot to remove it from the
critical boot path. Doing so saves us almost 35ms on villager:
before change:
finished storage device initialization 50,783
after change:
finished storage device initialization 16,255
BUG=b:254092907,b:218406702
BRANCH=None
TEST=flash new FW onto villager and make sure can boot from eMMC
Change-Id: I1af1ec162029120332e7f531f75c3780266d322b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Remove the commented VBOOT_VBNV_CMOS Kconfig option as well as VBOOT for
emeraldlake2.
BUG=b:235293589
TEST=none
Change-Id: Ie583dcf615573784c657b9d220ad417b05704150
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for z220_series.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
BUG=b:235293589
TEST=./util/abuild/abuild -t HP_Z220_CMT_WORKSTATION -a \
# with VBOOT enabled and a custom FMDFILE with RW_NVRAM region
Change-Id: I1c60a44fb12fd093f45cf54ef2f9e0e02afc80bd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz for starting next phase.
BUG=b:267539952
TEST=None
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id46201351780bb5bc05422ff36dad6972285690e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Create the aurash variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:263691099
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_AURASH
Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add NO_S0IX_SUPPORT for boards that do not support, or do not want
to support S0IX.
As all the boards in the tree that do this, don't support D3Cold,
add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is
selected to disable D3Cold support.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This is required to prevent the EC from shutting down the system after
about 15 seconds after being turned on. If the EC doesn't receive a
command meaning "CPU OK" it assumes that the processor has failed and
flashes a diagnostic code on the keyboard LEDs to indicate this.
This also enables the keyboard and trackpad/trackpoint interfaces.
Parts of this code were derived from yet-to-be merged code in CB:44975
(ec: Add support for MEC5055 for Dell laptops) written by Iru Cai.
Tested on a Dell Latitude E6400
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: Ia420cd51e9a64be5eee4af2c0d113618575522b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update ec_commands.h from the EC repo at:
"8b6f7de2a7 fan: update fan stalled value reporting"
This is an exact copy of the EC repo's ec_commands.h with the
exception of updating the copyright message.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: I4ce15e1af40cc54a6cf2ebd6f5d5adf8953dee60
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This is a format-only change: Reformat ec_commands.h using clang-format
according to the EC repo's current formatting style.
The command is:
clang-format --style=file:$EC/.clang-format -i ec_commands.h
where $EC points to the chromeos EC repo.
The EC repo has recently adpoted the practice of formatting all files
through clang-format using its own style. So, run ec_commands.h through
the EC's clang-format so future updates don't get overwhelmed by
inconsequential style changes.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move get_loglevel_from_vpd from mb/ocp/deltalake to driver
drivers/ocp/vpd/loglevel_vpd.c.
Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71936
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch enables PCI Express Advanced Error Reporting Capability for
WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device
will automatically report (if any error) about the error nature to the
corresponding PCIe root port.
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Iab8619818e2219b41287b895513eb04b0464401e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Use common sdhci driver in coreboot to initialize eMMC for sc7280.
This should allow us to initialize eMMC earlier in the boot process,
taking it out of the critical path.
BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot chromeos-bootimage
Change-Id: Ifa88da500e82b44d7523f2e68763e01399c89f4d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71829
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Porting from depthcharge changes for supporting eMMC driver
functionality with standard SDHC controller on Qualcomm chipsets.
sdhci_msm_init() needs to be run before the standard
sdhci_mem_controller initiailzation.
BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I6f4fd1360af1082b335f9cc3046871ce9963b5d0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72634
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding a attach callback function pointer in case a platform needs
to execute anything before the standard initialization of the sdhci
mem controller.
BUG=b:254092907
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I0f37ec09d083922cad5ecd3c47b184cf3311fe2d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Port over the remaining AMD SoCs to use CPUID_FROM_FMS. The Glinda CPUID
still needs to be updated to the actual CPUID, but for now just change
it to use CPUID_FROM_FMS.
TEST=Resulting image of timeless build for Gardenia (Stoneyridge),
Majolica (Cezanne), Chausie (Mendocino), Mayan (Phoenix) and Birman
(Glinda) don't change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia508f857d06f3c15e3ac9f813302471348ce3d89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72862
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement a get_soc_type function to determine if the silicon the code
is running on is Phoenix or Phoenix 2. This will for example be needed
to provide the correct DXIO descriptor table for the SoC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f2b668b83432426b04e7f1354b694ddd6c300d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72861
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that there is a cpuid_match function, we can use it instead of doing
basically the same thing manually. In the functions is_fam17_1x and
is_fam17_2x both the stepping number and the lower nibble of the model
number are masked out. To avoid having magic constants in the code,
introduce the CPUID_ALL_STEPPINGS_AND_BASE_MODELS_MASK definition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I758f9564c08c62c747cc4f93a8d6b540a1834a62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72860
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the functionality of cpuid_match is also useful outside of
arch/x86/cpu.c and it's a relatively simple function, move its
definition as inline function to the header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic96746b33b01781543f60cf91904af35418e572d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72859
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To provide power to MIPI panel BOE_TV110C9M_LL0, add support for
regulator VM18.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: Ib8c3b2df1157b23b37492b1e9b1716903ea67799
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72747
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There might be inconsistence between regulator_id[] and
`enum mtk_regulator` when we need to add new regulator IDs for Geralt.
Therefore, we implement get_mt6366_regulator_id() to get regulator IDs.
BUG=None
TEST=build pass.
Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
