This patch drops NEM support from MTL and enables eNEM support.
BUG=b:217130861
TEST=Able to build and boot Google/Rex in eNEM mode.
Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch combines all required configs under one umbrella config
named `METEORLAKE_CAR_ENHANCED_NEM`.
MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not
selected.
BUG=b:217130861
TEST=Able to build and boot Google/Rex.
Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch moves all required TCSS related configs under one umbrella
config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will
help in future to deselect the TCSS support for MTL SoC SKUs.
TEST=Able to build and boot Google/Rex.
Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
This patch is backported from
commit fad1cb062e (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).
Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP
doesn't like to allow an option for boot firmware to perform CPU feature
programming being independent of FSP.
Change-Id: I6447937838ab91551d172936cbb4201ea86a614b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.
Also, drop 1ms delay after setting the BIOS reset CPL.
This patch is backported from
commit 3f980ca7be (soc/intel/alderlake:
Drop enable_bios_reset_cpl() function).
Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Drops the `FIXME` comment and relevant code as this patch enables
VMX and VTD.
This patch also fixes the problem of additional reboot on every warm
boot due to overriding the CPU soft-strap.
TEST=No extra reboot seen while issuing warm reset from kernel
console.
without this patch:
950:calling FspMemoryInit 1,225,259 (20,537)
951:returning from FspMemoryInit 10,334,707 (9, 109,447)
with this patch:
950:calling FspMemoryInit 1,225,259 (20,537)
951:returning from FspMemoryInit 1,334,707 (109,447)
Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable GPP clk req disabling on morgana after reviewing against morgana
ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update pci int defs per preview of next ppr after rev 1.52, #57396
Update birman and mayan mainboards to remove deleted PIRQs.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch skips sending CONN IPC command to PMC if system is resuming
from S3.
Sending CONN IPC command as part of `tcss_configure_dp_mode()` function
results into ERROR while system is resuming from S3.
Additionally, skip `configure_aux_bias_pads()` during S3 resume.
BUG=b:260984500
TEST=Able to test on Google/Rex.
Without this patch:
[ERROR] pmc_send_ipc_cmd status: fatal
[ERROR] Port 1 connect request failed
[SPEW ] [TCSS] TcssInit() - End
With this patch:
No error seen during S3 resume.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The API socinfo_pro_part() returns 1 for Pro and 0 for NON_PRO SKUs. To
reduce the binary footprint for chipinfo structure, change its members
range from uint32_t to uint16_t. Add helper functions for reading and
matching jtagid. Modified socinfo_modem_supported() API to utilize
helper functions.
BUG=b:248187555
TEST=Validate boards are detected correctly on PRO and NON_PRO SKUs
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Id9f23696384a6c1a89000292eafebd8a16c273ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68384
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the HIDs that Windows uses for the DPTF driver.
Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5db2587ff74432a0ce1805d8d7ae76d650693eea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb:
device pci 16.0 alias heci1 on end
device pci 14.2 alias shared_sram off end
This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel
TEST=Built and tested on brya to confirm errors are not seen.
BUG=b:260258765
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are eDP and MIPI panels supported in geralt. We put the panels'
specified functions - `power_on()` and `configure_panel_backlight()` in
panel_geralt.c. Also provide the common interface `get_active_panel()`
in panel.c to generalize the display initialization. Since each board
may support a different set of MIPI panels, we put the MIPI data in a
separate file panel_geralt.c.
BUG=b:244208960
TEST=emerge-geralt coreboot
Change-Id: Ie928759e020a916f29f0364201a3cf202dc512c3
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Morgana does not have emmc, so do not select it.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ib75618c137e825befc7384275f1a4ef9b5137b09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70477
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch enables CPPCv3 support for Intel Meteor Lake which is based
on hybrid core architecture.
TEST=Build code for Rex.
Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes include:
- Add config for Meteor Lake SoC to select FirmwareVersionInfo.h
using 'DISPLAY_FSP_VERSION_INFO_2'
BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
BUG=b:259716145
TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains
the value from the devicetree on google/redrix.
Before:
Scope (\_SB.PCI0.WFA3)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
After:
Scope (\_SB.PCI0.CNVW)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions
Swap the position of two lines so that defaults are listed in
alphabetical order according to the PCH type: M, N, P, S.
Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this. Also make sure that the address of the lcl_usb_phy
struct is located below the 4GB boundary, so that the truncation to 32
bits won't result in pointing to a different memory location than
intended. In this error case, which I don't expect to happen, print an
error and write 0 to mcfg->usb_phy_ptr so that the FSP will use its
default values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1394aa6ef5f401e0c7bdd4861f1e28ae46e56e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70505
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves TCSS firmware latency related macros from SoC
specific tcss.h to IA common tcss.h
Additionally, ensure other structure definitions belonging to the
IA common code tcss.h are not causing compilation issues for ASL files
(due to including FW latency macros) hence, guarded against
`!defined(__ACPI__)`.
TEST=Able to build and boot Google/Rex and Google/Kano.
Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.
TEST=Able to build and boot Google/Volteer.
Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.
TEST=Able to build and boot Google/Kano.
Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `soc_read_pmc_base()` function returns an `uintptr_t`, which
is then casted to a pointer type for use with `read32()` and/or
`write32()`. But since commit b324df6a54 ("arch/x86:
Provide readXp/writeXp helpers in arch/mmio.h"), the
`read32p()` and `write32p()` functions live in `arch/mmio.h`.
These functions use the `uintptr_t type for the address parameter
instead of a pointer type, and using them with the
`soc_read_pmc_base()` function allows dropping the casts to pointer.
BUG=none
TEST=Build and Boot verified on google/rex
Port of 'commit f585c6eeea ("soc/intel: Drop casts
around `soc_read_pmc_base()`")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.
BUG=none
TEST=Build and Boot verified on google/rex
Port of 'commit bc35bed18e ("soc/intel/*: Allow configuring
8254 timer via CMOS")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes the `unknown` voltage field issue in processor SMBIOS
table.
This patch is backported from
commit 30e8fc1f4e (soc/intel/alderlake:
Fix unknown voltage in SMBIOS)
TEST=Able to see meaningful voltage data in the SMBIOS table.
Without this patch:
localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
...
Voltage: Unknown
With this patch:
localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
...
Voltage: 0.8 V
Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...
This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag
This patch is backported from
commit 096ce1444e (soc/intel/alderlake:
Support PCIe hardware compliance test mode)
Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip PCIe CLKSRC programming without a clock structure.
In addition, a root port can not use a free running clock or clock set
to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
This patch is backported from
commit edf71a08b4 (soc/intel/alderlake:
Skip PCIe source clock assignment if incorrect)
Change-Id: Ie9179880a57796d8595874325203280590d7ee9d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message.
This patch is backported from
commit ff553ba8b3 (soc/intel/alderlake:
Check clkreq overlap)
Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
selfboot.c blocks the payload that does not target RAM. But MT8173 loads
and runs BL31 payload in SRAM. Make the exception by implementing
`payload_arch_usable_ram_quirk()`.
TEST=load and initialize BL31 successfully
Change-Id: I8951b1c4673cdae7d1ad0c11d7d6c12376acd328
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70344
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable LPC SPI DMA. This helps with ~20ms boot time improvement while
loading various components synchronously.
BUG=None
TEST=Build Skyrim BIOS image and boot to OS. Observe a boot time
improvement of ~20 ms.
Before:
Total Time: 1,503,032
After:
Total Time: 1,485,536
Change-Id: I4dd57d46ae9bd664d57178d34b5beda872ed2cdb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70383
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The original version of the mem_chip_info structure does not record rank
information and does not allow precise modeling of certain DDR
configurations, so it falls short on its purpose to compile all
available memory information. This patch updates the format to a new
layout that remedies these issues. Since the structure was introduced so
recently that no firmware using it has been finalized and shipped yet,
we should be able to get away with this without accounting for backwards
compatibility.
BRANCH=corsola
Cq-Depend: chromium:3980175
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If34e6857439b6f6ab225344e5b4dd0ff11d8d42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68871
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81f3a38344f91cecb4fe5431ed211834e5ed599c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69897
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The size of a pointer changes between a 32 and 64 bit coreboot build. In
order to be able to use a 32 bit FSP in a 64 bit coreboot build, change
the pointer in the UPDs to a uint32_t to always have a 32 bit field in
the UPD for this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I419fef73d2881e323487bc7fe641b2ac4041cb17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
DTTS indicated Dynamic Thermal Table Switching.The proposal would like
to develop the schematic for switching 6 thermal table by lid status,
machine body mode and temperature. After entering the OS, the thermal
table would be table A. If the “Motion” or “Lid status change” is
detected. The thermal table would switch to laptop mode or lid close
mode.
Once the higher environment temperatures are detected,the thermal
table would switch to the corresponding power throttle table (B, D or
F). Based on these table switching mechanisms, no matter how the
end-user uses Chromebook,they could enjoy more humanized thermal
designs.
Release Over Over Release .
Temp. Temp. Temp. Temp. .
-------------------------------------------------------- .
Desktop mode Table A Table B 50C 45C .
Lid open (Default) .
-------------------------------------------------------- .
Desktop mode Table C Table D 55C 50C .
Lid close .
-------------------------------------------------------- .
Laptop mode Table E Table F 45C 40C .
-------------------------------------------------------- .
On the proposal, the transmission rules are list below:
1. Table A is the default table after booting.
2. A, C, E (Release Temp) can switch to each other.
3. B, D, F (Over Temp) can switch to each other.
4. A and B, C and D, E and F can switch to each other.
5. If Lid open/close or mode switch event trigger, temperature release
tables will translation to each other, temperature over tables will
translation to each other.After that event trigger, EC will check the
new temperature condition and decide if the temperature need to be
trigger.For example, if table A will switch to table D, table A will
switch to C with Lid close event, if temperature is over 55C, EC will
trigger temperature to switch form table C to D.
6. EC will trigger 3 times body-detection events during power on boot
without any body-mode and lid status change. For this case if the
previous table label is on same group, we will based on the temperature
to decide the table.
For example, assume table A is current table. When the temperature
reaches 50C, than the table is switched from A to B. The current table
is B. When the temperature is downgrade below 45C, the table is
switched form B to A. The same rule is for C and D, E and F.
BRANCH=none
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I866e5e497e2936984e713029b5f0b6d54cbc9622
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Include <amdblocks/gpio_defs.h> instead of "gpio_defs.h", since
gpio_defs.h is not only visible in a local scope, but also as
<amdblocks/gpio_defs.h>.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab3e5bb235a5b1bc995b6cf8710f0d8c1886142d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70432
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This avoids the need to hardcode the IOAPIC ID.
Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There are four requirements for the SMI to hit a printk()
this commit now removes.
Build must have DEBUG_SMI=y, otherwise any printk() is a no-op
inside SMM.
ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value.
Platform needs to have IO Trap #3 enabled at IO 0x800.
The SMI monitor must call io_trap_handler for IO Trap #3.
At the moment, only getac/p470 would meet the above criteria
with TRAP(0x32) in its DSDT _INI method. The ASL ignores any
return value of TRAP() calls made.
A mainboard IO trap handler should have precedence over
a southbridge IO trap handler. At the moment we seem to have
no cases of the latter to support, so remove the latter.
Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
At the moment IO trap is not implemented for AMD platforms.
Change-Id: Ib62ac4e4e418a8bab80c30dfb5183ecd8beb998d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is more robust than hardcoding whathever FSP has set up and is a
lot less code.
Change-Id: I6423ddc139d742879d791b054ea082768749c0a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.
Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.
This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.
TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.
Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Do not hide UARTs in ACPI mode from the OS, as this prevents using them
on at least Windows. Currently, the driver is only used on the Prodrive
Hermes mainboard.
Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.
Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixing documentation of PAD_INT macro and replacing spaces with a tab to
match the rest of the documentation.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.
BUG=b:244208960
TEST=build pass
BRANCH=corsola
Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.
BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.
Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will avoid clearing the other bits in fifo_status.
Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)
BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.
BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time
Without this patch:
942:before sending EOP to ME 1,795,702 (354)
943:after sending EOP to ME 1,950,526 (154,824)
With this patch:
942:before sending EOP to ME 2,051,406 (35,484)
943:after sending EOP to ME 2,057,583 (6,177)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.
1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.
During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).
Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.
The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.
Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.
The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'
`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.
BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The patch logs CSE RO's write protection information for Meteor Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
Port of commit abe0d810f0 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").
BUG=none
TEST=Verify the write protection details on google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This reverts commit 095c931cf1.
Previously cpu_info() was implemented with a struct on top of an
aligned stack. As FSP changed the stack value cpu_info() could not be
used in FSP context (which PPI is). Now cpu_info() uses GDT segments,
which FSP does not touch so it can be used.
This also exports cpu_infos from cpu.c as it's a convenient way to get
the struct device * for a certain index.
TESTED on aldrvp: FSP-S works and is able to run code on APs.
Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coreboot CPU index for a lapic is arbitrary: it depends on which
CPU obtains a spinlock first. Simply using an increasing index will
result in consistent ACPI tables across each boot.
Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.
BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.
SSDT snippet:
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
One
}
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package (0x01)
{
Package (0x02)
{
"ExternalFacingPort",
One
}
}
})
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The message only makes sense if ACPI PM base address is
allowed to be dynamic. If requested, it can be logged
in common code.
Change-Id: Iad7a60098c0391cc23384035af49e373dad90233
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.
In src/soc/intel/denverton_ns:
#define TCO2_STS_SECOND_TO 0x02
In soc/intel/baytrail,braswell:
#define SECOND_TO_STS (1 << 17)
Elsewehere
#define SECOND_TO_STS (1 << 1)
It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.
Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch drops the local implementation
`log_me_ro_write_protection_info` and adopts the API from IA common
code (cse_lite.c).
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
These boards do no fill MADT with useful information.
Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Set of boards and platforms did not have LINT1 configured
as NMI source.
Change-Id: I65044125562bda363b3a0d92da6137c77a28b587
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.
Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI
FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182
Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the
other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:260183610
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the MDIO access for the TSN GbE device by placing
the MDIO read and write functions into mdio_bus_operations struct which
is assigned to the .ops_mdio member of the PCI device struct. In this
way the MDIO interface of the TSN GbE device is exposed and can be used
by other drivers if needed.
Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch skips setting D0I3 bit for all HECI devices by FSP.
The learning being made from Alder Lake platform showed that the CSE
EOP cmd response time is highly nondeterministic and letting the EOP
cmd issued by FSP makes the response time even worse.
The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
(late sending of EOP) to ensure there is ample time for CSE to come
to a state where the response to the EOP is almost immediate.
There were a number of refactoring being done to ensure the EOP cmd
can be sent at the later stage.
#1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change)
#2: Modify the CSE related boot state based operation to allow a
proper window for sending late EOP cmd. (Common Code Specific change)
The entire refactoring helps us to save ~60ms of boot time.
Without those code change EOP sending timestamp as below:
943:after sending EOP to ME 1,248,328(61,954))
With those code change EOP sending timestamp as below:
943:after sending EOP to ME 1,231,660 (2,754)
Port of commit d6da4ef69e ("soc/intel/alderlake: Skip setting D0I3
bit for HECI devices") to incorporate the #1 which is a SoC specific
code change.
BUG=none
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.
Excerpt from google/rex coreboot log:
[SPEW ] DisableD0I3SettingForHeci : 0x1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update the fields that need to be updated directly in the local static
usb_phy_config struct instead of dereferencing the pointer written to
the corresponding UPD field. This will allow updating the type of UPD
field in a follow-up commit to enable 64 bit coreboot builds.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This ports forward part of commit df09680626 ("soc/amd/picasso: Add
support for 64bit builds") to the newer AMD SoCs.
Use -Wl instead of -l to get the output format that the commands in the
Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this
change, readelf will split the output into two lines in case of a 64 bit
coreboot build. This results in invalid amdcompress and amdfwtool
command lines which will cause the amdfwtool call to fail with
Error: BIOS binary destination and uncompressed size are required
With the old readelf -l command we get this output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000
0x0000000000010000 0x0000000000010000 RWE 0x10
while we get the correct output in a 32 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20
With readelf -Wl we also get the expected output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10
TEST=This fixes the 64 bit build on Cezanne with some follow-up patches
applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Skip eDP initialization when we failed to get EDID. This prevents the
PLL assertion in dp_intf_config() if the display could not be
initialized properly.
BUG=b:233720142
TEST=boot to depthcharge on MT8188 EVB.
Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.
Port the Alder Lake 'commit 6526e78967 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake.
Additionally, no performance degradation is observed while running
benchmarks.
BUG=b:211770003
TEST=Able to boot Google, Rex to ChromeOS with all cores enabled.
Without this patch:
30:device enumeration 1,480,217 (28,232)
With this patch:
30:device enumeration 1,472,466 (18,334)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.
BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.
Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.
BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.
Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").
NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.
BUG=none
TEST=Boot to OS on google/rex.
Excerpt from google/rex coreboot log:
[SPEW ] EnableTcoTimer = 1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Issue:
Device can't wake up using power key.
Root cause and solution:
EINT event mask register is used to mask EINT wakeup sources. All
wakeup sources are masked by default. So we add a driver here to unmask
all wakeup sources.
BUG=none
TEST=wake the device up by power key on MT8188 EVB.
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On Herobrine, we will determine if we have an NVMe device based on SKU
id. Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.
BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
on villager, which does not have NVMe and made sure that it boots
still. Check cbmem dump to make sure that device configuration
entry is still low since it's not initializing PCIe devices:
40:device configuration 730,203 (1,295)
Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.
BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.
This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.
This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by
accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB.
Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.
Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
