Commit Graph

390 Commits

Author SHA1 Message Date
Patrick Georgi 819c7d4a35 Whitespace fixes
Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/834
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
2012-03-31 18:06:09 +02:00
Kyösti Mälkki a860c683bc Intel cpus: get MAXPHYADDR at runtime for new CAR
Use CPUID to get MAXPHYADDR and set MTRR masks correctly.
Also only BSP CPU clears MTRRs and initializes its Local APIC.

Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/686
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 12:03:44 +02:00
Kyösti Mälkki 0078ceb553 Intel cpus: add hyper-threading CPU support to new CAR
This improvement of CAR code starts the sibling CPU processors and
clears their cache disable bits (CR0.CD) in case a hyper-threading
CPU is detected.

Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/604
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31 12:02:16 +02:00
Kyösti Mälkki 05d6ffba0f Intel cpus: improve CPU compatibility of new CAR
Most or many Xeons have no MSR 0x11e.

I have previously tested that a HT-enabled P4 (model f25) can
execute this but will not have cache-as-ram enabled. Should work
for non-HT P4.

Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/644
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31 11:58:51 +02:00
Kyösti Mälkki f9d1a42d98 Intel cpus: apply some good programming practices in new CAR
Delete dead CAR code and whitespace fixes.

Replace cryptic 32bit hex values with existing LAPIC definitions.

Do not assume state of direction flag before "rep" instruction.

Do not load immediate values on temporary registers when not needed.

Parameter pushed on stack was not popped (or flushed) after returning
from call. This is a sort-of memory leak if multiple call's are
implemented the same way.

Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/643
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-03-31 11:55:54 +02:00
Kyösti Mälkki 325b92f64a Intel cpus: cache actual size of the Flash ROM device
Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.

Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.

Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 11:54:37 +02:00
Kyösti Mälkki 5a660ca229 Intel cpus: copy model_6ex CAR code
Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended
with hyper-threading CPU support.

Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/606
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-31 11:50:57 +02:00
Kyösti Mälkki 8b28d50cdd Intel cpus: Fix deadlock on hyper-threading init
Only the BSP CPU was able to start its hyper-threading CPU siblings.
When an AP CPU attempts this it calls start_cpu() within start_cpu(),
deadlocking the system with start_cpu_lock.

At the time intel_sibling_init() is run, the BSP CPU is still
walking the cpu_bus linked list in lapic_cpu_init: start_other_cpus().
A sibling CPU appended at the end of this list will get started.

Also fail compile with #error if SERIAL_CPU_INIT==0, as microcode
updates on hyper-threading sibling CPUs must be serialized.

Tested with HT-enabled P4 Xeons on dual-socket604 platform.

Change-Id: I0053f58f49ed604605ce0a55e826d3e1afdc90b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/775
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2012-03-25 20:33:28 +02:00
Kyösti Mälkki 7a39446ec2 Intel cpus: Include CAR from socket
It was not obvious which CAR was compiled in. Also build would fail
if a socket included two models with both having an include for CAR.

Change-Id: I000c2e24807c3d99347a43d120333c13fbf91af4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/626
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-17 09:38:31 +01:00
Kyösti Mälkki 53c1d204ed Intel cpus: use CPU_PHYSMASK_HI define in CAR
Unifies models 6ex, 6fx and 106cx.

Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-16 01:55:50 +01:00
Kyösti Mälkki adf105fe45 Intel model_106cx: Use symbolic names for MTRR bits
Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/637
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-15 18:04:33 +01:00
Kyösti Mälkki e13632a939 Intel cpus: apply un-written naming rules
Kconfig directives to select chip drivers for compile literally
match the chip directory names capitalized and underscored.

Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x.

Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/618
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-10 23:40:07 +01:00
Sven Schnelle 6d64adeaa6 Add Intel Socket LGA771
Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/492
Tested-by: build bot (Jenkins)
2012-02-09 21:12:34 +01:00
Sven Schnelle adfbcb79ab MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.

Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-10 21:51:40 +01:00
Sven Schnelle 8d846135ff ACPI: mark empty get_cst_entries() weak
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.

Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)
2012-01-09 11:07:18 +01:00
Patrick Georgi 784544b934 Remove XIP_ROM_BASE
The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-11-01 19:06:23 +01:00
Rudolf Marek 9438da370f Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9
It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.

This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.

Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2011-10-30 21:28:11 +01:00
Patrick Georgi 914377efd6 Get rid of the old romstage-as-bootblock ROM layout
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.

This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.

Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:17:36 +02:00
Patrick Georgi 1da104647d Get rid of AUTO_XIP_ROM_BASE
That value is now generated from a code address and CONFIG_XIP_ROM_SIZE.
This works as MTRRs are fully specified by their size and any address
within the range.

Change-Id: Id35d34eaf3be37f59cd2a968e3327d333ba71a34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:17:10 +02:00
Sven Schnelle 5460097041 SPEEDSTEP: write _CST tables
Change-Id: Idb4b57044808918de343d31519768d0986840f01
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/321
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-10-25 18:59:10 +02:00
Kyösti Mälkki 521d8c2573 Activate older Xeon P4 microcodes
As new microcode files were included, the table was not updated with
families 0f25 and 0f26.

Change-Id: I5bb8be9d7c37eb8406dcb48a4b933eab24639bda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-18 00:10:51 +02:00
Patrick Georgi ac624a638d Crank up CPU speed on Intel Core and Core2 CPUs
The CPUs start on their slowest speed, and were left that way by
coreboot. This change will speed up coreboot a bit, as well as
systems that don't change the clock for whatever reason.

Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/176
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-09 11:40:30 +02:00
Keith Hui 1ac19e28ee cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs.
Bring from coreboot v1 support for initializing L2 cache on Slot 1
Pentium II/III CPUs, code names Klamath, Deschutes and Katmai.

Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with
Pentium III 600MHz, Katmai core.

Also add missing include of model_68x in slot_1, to address a
similar problem fixed for model_6bx by r5945.

Also change Deschutes CPU init sequence to match Katmai.

Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: http://review.coreboot.org/122
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-08-04 08:10:12 +02:00
Sven Schnelle 2f81c03d3a Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-03 07:55:43 +00:00
Stefan Reinauer d4814bd41c more ifdef -> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21 20:45:45 +00:00
Stefan Reinauer 139e6f9555 Use symbolic names for some MTRR bits instead of numbers in CAR code
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6493 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-14 20:06:30 +00:00
Alexandru Gagniuc 5005bb06c1 Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 20:17:22 +00:00
Stefan Reinauer ce952652a1 oops. this is weird. CAR addresses should be specified in the socket and not in
the board. I thought we did this ages ago.

Also push CAR BASE further down so it won't conflict with a 32mbit flash part.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27 01:11:20 +00:00
Stefan Reinauer 7b0500c24c Revert r5902 to make code more readable again. At least three people like to
have this go away again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>                                                                          
Acked-by: Kevin O'Connor <kevin@koconnor.net>                                                                          



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 06:54:42 +00:00
Stefan Reinauer fb433bea6a drop unused files
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-12 21:09:25 +00:00
Stefan Reinauer dfeb04d463 fix model 106cx
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-12 00:37:41 +00:00
Stefan Reinauer 2a27b20226 factor out cpu power management base into a separate file. And fix a bug in
model_1067x

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 22:14:44 +00:00
Tobias Diedrich abebf5ca92 These empty files sneaked in from another patch and shouldn't have been included in r6153, remove them.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 21:45:57 +00:00
Tobias Diedrich b672d94ce0 Tobias Diedrich wrote:
> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.

Here is a solution using the SSDT.

Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.

Abuild-tested.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 21:40:12 +00:00
Uwe Hermann d351925446 Move "select CACHE_AS_RAM" lines from boards into CPU socket.
All K8/Fam10h boards use CAR, so move the "select CACHE_AS_RAM"
into the socket directories, and remove it from the individual boards.

Do the same for Intel CPUs/sockets where all boards use CAR.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 08:22:04 +00:00
Patrick Georgi 361bd10bce Move Intel power management related defines to some central location.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 21:52:15 +00:00
Stefan Reinauer c104cb0d9d update intel microcode files.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:21:39 +00:00
Uwe Hermann 321ebe0953 Make update-microcodes.sh executable.
This also has an additional benefit:

I was running "sh update-microcodes.sh" previously which broke with

  update-microcodes.sh: 102: Bad substitution

due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific
stuff). Running "bash update-microcodes.sh" works fine.

Making the script executable in svn reduces the likelyhood of people
running the script with differing shells that may not work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-18 00:20:40 +00:00
Stefan Reinauer a600a3f700 update intel microcode update script
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 23:55:17 +00:00
Keith Hui a14b117269 Removes model_65x CPUIDs from model_6xx code.
They now have their own home at cpu/intel/model_65x.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-17 22:07:08 +00:00
Keith Hui b14fb6abd6 Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.
abuild-tested. I have no Deschutes CPUs to boot test this with.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-16 08:45:31 +00:00
Uwe Hermann af8b2b91b4 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-15 07:47:51 +00:00
Keith Hui 6529c2a717 Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.
abuild-tested. Boot tested on P2B-LS.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 17:00:42 +00:00
Uwe Hermann ab50d62ea6 Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.

 - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
   usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.

 - In socket_PGA370/Makefile.inc add:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Other smaller related fixes.

Abuild-tested and boot-tested on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 08:21:44 +00:00
Keith Hui 5e9c1cd693 Add missing include of model_6bx for slot_1.
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
"unknown CPU". I believe it will happen with any Slot 1 440BX boards
that supports model_6bx CPUs.

I need to make the change below to make it work. abuild tested. Boot
tested on P2B-LS and P3B-F.

Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 23:22:08 +00:00
Warren Turkal 4ffde94c4e Reduce duplicate definition in CAR code.
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.

I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-12 06:13:40 +00:00
Uwe Hermann 554c052b48 Remove some duplicate #include files (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 23:42:17 +00:00
Uwe Hermann 6f2d20ec49 Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.

 - Add the following in src/cpu/intel/slot_1/Makefile.inc:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Remove "select ROMCC" from all 440BX board Kconfig files.

 - Drop all early_mtrr_init() calls, that's done by CAR code now.

Various small fixes were needed to make it build:

 - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
   those were never called anyways.

 - Remove the "static" from the main() functions in romstage.c files.

 - Always call dump_spd_registers() from the 440BX debug.c, but use
   "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
   is enabled in menuconfig.

 - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
   commented out) from romstage.c's, as we've done for most other boards.

 - Add missing #includes or prototypes. Some of the prototypes will be
   removed later when we get rid of the #include'd .c files.

Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-06 19:32:39 +00:00
Uwe Hermann cc0dc7f839 Add missing Intel Pentium II/III era CPU IDs.
Add links to the respective Intel specification updates or manuals where
the IDs are listed. Mention the possible core steppings of each CPU ID.

There are duplicate IDs in model_6xx and model_68x for now, not sure if
those should be eliminated, but there were already duplicates before this
patch, so that's probably an extra issue to look into.

Abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5909 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-04 20:43:55 +00:00
Uwe Hermann 36455aade4 Add comments to make it clear why these two lines are written like that:
movl    $REAL_XIP_ROM_BASE, %eax
  orl     $MTRR_TYPE_WRBACK, %eax

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 20:51:29 +00:00
Uwe Hermann dd8367006c Factor out common CAR asm snippets.
This makes the CAR implementations a lot more readable, shorter and
easier to follow, and also reduces the amount of uselessly duplicated code.

For example there are more than 12 open-coded "enable cache" instances
spread all over the place (and 12 "disable cache" ones), multiple
"enable mtrr", "save BIST", "restore BIST", etc. etc.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5902 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 21:46:04 +00:00
Uwe Hermann 2ba2b553b5 Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial).
This is abuild-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 17:37:45 +00:00
Myles Watson c7e982bbef Fix some breakage from 5890.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5899 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 15:16:20 +00:00
Uwe Hermann 66d1687b92 CAR simplifications, typos, readability improvements (trivial).
- Use some more #defines instead of hard-coding values.

 - Merge multiple movl/orl or movl/andl lines into one where possible.

 - Add some TODOs in places which seem to have either an incorrect
   code or incorrect comment.

 - Fix typos: s/for/from/, s/BSC/BSP/, s/size/carsize/.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5890 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 07:27:51 +00:00
Uwe Hermann 4292684e1a Various cosmetic and coding style fixes in CAR code (trivial).
Also, whitespace fixes, consistency fixes, and drop some of the less
useful comments.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 23:15:36 +00:00
Uwe Hermann 1d36d6df7d Use existing, readable MTRR #defines instead of hardcoding numbers.
Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 21:22:40 +00:00
Patrick Georgi 8463dd9db0 Rename build system variables to be more intuitive, and
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs

The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y

Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.

Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 16:55:02 +00:00
Uwe Hermann aac8f661f5 Factor out fill_processor_name() and strcpy() functions.
The fill_processor_name() function was duplicated in multiple
model_*_init.c files, move it into a new src/cpu/x86/name
directory.

The strcpy() function was also duplicated multiple times, move it
to <string.h> where we already have similar functions.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-29 09:54:16 +00:00
Warren Turkal 7571c0b566 This patch moves one of the CAR configs to the socket from the single
mainboard that uses it.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:11:54 +00:00
Stefan Reinauer da28cd8542 drop double include (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 11:11:09 +00:00
Warren Turkal d6924e820f Normalize the config option for the Intel Atom CPU.
All Intel CPU models appear to be identified with the form
INTEL_CPU_MODEL_xxxxx. I haved changed the Atom to fit this normal form.

A side effect is that the CPU doesn't need to be listed on the boards
that support it since the socket identifies the CPUs it supports.

Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5853 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-26 15:18:21 +00:00
Uwe Hermann b124dcf935 Drop <cpu/amd/mtrr.h> #include from Intel CPUs.
Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
is obviously wrong, so drop the #includes. None of their #defines are used
in the Intel code.

Build-tested with two of the affected boards.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25 12:37:33 +00:00
Stefan Reinauer 704b59662d We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 17:53:13 +00:00
Andreas Schultz 1bab1fb839 mPGA479M Sockets can take Intel Mobile Celeron.
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.

Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

This patch likely breaks the following two boards since it unconditionally
activates CAR code for this socket:

 * digitallogic/adl855pc
 * intel/mtarvon

stepan suggests moving those two boards over to CAR, too, so we don't have to
worry.

---
 src/cpu/intel/socket_mPGA479M/Kconfig      |    1 +
 src/cpu/intel/socket_mPGA479M/Makefile.inc |    2 ++
 2 files changed, 3 insertions(+), 0 deletions(-)




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 16:16:01 +00:00
Stefan Reinauer 3058491257 My forgotten CAR cleanup patch...
- Drop lots of dead code from the various cache_as_ram.inc files.
- Use some descriptive macros instead of magic numbers for MTRR MSRs
- drop unused duplicate descriptors from romstage GDT
- slightly reformatting code and comments

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-14 20:38:17 +00:00
Stefan Reinauer 8c4f31b3b5 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision to make for any user /
board porter: printk should always be available in CAR mode.

Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
but it's not been used there. Very odd.

There is one usage of CONFIG_USE_INIT which was always off in 
src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
those few lines.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-03 15:42:29 +00:00
Joseph Smith b94a79fa6a This patch adds support for the Intel D810E2CB (i810e/ICH2) desktop board. Hurray, this is the first i810 board running CAR.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-21 23:25:06 +00:00
Joseph Smith 40bffc22cd Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x).
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-21 19:40:09 +00:00
Stefan Reinauer 32e6e411ea Add Intel Atom microcode
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-28 16:21:21 +00:00
Stefan Reinauer 89ef0a9f41 Update Intel microcode include files from their web page.
This still requires someone to adjust the #includes in the
model_XXX_init.c files but with a script we're getting closer
to automate the update of 3rd party files.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-26 17:08:13 +00:00
Stefan Reinauer f71fca0a7f Use the microcode files as created by the new microcode update script. (Fixes some whitespace and gets in new time stamps).
No new microcode files included.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-26 16:54:33 +00:00
Stefan Reinauer a998eae425 Drop problematically licensed Intel microcode files
and replace them by their counterparts from Intel's
opensource microcode file.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-26 12:55:14 +00:00
Stefan Reinauer c8f8a6cb91 cosmetical changes on intel's microcode.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-26 12:53:43 +00:00
Stefan Reinauer 7e00a44b77 also rename the config option.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-25 17:09:05 +00:00
Stefan Reinauer da3237376f Long ago we agreed on kicking the _direct appendix because everything in
coreboot is direct. This patch does it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-25 16:17:45 +00:00
Nils Jacobs dd6ad3447b license header fixes
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5545 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-05-14 09:48:05 +00:00
Stefan Reinauer 14e2277962 Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-27 06:56:47 +00:00
Myles Watson b333718e90 I meant SSE. Reported by Dustin Harrison.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5505 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 13:33:23 +00:00
Myles Watson 03a5d802ff Enable SSE2 for ep80579. Reported by Dustin Harrison.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5504 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-26 13:27:35 +00:00
Stefan Reinauer e08c29e0e7 a single place for the romstage stack for copy_and_run.
geode lx and amd opteron don't use this yet.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-25 21:43:29 +00:00
Stefan Reinauer 4186d8e6ea these cpus are explicitly supported by model_6bx
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5489 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-24 23:16:23 +00:00
Stefan Reinauer ccdd20a539 move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list.
this patch also slightly changes it so we have a single cache_as_ram.inc which
requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
worse, a lot of cruft hacked right into romstage.c like on tyan s2735)

Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-14 07:47:07 +00:00
Stefan Reinauer 1f10de6cab fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to
mention it explicitly. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-13 13:48:20 +00:00
Stefan Reinauer 170679b9dd update atom car code in the same way that 6ex/6fx was updated.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-13 00:11:59 +00:00
Stefan Reinauer 1977b891c5 port latest model 6ex car changes to 6fx car, which is almost identical and
currently unused. Just keep it in sync, we might need it some day.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-12 23:12:15 +00:00
Stefan Reinauer 3e1f524566 move model_6ex car to a single file. No more .c files that only consist of a
single several pages long asm statement

Could use some renumbering of post codes, but that's good for another time.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-12 23:04:29 +00:00
Patrick Georgi 5934b507d5 Move the CPU specific includes from
src/arch/i386/Makefile.inc to the respective CPU directories.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-12 15:28:34 +00:00
Stefan Reinauer accb50a4e3 The ADL855PC was never confirmed working (in fact it's pretty sure that code
does not work as it is, but it's the only compile test case for i855pm). It's
the only board left using an ICH4 that does not use CAR. Change that.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-11 19:02:10 +00:00
Joseph Smith 7488e049df 1. This patch adds CAR for Intel P6 series processors.
2. Add support for Micro-FCBGA 479 Celeron and PIII's
3. Add support for model_6bx and microcode updates
4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson
   IP1000

Build and boot tested.

Signed-off-by: Joseph Smith <joe@settoplinux.org>

The change to CAR reveiled a few more warnings in the ICH4 and i830 code,
I fixed them on the fly. 

Checking this in because my last two commits broke Joseph's CAR patch. This
version fixes the issues.

Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09 11:10:25 +00:00
Stefan Reinauer 853263b963 copy_and_run.c is not needed twice, and it is used on non-car too.
So move it to src/arch/i386/lib/cbfs_and_run.c

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-09 10:43:49 +00:00
Stefan Reinauer 0c781b2694 - get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files.
- start naming all versions of post code output "post_code()"

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-04-01 09:50:32 +00:00
Stefan Reinauer 64ed2b7345 Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C
completely?

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-31 14:47:43 +00:00
Stefan Reinauer 8013d5a568 cpu_driver structs need to be const, too...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5314 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-29 19:04:13 +00:00
Stefan Reinauer 53b0ea4bf2 drop some unused files and fix warnings on i945 based systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5267 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22 11:50:52 +00:00
Stefan Reinauer c02b4fc9db printk_foo -> printk(BIOS_FOO, ...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-22 11:42:32 +00:00
Patrick Georgi 78acf93291 Remove remaining uses of
HAVE_FAILOVER_BOOT
HAVE_FALLBACK_BOOT
USE_FAILOVER_IMAGE
USE_FALLBACK_IMAGE

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5259 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18 20:58:41 +00:00
Patrick Georgi 776b85ba45 Remove fallback/normal handling in mainboards'
romstage.c like r5255 did for failover/fallback/normal
mainboards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-18 16:18:58 +00:00
Stefan Reinauer bd112980ff more warning fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5242 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17 03:14:54 +00:00
Stefan Reinauer d4ab7c5efb fix dell s1850, ROMCC didn't seem to like SSE2 memtest here.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17 02:09:12 +00:00
Myles Watson d9659013f9 Source all Kconfig files for Intel® CPU models..
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-17 00:55:39 +00:00
Keith Hui f7b3c5e852 Add support for the 0x06B1 CPU ID for Celeron (Tualatin).
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5193 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-06 16:19:11 +00:00
Keith Hui e1ec158c0a Add proper Slot 1 CPU support code/infrastructure.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-05 16:18:38 +00:00
Stefan Reinauer a7acc515bd HAVE_MOVNTI really means SSE2. Also add sfence in the MOVNTI case.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-25 13:40:49 +00:00
Stefan Reinauer de3206a7be This is a general cleanup patch
- drop include/part and move files to include/
- get rid lots of warnings 
- make resource allocator happy with w83627thg
- trivial cbmem resume fix
- fix payload and log level settings in abuild
- fix kontron mptable for virtual wire mode
- drop some dead includes and dead code. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 06:09:43 +00:00
Uwe Hermann c70e9fc233 Various license header consistency fixes (trivial).
- Consistently use the same wording and formatting for all license headers.

 - Remove useless whitespace, add missing whitespace, fix indentation.

 - Add missing "This file is part of the coreboot project." where needed.

 - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency.

 - Add some missing "(C)" strings and copyright years where needed.

 - Move random comments and file descriptions out of the license header.
   - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc).
 
There should be no changes in _content_ of the license headers, if you spot
such changes that's a bug, please report!

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-15 23:10:19 +00:00
Patrick Georgi abf2ad716d newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-07 21:43:48 +00:00
Stefan Reinauer f14e69bc62 typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 11:05:59 +00:00
Stefan Reinauer 04d74b1fdd Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.
This automatically adds the settings for those boards that didn't have settings
at all yet. Also, small fixup to compareboard.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>

--> Please help porting all boards from newconfig to Kconfig <--

This is a lot of janitor work and we can use your helping hands.
The sooner we can get rid of Kbuild, the better. The KBuild report
on the mailing list shows the config differences between newconfig
and Kconfig. In theory, all Kconfig configs should be equal to their
newconfig pendant. In practice it's better to come close but stay 
clean.

--> Please help porting all boards from newconfig to Kconfig <--



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-04 01:32:43 +00:00
Patrick Georgi e8d943f266 Fix ACPI build on a couple of boards (now that it's active)
Fix timer handling on amd/sc520 systems
Match UDELAY_* configuration of newconfig in Kconfig

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5054 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-25 15:17:11 +00:00
Patrick Georgi d5663bac2c Move all IOAPIC selection to southbridges, and remove them
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.

Fix intel/d945gclf build, which was missing some ACPI component.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-18 17:30:36 +00:00
Stefan Reinauer 12ee934cb3 Make internal functions static in speedstep ACPI generation code.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:49:03 +00:00
Stefan Reinauer f0ec230280 Fix stack base for Atom CPUs, the resume mechanism (cbmem etc) expects this.
This unifies the base with Core and Core 2 CPUs.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5013 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:48:20 +00:00
Stefan Reinauer ba8b21c376 Micro-optimization: movl $0 --> xorl.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5012 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:47:07 +00:00
Stefan Reinauer 68b3c4637a new microcode for Intel Core 2(tm) CPUs
(taken from Intel's Linux microcode release)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-16 13:42:43 +00:00
Patrick Georgi 1f807fd42f - Fix UDELAY options and HAVE_INIT_TIMER [kconfig]
(defaults to UDELAY_IO again, like newconfig)
- Use UDELAY_TSC on Via C7 [kconfig]
- Support Tinybootblock on Intel CPUs
- set XIP location correctly for Tinybootblock on Intel
- provide correct XIP location in Tinybootblock configuration
- Make kontron/986lcd-m use Tinybootblock
- Some kconfig fixes to kontron/986lcd-m [kconfig]

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-04 20:09:27 +00:00
Patrick Georgi ce56835a5c - use LAPIC timer if selected (instead of TSC all the time) [kconfig]
- uncomment commented out intel socket [kconfig]
- HAVE_MOVNTI is a property of the cpu [kconfig]

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4996 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-04 14:36:55 +00:00
Myles Watson 59968f5c81 Trivial fix for kconfig socket 441 (typo was 411) so that d945gclf builds.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4973 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-02 05:43:50 +00:00
Stefan Reinauer 702a5a5741 Atom only supports 32bit MTRRs (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4970 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-12-01 08:15:38 +00:00
Stefan Reinauer 5fc7f98c51 Fix up typo in Socket 441 CPUs, and add a few (trivial) Kconfig files for them.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4908 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-04 12:18:44 +00:00
Patrick Georgi c6680487b9 Some fixes.
Atom does not like 36bit MTRRs in CAR setup.
Enable XIP setup again (works with 32bit MTRRs)
Keep code more similar to 6ex code..

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-11-03 15:02:15 +00:00
Myles Watson 4ec4fbe0e9 Make d945gclf build.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4882 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 18:51:47 +00:00
Uwe Hermann 2d2f0c121f Add some missing license headers, consistency fixes for others (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4881 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 17:36:11 +00:00
Stefan Reinauer 1a08f582b5 preliminary Intel D945GCLF Atom+i945 support.
ram init fails, as the i945 driver currently only supports the mobile version
of the chipset..

Not sure how much sense it makes to check this in, but since it's a nice and
cheap board, maybe someone wants to work on this.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-28 16:52:48 +00:00
Stefan Reinauer 3b31402380 CBMEM high table memory manager.
This code adds a very simple toc based memory manager for the high tables area.
The purpose of this code is to make it simpler and more reliable to find
certain data structures in memory. This will also make it possible to have ACPI
S3 Resume working without an ugly hole at 31MB.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4860 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 17:04:28 +00:00
Stefan Reinauer a769344d43 intel core and core 2:
- small preprocessor fix
- leave some space in the CAR area for the usbdebug structure
  if usbdebug is used

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4859 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-26 16:49:16 +00:00
Stefan Reinauer 105bace68d Some ACPI implementations don't like to see full paths within a scope for
CPU power management, so don't add the scope name

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-24 18:36:51 +00:00
Myles Watson 0bc615482e Remove CONFIG_ from #defines that aren't config variables. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 13:25:07 +00:00
Peter Stuge f078be2cb1 Remove some more instances of including previous empty x86/fpu/Makefile.inc
Thanks to Jakob and Uwe for spotting the mistake!

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 02:51:26 +00:00
Peter Stuge b1924301ca Drop src/cpu/x86/fpu/{Config.lb,Makefile.inc} since they are also empty
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-17 01:12:42 +00:00
Peter Stuge 2c54f90280 Drop empty cpu/x86/{mmx,sse}/{Config.lb,Makefile.inc} and remove references
Files in those directories are still used, but always with explicit path.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-16 18:27:13 +00:00
Myles Watson b8e2027be8 Add CONFIG_GENERATE_* for tables so that the user can select which tables not
to build, but by default all the tables that are available are built.

Make PIRQ table build for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-15 13:35:47 +00:00
Myles Watson e7bbb50ba0 Remove default n statements to simplify .config and ldoptions files.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4753 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-09 17:39:35 +00:00
Ronald G. Minnich cc2b9f2abe Set MMX and SSE where needed. Note that many boards don't even bother
with this as many boards (AMD in particular) use CAR.

This list determined by a series of greps etc. on mainboards, no humans
were harmed in the making of this list.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-08 16:06:09 +00:00
Patrick Georgi 0e9a92545d Various fixes to Kconfig: All kconfig-boards should have a
complete set of variables now, though they might still have
the wrong values.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-06 20:48:07 +00:00
Peter Stuge 4c5786b1f9 Add some trivial numbers for 945, and Core2 Duo E8200 Intel parts
Sorry, but I've forgotten where I found them. :\

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-01 22:34:18 +00:00
Patrick Georgi 5e54871375 More consistent use of "default n" and "select XYZ" in
Kconfig files


Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4685 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-29 14:38:10 +00:00
Patrick Georgi 88f55b2c12 some progress on kconfig:
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
  the socket it has, and the CPUs are pulled in automatically. There is
  some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
  - intel/eagleheights
  - intel/jarrell
  - intel/mtarvon
  - intel/truxton
  - intel/xe7501devkit
  - sunw/ultra40
  - supermicro/h8dme
  - tyan/s2850
  - tyan/s2875
  - via/epia
  - via/epia-cn
  - via/epia-m
  - via/epia-m700
  - via/epia-n
  - via/pc2500e
(PPC not considered, probably overlooked something)

All of them only _build_, but some options are probably completely
wrong. To be fixed later

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-25 18:43:02 +00:00
Uwe Hermann 6dd5223b07 Use driver-y instead of obj-y for model_6xx_init.o.
Otherwise booting (but not building) fails:

  Initializing CPU #0
  CPU: vendor Intel device 665
  CPU: family 06, model 06, stepping 05
  Unknown cpu

This patch was tested to fix the issue on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-04 16:30:31 +00:00
Uwe Hermann b7fec825fe Add kconfig support for ASUS P2B-F.
Only build-tested so far, not tested on hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 12:25:36 +00:00
Uwe Hermann 5ec2c2b998 Various Kconfig and Makefile.inc fixes and cosmetics.
- Whitespace fixes, remove trailing whitespace, use TABs for identation
   (except in Kconfig "help" lines, which start with one TAB and two spaces
   as per Linux kernel style)

 - Kconfig: Standardize on 'bool' (not 'boolean').

 - s/lar/cbfs/ in one Kconfig help string.

 - Reword various Kconfig menu entries for a more usable and consistent menu.

 - Fix incorrect comment of NO_RUN in devices/Kconfig.

 - superio/serverengines/Kconfig: Incorrect config name.

 - superio/Makefile.inc: s/serverengine/serverengines/.

 - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.

 - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.

 - mainboard/via/epia-n/Kconfig: Fix "bool" menu text.

 - console/Kconfig: Don't mention defaults in the menu string, kconfig
   already displays them anyway.

 - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 00:53:22 +00:00
Ronald G. Minnich ebed2dc720 Change the intel cpu makefile.inc so that it fits the model better.
- intel/Makefile.inc only mentions sockets
- those sockets are conditionally included
- makefile.inc in socket directories are almost all unconditionally included
- Get rid of if where possible, use -$(CONFIG_VARIABLE) instead as per Kconfig 
  standards in linux kernel

See the Kconfig.tex documentation for questions.  


Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-21 18:08:49 +00:00
Patrick Georgi 0588d19abe Kconfig!
Works on Kontron, qemu, and serengeti. 

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>

tested on abuild only. 

Acked-by: Ronald G. Minnich <rminnich@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 15:00:51 +00:00
Stefan Reinauer 4da810bd53 add intel speedstep support and some PM fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-21 21:41:42 +00:00
Thomas Jourdan 1a692d8176 Add support for the Intel Eagle Heights development board.
Signed-off-by: Thomas Jourdan <thomas.jourdan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 17:01:17 +00:00
Myles Watson 6c96517a13 Fix typo and only output post code if the work was done.
Thanks to Thomas Jourdan <thomas.jourdan@gmail.com> for reporting it.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4391 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-07-01 16:34:03 +00:00
Stefan Reinauer 0867062412 This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-30 15:17:49 +00:00
Luc Verhaegen a9c5ea08d0 Revert "CMOS: Add set_option and rework get_option."
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.

Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 14:19:33 +00:00
Luc Verhaegen 9ceae905f1 CMOS: Add set_option and rework get_option.
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.

get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.

The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.

build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-06-03 10:47:19 +00:00
Stefan Reinauer 88e71e8859 Run dos2unix on all files:
find . -type f| grep -v svn | xargs dos2unix

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4250 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-05-02 12:42:30 +00:00
Stefan Reinauer c7757f20ac * Use latest version of intel microcodes from their Linux drivers page for
models 6ex and 6fx (core and core2 solo and duo). Also, use the names suggested 
  by Intel for the microcode files instead our short version of it. This allows to
  create new microcode patches with a simple set of scripts.
* some minor cpu setup fixes for c and p states

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4235 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 10:14:22 +00:00
Patrick Georgi 12aba82e55 Refactor copy_and_run so that it uses a single code base instead of
3 (with one of them way too much assembler code).

On the way, I had to make some changes to the way the code is built, 
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as 
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects 
lots of post-raminit code (memcpy doesn't really make sense before 
raminit, or at least CAR)

The coreboot_apc code (AMD boards) gained some .c includes because I 
don't know that part of the code enough to really rework it and only 
have limited possibilities to test it. The includes should give an 
identical situation for this part of the code.

This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-30 07:07:22 +00:00
Stefan Reinauer 38c49fddde argh... never redo parts of the original patch on the fly. This fixes the tree
again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 09:06:38 +00:00
Stefan Reinauer 953253f093 This patch unifies the socket_mPGA604_800Mhz and socket_mPGA604_533Mhz to a
combined socket_mPGA604. No other sockets come with clock rates, and there is
no difference in code, except for the number of microcode patches included in a
build.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:56:50 +00:00
Patrick Georgi 6af0cb6efc Trivial removal of a freudian slip.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-22 08:07:31 +00:00
Stefan Reinauer 3081bdfa44 Drop CONFIG_CHIP_NAME. Those config statements in Config.lb should
be used unconditionally, and the names don't hurt.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-04-01 13:43:21 +00:00
Stefan Reinauer 45cc550c3a Some updates for core/core duo/core2/core2 duo cpus.
The microcode is from Intel's Linux microcode file, so it's unproblematic.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3983 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-03-06 19:54:15 +00:00
Stefan Reinauer 2b34db8d1d coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-02-28 20:10:20 +00:00
Stefan Reinauer 20b261dacf Fix register typo for core 2 cpus (trivial)
This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:32:37 +00:00
Stefan Reinauer c5983305ef fix compiler warnings (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3878 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-20 21:27:23 +00:00
Stefan Reinauer 269563a423 First shot at factoring SMM code into generic parts and southbridge specific
parts.

This should help to reduce the code duplication for Rudolf's K8/VIA SMM
implementation...

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-01-19 21:20:22 +00:00
Corey Osgood e562f7258e Fix a LOT of implicit function declarations before they become errors.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-12-19 03:36:48 +00:00
Stefan Reinauer 00a889c8aa Support for Intel Core Duo and Core 2 Duo (tm) CPUs.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3702 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-10-29 04:48:44 +00:00
Ed Swierk 1996313756 This patch implements support for the CPU core of the Intel EP80579
Integrated Processor.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-25 14:41:11 +00:00
Stefan Reinauer 5a522d4a42 match against all steppings of a CPU model, because these are _model_ drivers.
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 12:11:00 +00:00
Stefan Reinauer df6c858218 drop unused code (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3452 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-08-01 11:53:39 +00:00
Uwe Hermann 049814cc8f Add missing Intel CPU (trivial).
Tested by me on actual hardware.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3422 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2008-07-15 13:22:21 +00:00
Stefan Reinauer 124e4a45ca analog changes for the cpu_driver structures...
make them const before putting them into the read-only segment...
(trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-24 11:10:21 +00:00
Stefan Reinauer 8b83836115 Add support for the Intel mFCPGA 478 socket. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2888 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-23 18:59:21 +00:00
Joseph Smith a3e03872f3 This patch adds support for the Mobile Intel Celeron CPU (Micro-FC-BGA)
Signed-off-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-10-15 21:39:48 +00:00
Corey Osgood e99bd105af This patch adds support for the Intel i82810 northbridge and various i82801xx
southbridges, along with the Asus MEW-VM. With this, my machine attempts to
boot linux, but does so very slowly and fails during the boot process, probably
because of the irq tables.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-14 06:10:57 +00:00
Jon Dufresne a522df039b Add mtrr support for pentium m cpus
For cache to work the x86_setup_mtrrs() must be called. 

Closes #61

Signed-off-by: Jon Dufresne <jon.dufresne@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2522 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-12-14 00:40:09 +00:00
Uwe Hermann a7aa29b943 Use the canonical name of the vendors/devices and the
same format for all CHIP_NAME() entries in LinuxBIOS (Closes #20).

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-11-05 18:50:49 +00:00
Richard Smith cb8eab482f add framework for i440bx chipset
add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config

This is a very basic framework for the i440bx chipset and the 
Bitworks IMS board that uses it.  Most things are 
structure only.

Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2006-07-24 04:25:47 +00:00
Steven J. Magnani 059182cc4f Print a failure message if a sibling CPU fails to start.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-09-14 13:52:06 +00:00
Yinghai Lu 13f1c2af8b eric patch
1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-07-08 02:49:49 +00:00
Eric Biederman 3f5ef301a7 Fix typo in microcode header file include
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1894 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2005-01-20 18:37:00 +00:00
Eric Biederman 69afe2822a mpspec.h: Tweak the write_smp_table macro so that it is safe if passed a complex expression.
crt0.S.lb: Modified so that it is safe to include console.inc
console.c:  Added print_debug_ and frieds which are non inline variants of the normal console functions
div64.h:   Only include limits.h if  ULONG_MAX is not defined and define ULONG_MAX on ppc
socket_754/Config.lb Conditionally set config chip.h
socket_940.c We don't need and #if CONFIG_CHIP_NAME we won't be linked in if there are no references.
slot_2/chip.h: The operations struct need to be spelled cpu_intelt_slot_2_ops
slot_2/slot2.c: The same spelling fix
socket_mPGA603/chip.h: again
socket_mPGA603/socket_mPGA603_400Mhz.c: and again
socket_mPGA604_533Mhz/Config.lb: Conditionally defing CONFIG_CHIP_NAME
socket_mPGA604_800Mhz/chip.h: Another spelling fix
socket_mPGA604_800Mhz.c     and again
via/model_centaur/model_centaur_init.c: It's not an intel CPU so don't worry about Intel microcode uptdates
earlymtrr.c:  Remove work around for older versions of romcc
pci_ids.h:  More ids.
malloc.c:   We don't need string.h any longer
uart8250.c: Be consistent when delcaring functions static inline
arima/hdama/mptable.c: Cleanup to be a little more consistent
amdk8/coherent_ht.c:
 - Talk about nodes not cpus (In preparation for dual cores)
 - Remove clear_temp_row (as it is no longer needed)
 - Demoted the failure messages to spew.
 - Modified to gracefully handle failure (It should work now if cpus are removed)
 - Handle the non-SMP case in verify_mp_capabilities
 - Add clear_dead_routes which replaces clear_temp_row and does more
 - Reorganize setup_coherent_ht_domain to cleanly handle failure.
 - incoherent_ht.c: Clean up the indenation a little.
i8259.c: remove blank lines at the start of the file.
keyboard.c: Make pc_keyboard_init static
ramtest.c: Add a print out limiter, and cleanup the printout a little.
amd8111/Config.lb: Mention amd8111_smbus.c
amd8111_usb.c: Call the structure usb_ops not smbus_ops.
NSC/pc97307/chip.h: Fix spelling issue
pc97307/superio.c: Use &ops no &pnp_ops.
w83627hf/suerio.c: ditto
w83627thf/suerio.c: ditto
buildrom.c: Use braces around the body of a for loop.  It's more maintainable.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-11 06:53:24 +00:00
Ronald G. Minnich 52c2277a1b adl855pc support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1772 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-10 15:12:48 +00:00
Eric Biederman 018d8dd60f - Update abuild.sh so it will rebuild successfull builds
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
  enabled.  All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-04 11:04:33 +00:00
Yinghai Lu bf8bb42d6a *** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-11-02 18:05:22 +00:00
Eric Biederman f8a2dddb57 - To reduce confuse rename the parts of linuxbios bios that run from
ram linuxbios_ram instead of linuxbios_c and linuxbios_payload...
- Reordered the linker sections so the LinuxBIOS fallback image can take more the 64KiB on x86
- ROM_IMAGE_SIZE now will work when it is specified as larger than 64KiB.
- Tweaked the reset16.inc and reset16.lds to move the sanity check to see if everything will work.
- Start using romcc's built in preprocessor (This will simplify header compiler checks)
- Add helper functions for examining all of the resources
- Remove debug strings from chip.h
- Add llshell to src/arch/i386/llshell (Sometime later I can try it...)
- Add the ability to catch exceptions on x86
- Add gdb_stub support to x86
- Removed old cpu options
- Added an option so we can detect movnti support
- Remove some duplicate definitions from pci_ids.h
- Remove the 64bit resource code in amdk8/northbridge.c in preparation for making it generic
- Minor romcc bug fixes


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-30 08:05:41 +00:00
Eric Biederman dfde9bb649 - Actually enable the Pentium-M cpus
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:47 +00:00
Eric Biederman 3566b3d545 - Bug fixes to the P-III support
- Initial Pentium-M support


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1718 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-27 01:18:16 +00:00
Yinghai Lu fb198640d8 ops and tsc
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-25 19:55:30 +00:00
Eric Biederman 60216355d2 - With Xeon cpus it seems best to use the tsc calibrated with timer2 as
the time source.  The apic timer also has a variable time base.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-23 02:47:13 +00:00
Yinghai Lu 2560dbdd50 for S2735 support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 21:33:08 +00:00
Yinghai Lu ccf0bc01aa s2735 half update
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-22 18:45:36 +00:00
Eric Biederman dbec2d4090 - Bump the LinuxBIOS major version
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-21 10:44:08 +00:00
Eric Biederman 7003ba4a88 - First stab at running linuxbios without the old static device tree.
Things are close but not quite there yet.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-16 06:20:29 +00:00
Eric Biederman fcd5ace00b - Add new cvs code to cvs
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2004-10-14 19:29:29 +00:00